KR100869354B1 - Phase change random access momory device and method for fabricating the same - Google Patents

Abstract

The operating current can be remarkably reduced by reducing the contact area between the phase change material layer and the first electrode. The first electrode having a lager size than the target can be patterned without using the ArF photosensitive film and hard mask structure. The phase change memory device comprises as follows. The first electrode(28) is buried in the contact hole in the interlayer insulating film. The insulating layer(24,26,29) has the stepped contact area whose part for exposing the first electrode becomes narrow. The phase change material layer(32) is buried in the stepped contact area. The second electrode(33) is formed on the phase change material layer. The stepped contact area of the insulating layer is formed as the step type structure. The step type structure has the first contact area(31A) for exposing a part surface of the first electrode and a wider width than the first contact area. The first and the second film are a oxide layer.

Description

PHASE CHANGE RANDOM ACCESS MOMORY DEVICE AND METHOD FOR FABRICATING THE SAME

1A is a structural cross-sectional view of a phase change memory device according to the prior art.

Figure 1b is a detailed view showing the contact area between the first electrode and the phase change material layer according to the prior art.

2A is a structural cross-sectional view of a phase change memory device according to an embodiment of the present invention.

FIG. 2B is a cross-sectional view for describing an operation of the phase change memory device shown in FIG. 2A.

3A to 3E are cross-sectional views illustrating a method of manufacturing a phase change memory device according to an embodiment of the present invention.

4 is a plan view illustrating a contact area between a first electrode and a phase change material layer according to an exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 substrate 22 device isolation film

23 impurity region 24 first interlayer insulating film

25 contact plug 26 second interlayer insulating film

28: first electrode 29: third interlayer insulating film

31A: first contact area 31B: second contact area

32: phase change material layer 33: second electrode

The present invention relates to a memory device, and more particularly, to a nonvolatile memory device using a phase change material and a method of manufacturing the same.

Recently, a phase change memory device (PRAM) has been proposed as a new semiconductor device. The phase change memory device has a nonvolatile characteristic in which stored data is not destroyed even when power supply is interrupted.

The unit cell of the phase change memory device (PRAM) uses a phase change material as a data storage medium. The phase change material has two stable states (amorphous state and crystalline state) depending on the heat provided. Commonly known phase change materials are GST (Ge-Sb-Te), a compound of germanium (Ge), stevilium (Sb) and tellurium (Te).

If the GST is heated at a temperature close to the melting temperature for a short time and then rapidly cooled, the GST becomes amorphous. In contrast, when GST is heated for a long time at a low crystallization temperature compared to the melting temperature and then gradually cooled, the GST changes to a crystalline state. At this time, the GST in the amorphous state has a higher specific resistance than the GST in the crystalline state. Accordingly, the amount of current flowing through the phase change material may be sensed to determine whether the information stored in the cell of the phase change memory device is a logic "1" (amorphous state) or a logic "0" (crystal state).

The heat supplied to the phase change material uses Joule's heat. That is, Joule heating is generated from the electrode by supplying current to the electrode connected to the phase change material to supply heat to the phase change material. The temperature of the heat supplied to the phase change material may vary depending on the amount of current supplied.

1A is a cross-sectional view of a structure of a phase change memory device according to the prior art, and FIG. 1B is a detailed view illustrating a contact area between a first electrode and a phase change material layer according to the prior art.

Referring to FIG. 1A, a phase change memory device according to the related art has a phase formed on a second interlayer insulating film 16 having a first electrode 17 embedded therein and a second interlayer insulating film 16 having a first electrode 17 embedded therein. A second electrode 19 formed on the change material layer 18 and the phase change material layer 18 is included. A contact plug 15 formed in the first interlayer insulating layer 14 is connected under the first electrode 17, and a substrate 11 on which an impurity region 13 is formed is positioned below the contact plug 15. . The impurity regions 13 are separated from each other by the device isolation film 12.

In the conventional phase change memory device as shown in FIG. 1A, the first electrode 17 is reduced in size so that the phase change may occur even when a low current (low operating current) is applied as the integration and low power are increased. That is, the area of overlap between the first electrode 17 and the phase change material layer 18 is reduced.

In the prior art of FIG. 1A, the first electrode 17 and the phase change material layer 18 are reduced by reducing the width of the first electrode 17 to 'A1' smaller than the set width A, as shown in FIG. 1B. Reducing the area of contact between them.

In order to reduce the width of the first electrode 17, a contact hole 17A in which the first electrode 17 is embedded is patterned using an ArF photosensitive film, or a desired size is used using a hard mask structure. ) Pattern the contact hole 17A in which the first electrode 17 is to be filled.

However, in the related art, in order to reduce the contact area between the first electrode and the phase change material layer, the size of the first electrode is inevitably reduced. For this purpose, a contact hole in which the first electrode is buried is formed by using an ArF photosensitive film and a hard mask structure. Since patterning has to be performed, there is a problem in that a manufacturing cost of the phase change memory device increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and a phase change memory device capable of reducing the contact area between the first electrode and the phase change material layer without reducing the size of the first electrode, and a manufacturing method thereof. The purpose is to provide.

Another object of the present invention is to provide a phase change memory device capable of patterning a first electrode with a larger size than a desired target without using an ArF photosensitive film and a hard mask structure, and a method of manufacturing the same.

A phase change memory device of the present invention for achieving the above object comprises a first electrode embedded in a contact hole in an interlayer insulating film; An insulating film providing a stepped contact region in which a portion exposing the first electrode is narrowed; A phase change material layer embedded in the stepped contact region; And a second electrode formed on the phase change material layer, wherein the stepped contact region of the insulating layer is formed on the first contact region and the first contact region exposing a part of the surface of the first electrode. And a second contact region having a width greater than that of the first contact region to form a stepped structure, wherein the insulating layer provides a first layer providing the first contact region and the second contact region. And a second film, wherein the first film is a PETEOS film, and the second film is a PSG film.

In addition, the method of manufacturing a phase change memory device may include forming a contact hole by etching an interlayer insulating layer on a substrate; Forming a first electrode embedded in the contact hole; Forming an insulating film on the first electrode; Etching a portion of the insulating layer to form a stepped contact region in which a portion exposing the first electrode is narrowed; Forming a phase change material layer buried in the contact region; And forming a second electrode on the phase change material layer, wherein the stepped contact region is formed by wet etching the insulating film after forming a photoresist pattern on the insulating film. The insulating film may be formed by stacking layers having different wet etch rates with respect to the same wet chemical, and the insulating film may have a first wet etching rate greater than that of the first film. And a first layer is a PETEOS film, and the second film is a PSG film.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

FIG. 2A is a cross-sectional view of a phase change memory device according to an embodiment of the present invention, and FIG. 2B is a cross-sectional view for describing an operation of the phase change memory device shown in FIG. 2A.

As shown in FIG. 2A, the phase change memory device according to the embodiment of the present invention has a third step that provides a stepped contact region in which a portion exposing the first electrode 28 and the first electrode 28 is narrowed. An interlayer insulating layer 29, a phase change material layer 32 embedded in a stepped contact region, and a second electrode 33 formed on the phase change material layer 32 are included. In addition, the first electrode 28 is formed in the second interlayer insulating layer 26, and a contact plug 25 formed in the first interlayer insulating layer 24 is connected to the bottom of the first electrode 28. 25) an impurity region 23 is connected below. The impurity regions 23 are separated from each other by the device isolation layer 22 and are formed in the substrate 21, and the impurity regions 23 correspond to source and drain regions of the transistor.

In FIG. 2A, the stepped contact region has a width greater than that of the first contact region 31A on the first contact region 31A and the first contact region 31A exposing the surface of the first electrode 28. It consists of two contact areas 31B. Here, the width B1 of the first contact region 31A is smaller than the width B2 of the second contact region 31B, and the width B1 of the first contact region 31A is the width of the first electrode 28. It has a width smaller than the width B3. In addition, the width B2 of the second contact region 31B has the same width as that of the first electrode 28.

The third interlayer insulating film 29 that provides the stepped contact region is a stack structure of films having different etching rates. The third interlayer insulating film 29 includes the first film 29A and the second film 29B. It includes. Here, the first film 29A and the second film 29B are films having different wet etch rates, such as an oxide film (first film), an oxide film (second film), a nitride film (first film), and an oxide film (second film). Film), a polysilicon film (first film) and an oxide film (second film). Polysilicon films are known to be insulating films when impurities are not doped.

Preferably, the first layer 29A and the second layer 29B constituting the third interlayer insulating layer 29 may be formed of silicon oxide (SiO ₂ ), in particular, plasma enhanced tetra ethyl ortho silicate (PETOS) and phospho silicate glass (PSG). It includes a film. When the first layer 29A is PETEOS, the second layer 29B has a larger wet etching rate than the PETEOS layer, and when the second layer 29B is a PSG layer, the first layer 28A has a smaller wet etching rate than the PSG layer. That's it. Preferably, the first film 29A is a PETEOS film, the second film 29B is a PSG film, and the PETEOS film has a smaller wet etch rate than the PSG film. The difference in wet etch rate is due to the wet chemical of the oxide film. Wet chemicals are HF or Buffered Oxide etchant (BOE) solutions. As a result, the third interlayer insulating film 29 may have a stacked structure of a PETEOS film and a PSG film having different wet etch rates.

Preferably, the third interlayer insulating film 29 may be formed of insulating films of different materials. For example, the second layer 29B may be any one selected from PETEOS, PSG, Tetra Ethyl Ortho Silicate (TEOS), Undoped Silicate Glass (USG), Spin On Glass (SOG), or High Density Plasma Chemical Vapor Deposition (HDP-CVD). The first film 29A can be used as the nitride film or the polysilicon film. In this case, wet chemicals are used differently to form a stepped contact region. When wet etching the oxide film used as the second film 29B to form the second contact region 31B, hydrofluoric acid or BOE solution is used, and the first film 29A to form the first contact region 31A. The nitride film used as) is a phosphoric acid (H ₃ PO ₄ ) solution, and in the case of a polysilicon film, a mixture of nitric acid (HNO ₃ ) and hydrofluoric acid (HF) is used. The first film 29A and the second film 29B have the same thickness. Thus, the depths of the first contact region 31A and the second contact region 31B may be the same.

The first and second interlayer insulating films 24 and 26 may be any one selected from tetra ethyl ortho silicate (TEOS), undoped silicate glass (USG), spin on glass (SOG), or high density plasma chemical vapor deposition (HDP-CVD). Oxide film.

The first electrode 28 is also referred to as a heating electrode or a lower electrode. The first electrode 28 is a physical vapor deposition method such as chemical vapor deposition (CVD) or sputtering using a compound such as doped polysilicon, a metal such as tantalum, copper, tungsten, titanium, aluminum, or a nitride thereof. It can form by (PVD) or an atomic layer lamination method (ALD).

The phase change material layer 32 may be formed by a sputtering method using a chalcogenide compound. Here, the chalcogenide compound uses germanium-antimony-tellurium (GST). In addition, the phase change material layer 32 is 5A such as arsenic-antimony-tellurium, tin-antimony-tellurium, tin-indium-antimony-tellurium, arsenic-germanium-antimony-tellurium, tantalum, niobium to vanadium and the like. Group 6A-antimony-tellurium, such as group element-antimony-tellurium, tungsten, molybdenum to chromium, etc., group 5A element-antimony-selenium, group 6A element-antimony-selen, and the like. Preferably, the phase change material layer 32 uses germanium-antimony-tellurium (GST).

The second electrode 33 is formed using a metal nitride film such as titanium nitride film (TiN), a metal film such as titanium or tungsten, or a metal silicide film such as titanium silicide film.

A method of programming or erasing the phase change memory device shown in FIG. 2A will be described with reference to FIG. 2B. An operating current for a program operation or an erase operation is supplied to the first electrode 28. Accordingly, Joule heat is generated from the first electrode 28 and heat is supplied to the phase change material layer 32 through a surface in contact with the first electrode 28 of the phase change material layer 32. As a result, the program region 32A of the phase change material layer 32 changes into an amorphous state or a crystalline state according to the amount of current supplied and the supply time of the current.

The present invention can significantly reduce the volume of the program region 32A by reducing the contact area between the first electrode 28 and the phase change material layer 32, and thus the heat to be provided in the program region 32A. Can be reduced. As a result, the amount of operating current of the phase change memory device can be significantly reduced.

In the phase change memory device shown in FIG. 2A, the third interlayer insulating film 29 having the phase change material layer 32 embedded therein may be formed in a stack structure of oxide films having different wet etch rates or formed of different materials to change phase. By forming the contact region in which the material layer 32 is embedded in a stepped structure that becomes narrower toward the bottom, the contact area between the phase change material layer 32 and the first electrode 28 can be reduced.

3A to 3E are cross-sectional views illustrating a method of manufacturing a phase change memory device according to an embodiment of the present invention.

As shown in FIG. 3A, a plurality of transistors having impurity regions 23 are formed in the substrate 21. Although not shown, the transistor includes another impurity region and also includes a gate. Here, the impurity region 23 corresponds to the source region and the drain region of the transistor, and is separated by the device isolation film 22.

Subsequently, a first interlayer insulating film 24 is formed on the substrate 21. Here, the first interlayer insulating film 24 is any one oxide film selected from tetra ethyl ortho silicate (TEOS), undoped silica glass (USG), spin on glass (SOG), or high density plasma chemical vapor deposition (HDP-CVD). .

Subsequently, a part of the first interlayer insulating layer 24 is etched through a photolithography process to form a contact hole exposing a part of the impurity region 22, and then a contact plug 25 is formed to fill the contact hole. Here, the contact plug 25 is formed using a conductive film such as a polysilicon film doped with impurities, copper, tantalum, tungsten or aluminum, and after the conductive film is deposited, a chemical mechanical polishing process, an etch back ( It is formed by removing until the upper surface of the first interlayer insulating film 24 is exposed by an etching process or a combination thereof.

As described above, the formed contact plug 25 is a plug to which a subsequent first electrode is connected. Although not illustrated, the bit line process may be performed after the contact plug 25 is formed.

Next, a second interlayer insulating film 26 is formed on the first interlayer insulating film 24 having the contact plug 25 embedded therein. Here, the second interlayer insulating film 26 is an oxide film selected from TEOS, USG, SOG, or HDP-CVD, similarly to the first interlayer insulating film 24.

Subsequently, the second interlayer insulating layer 25 is partially etched by a conventional photolithography process to form a contact hole 27 partially exposing the top surface of the contact plug 25. In this case, the width of the contact hole 27 may be the same as the width of the contact plug 25.

As described above, the contact hole 27 is a region in which the first electrode is to be buried, and does not use an ArF photosensitive film and a hard mask structure, and is formed by using an inexpensive photosensitive film such as a conventional KrF photosensitive film as an etching barrier. Thus, the present invention does not need to pattern the size of the contact hole small as in the prior art.

As shown in FIG. 3B, a conductive film filling the contact hole 27 is formed on the second interlayer insulating film 26 having the contact hole 27. Here, the conductive film is a physical vapor deposition method (PVD), such as chemical vapor deposition (CVD), sputtering method using a metal such as doped polysilicon, tantalum, copper, tungsten, titanium, aluminum, or nitrides thereof. Or it can form by atomic layer lamination method (ALD).

Next, the conductive film is removed until the top surface of the second interlayer insulating film 26 is exposed to form the first electrode 28 filling the contact hole 27. The first electrode 28 functions as a lower electrode electrically connecting the subsequently formed phase change material layer to the contact plug 25.

As shown in FIG. 3C, a third interlayer insulating film 29 is formed on the second interlayer insulating film 26 having the first electrode 28 embedded therein. In this case, the third interlayer insulating film 29 is a stacked structure of films having different etching rates, and the third interlayer insulating film 29 includes a first film 29A and a second film 29B. Here, the first film 29A and the second film 29B are films having different wet etch rates, such as an oxide film (first film), an oxide film (second film), a nitride film (first film), and an oxide film (second film). Film) or a polysilicon film (first film) and an oxide film (second film). Polysilicon films are known to be insulating films when impurities are not doped.

Preferably, the first layer 29A and the second layer 29B constituting the third interlayer insulating layer 29 may be formed of silicon oxide (SiO ₂ ), in particular, plasma enhanced tetra ethyl ortho silicate (PETOS) and phospho silicate glass (PSG). It includes a film. When the first layer 29A is PETEOS, the second layer 29B has a larger wet etching rate than the PETEOS layer, and when the second layer 29B is a PSG layer, the first layer 28A has a smaller wet etching rate than the PSG layer. That's it. Preferably, the first film 29A is a PETEOS film, the second film 29B is a PSG film, and the PETEOS film has a smaller wet etch rate than the PSG film. The difference in wet etch rate is due to the wet chemical of the oxide film. Wet chemicals are HF or Buffered Oxide etchant (BOE) solutions. As a result, the third interlayer insulating film 29 is a laminated structure of a PETEOS film and a PSG film having different wet etch rates.

Preferably, the third interlayer insulating film 29 may use the second film 29B as an oxide film and the first film 29A as a nitride film or a polysilicon film. In this case, wet chemicals are used differently in the formation of subsequent stepped contact regions. When wet etching the oxide film used as the second film 29B, a hydrofluoric acid or BOE solution is used, and the nitride film used as the first film 29A uses a phosphoric acid (H ₃ PO ₄ ) solution and is a polysilicon film. In this case, a mixture of nitric acid (HNO ₃ ) and hydrofluoric acid (HF) is used. Meanwhile, when the nitride film and the oxide film are stacked, the oxide film and the nitride film may be wet-etched at the same time using hydrofluoric acid (HF). In this case, the hydrofluoric acid has a very large etching rate for the oxide film, while the etching rate for the nitride film is smaller than that of the oxide film.

The first film 29A and the second film 29B have the same thickness. As a result, the depths of the first contact region and the second contact region which are formed subsequently may be the same.

Subsequently, a photosensitive film pattern 30 is formed on the third interlayer insulating film 29. In this case, the photoresist pattern 30 is used to define a contact region in which the phase change material layer is to be embedded, and the width of the opening 30A provided in the photoresist pattern 30 may be the same as that of the first electrode 28. Can be. In addition, the photoresist pattern 30 also serves to prevent the underlying structure from being attacked during the subsequent wet etching process.

The opening 30A of the photosensitive film pattern 30 described above is circular in shape, and the first electrode 28 is also circular. Here, the shape of the first electrode 28 and the opening shape of the photoresist pattern 30 may have various shapes.

Subsequently, wet etching is performed. At this time, the wet etching is performed using HF or BOE solution. The second contact region 31B having a larger width than the first contact region 31A on the first contact region 31A and the first contact region 31A exposing a part of the surface of the first electrode 28 by wet etching. ) Is formed at the same time. Thus, the first contact region 31A and the second contact region 31B form a stepped contact region. Preferably, since the first contact region 31A has a narrower width, the first contact region 31A and the second contact region 31B have a narrower width. The portion exposing the surface of the electrode 28 becomes a stepped contact region that becomes narrow.

Since the second layer 29B is the PSG layer, the wet etching rate is greater than that of the first layer 29A, which is the PETEOS layer. Therefore, the first contact region 31A formed after etching the first layer 29A is smaller in width than the second contact region 31B provided for etching the second layer 29B. That is, the width B1 of the first contact region 31A is smaller than the width B2 of the second contact region 31B. In addition, the width B1 of the first contact region 31A has a width smaller than the width B3 of the first electrode 28, and the width B2 of the second contact region 31B is the first electrode 28. Have the same width as).

As a result, the contact region exposing the surface of the first electrode 28 is composed of the first contact region 31A and the second contact region 31B, and the width of the lower first contact region 31A is smaller so that the contact region is stepped. A contact region is formed. As such, by forming the stepped contact region having the narrow first contact region 31A, the contact area between the phase change material layer and the first electrode 28 embedded in the subsequent stepped contact region can be reduced. This means that it is not necessary to adjust the size of the first electrode 28 in advance, and therefore, there is no need to use a costly ArF photosensitive film and a hard mask structure.

As shown in FIG. 3D, the photoresist pattern 30 is removed.

Subsequently, after the phase change material layer 32 is formed to fill the first contact region 31A and the second contact region 31B, the planarization process is performed. The phase change material layer 32 may be formed by a sputtering method using a chalcogenide compound. Here, the chalcogenide compound uses germanium-antimony-tellurium (GST). In addition, the phase change material layer 32 is 5A such as arsenic-antimony-tellurium, tin-antimony-tellurium, tin-indium-antimony-tellurium, arsenic-germanium-antimony-tellurium, tantalum, niobium to vanadium and the like. Group 6A-antimony-tellurium, such as group element-antimony-tellurium, tungsten, molybdenum to chromium and the like, group 5A element-antimony-selen, or group 6A element-antimony-selen and the like. Preferably, the phase change material layer 32 uses germanium-antimony-tellurium (GST).

As shown in FIG. 3E, the second electrode 33 is formed on the phase change material layer 32. The second electrode 33 is formed using a metal nitride film such as titanium nitride film (TiN), a metal film such as titanium or tungsten, or a metal silicide film such as titanium silicide film.

4 is a plan view illustrating a contact area between a first electrode and a phase change material layer according to an exemplary embodiment of the present invention.

Referring to FIG. 4, a plurality of circular first electrodes 28 are arranged at regular intervals, and one second electrode 33 corresponding to the plurality of first electrodes 28 is formed. A circular phase change material layer 32 is in contact with the first electrode 28. The phase change material layer 32 and the first electrode 28 have a small contact area by the first contact region 31A. do.

According to the embodiment described above, the present invention is a phase change material by forming the third interlayer insulating film 29 in which the phase change material layer 32 is embedded in a stacked structure of oxide films having different wet etch rates or formed of different materials. By forming the contact region in which the layer 32 is embedded in a stepped structure, the contact area between the phase change material layer 32 and the first electrode 28 can be reduced.

In addition, since the contact region in which the phase change material layer 32 is embedded is formed in a stepped structure, a hard mask structure and an ArF photosensitive film may not be used when patterning the first electrode 28. That is, since the first electrode 28 can be patterned to a larger size than the desired target, the KrF photosensitive film can be applied, and there is no need to use a hard mask structure. As a result, the burden Buden for reducing the size of the first electrode 28 is reduced.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the interlayer insulating film in which the phase change material layer is embedded is formed in a laminated structure of oxide films having different wet etch rates or formed of different materials to form a contact region in which the phase change material layer is embedded in a stepped structure. In addition, the contact area between the phase change material layer and the first electrode can be reduced to significantly reduce the operating current.

In addition, the present invention can reduce the contact area between the first electrode and the phase change material layer by forming a contact region in which the phase change material layer is embedded in a stepped structure, so that the first electrode can be patterned to a larger size than a desired target. The KrF photosensitive film can be applied, and there is no need to use a hard mask structure. As a result, an effect of reducing the burden for reducing the size of the first electrode can be expected.

Claims (25)

A first electrode embedded in a contact hole in the interlayer insulating film; An insulating film providing a stepped contact region in which a portion exposing the first electrode is narrowed; A phase change material layer embedded in the stepped contact region; And A second electrode formed on the phase change material layer Phase change memory device comprising a. The method of claim 1, The stepped contact region of the insulating film, And a second contact region forming a stepped structure having a width greater than that of the first contact region on the first contact region and exposing a first surface of the first electrode. The method of claim 2, The width of the first contact region has a width smaller than the width of the first electrode. The method of claim 2, The width of the second contact region has a width equal to the width of the first electrode. The method of claim 2, The insulating film, And a second layer providing the first contact region and a second layer providing the second contact region. The method of claim 5, And the first and second layers are oxide films. The method of claim 6, And the first layer is an oxide layer having a smaller wet etch rate than the second layer. The method of claim 5, The first film is a PETEOS film, and the second film is an oxide film having a larger wet etching rate than the PETEOS film. The method of claim 5, The second film is a PSG film, and the first film is an oxide film having a smaller wet etch rate than the PSG film. The method of claim 5, The first film is a PETEOS film, and the second film is a PSG film. The method of claim 5, And the second film is an oxide film, and the first film is a nitride film or a polysilicon film. The method of claim 11, The second layer is a phase change of any one oxide film selected from PETEOS, PSG, Tetra Ethyl Ortho Silicate (TEOS), Undoped Silicate Glass (USG), Spin On Glass (SOG), or High Density Plasma Chemical Vapor Deposition (HDP-CVD). Memory device. Forming a contact hole by etching the interlayer insulating layer on the substrate; Forming a first electrode embedded in the contact hole; Forming an insulating film on the first electrode; Etching a portion of the insulating layer to form a stepped contact region in which a portion exposing the first electrode is narrowed; Forming a phase change material layer buried in the contact region; And Forming a second electrode on the phase change material layer Phase change memory device manufacturing method comprising a. The method of claim 13, The stepped contact region, And forming a photoresist pattern on the insulating layer, followed by wet etching the insulating layer. The method of claim 13, The insulating film, A method of manufacturing a phase change memory device in which a wet etching rate is formed in a stacked structure of films having different wet etch rates for the same wet chemical. The method of claim 15, The insulating film, A method of manufacturing a phase change memory device having a stacked structure of a first film and a second film having a larger wet etch rate than the first film. The method of claim 16, And the first and second films are oxide films. The method of claim 17, The first film is a PETEOS (Plasma Enhanced Tetra Ortho Etyl Silicate) film, and the second film is an oxide film having a larger wet etching rate than the PETEOS film. The method of claim 17, And the second layer is a PSG layer, and the first layer is an oxide layer having a smaller wet etch rate than the PSG (Phospho Silicate Glass) layer. The method of claim 17, The first film is a PETEOS film, and the second film is a PSG film manufacturing method. The method of claim 13, The insulating film, A method of manufacturing a phase change memory device in which films having different wet chemicals are applied to form a stacked structure. The method of claim 21, And the insulating film is formed in a stacked structure of a nitride film and an oxide film. The method of claim 21, And the insulating film is formed in a stacked structure of a polysilicon film and an oxide film. The method of claim 22 or 23, The oxide film, A method of manufacturing a phase change memory device, which is any one selected from PETEOS, PSG, Tetra Ethyl Ortho Silicate (TEOS), Undoped Silicate Glass (USG), Spin On Glass (SOG), or High Density Plasma Chemical Vapor Deposition (HDP-CVD). The method of claim 13, Forming the stepped contact region, And a photoresist pattern having an opening having a width equal to that of the first electrode is used as an etch barrier.

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