KR20070120242A - Method of forming a contact and method of manufacturing a phase-changeable memory device using the same - Google Patents

Abstract

A method for forming a contact is provided to form a contact with an improved structure and an increased electrical characteristic by removing a titanium/titanium nitride layer remaining on the sidewall of a contact hole while using a cleaning solution. An insulation is formed on a silicon substrate(200), having a contact hole exposing part of the substrate. The inside of the contact hole is filled with a resistive material. The resistive material is partially etched to make the resistive material left only on the bottom surface of the contact hole so that a resistive material pattern is formed. The resistive material remaining on the sidewall of the contact hole is eliminated by using a cleaning solution. A conductive layer is formed on the resistive material pattern to completely fill the contact hole. In the cleaning solution, the volume ratio of nitric acid, phosphoric acid and acetic acid mixed with water is 75:15:1.

Description

A contact forming method and a method of manufacturing a phase change memory device using the same. {Method of forming a contact and method of manufacturing a phase-changeable memory device using the same}

1 to 5 are schematic cross-sectional views illustrating a method for forming a contact according to an embodiment of the present invention.

6 to 17 are schematic cross-sectional views illustrating a method of manufacturing a phase change memory device according to another exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

200 semiconductor substrate 212 gate structure

220: lower interlayer insulating film 222, 224: first and second contact pads

228 conductive pattern 232a first opening

236: lower electrode 238: titanium / titanium nitride film

240: cobalt silicide pattern 246: phase change material layer

252: upper electrode 254: upper wiring

The present invention relates to a pattern forming method and a method of manufacturing a phase change memory device using the same. A method for manufacturing a device.

The semiconductor memory device is generally classified into a volatile semiconductor memory device such as a DRAM device or an SRAM device and a nonvolatile semiconductor memory device such as a flash memory device or an EEPROM device when a power supply is interrupted. Can be. As a semiconductor memory device used in a device such as a digital camera, a mobile phone or an MP3 player, a flash memory device which is a nonvolatile memory device is mainly used. However, since flash memory devices require a relatively long time in writing or reading data, new semiconductor devices such as MRAM, FRAM or PRAM devices have been developed to replace such flash devices.

A PRAM device, which is one of nonvolatile semiconductor memory devices, stores data using a difference in resistance between an amorphous state and a crystal state due to a phase transition of a chalcogenide compound. That is, the PRAM device uses a reversible phase transition of a phase change material layer made of a chalcogenide compound, GST (Ge ₂ Sb ₂ Te ₅ ), according to the amplitude and length of an applied pulse. And save it as "1". In other words, the reset current required for the transition to a large amorphous state and the set current for changing to a low resistance crystal state are transferred from the underlying transistor through a lower electrode having a smaller size to a phase change material. Transfer to the layer causes a phase change. An upper region of the lower electrode is connected to a phase change material layer, and the lower region is connected to a contact in contact with the transistor. In this case, the contact should be made of ohmic contact with low resistance.

In more detail, as the integration increases, the width of the contact decreases while the thickness of the interlayer insulating layer increases, thereby increasing the aspect ratio of the contact. As the area of the contact bottom decreases, the interface resistance of the contact bottom increases. As the contact resistance increases, the current driving capability is greatly reduced, and as the current driving capability decreases, the speed of the semiconductor device is reduced.

In order to solve the above problems, a low-resistance cobalt silicon film is formed on the bottom of the contact hole, and then a conductive film for contact is formed to form an ohmic contact with low resistance.

In more detail, first contact holes exposing the surface of the first conductive patterns on the substrate on which the first conductive patterns including silicon and the second conductive patterns including metal are formed, and the second conductive layer. An interlayer insulating film including second contact holes exposing the surface of the pattern is formed. Subsequently, metal barrier films including a cobalt film and a titanium / titanium nitride film are sequentially formed on the first and second contact holes and the interlayer insulating film. A silicidation process is performed in which cobalt silicide is formed on bottom surfaces of first contact holes exposing the first conductive patterns by reacting the metal barrier layer with silicon included in the first conductive pattern.

Subsequently, after the metal barrier film which has not reacted to the formation of the cobalt silicide film formed on the bottom surface of the contact hole is removed by an etching process, a contact hole conductive film is formed.

At this time, due to the high integration, due to the limitations of the etching process and the etching selectivity problem, the titanium / titanium nitride film may not remain completely removed on the sidewall of the contact hole. It is difficult to constantly adjust the residual amount of the titanium / titanium nitride film, and the lower electrode formed in the contact hole becomes uneven. As a result, the electrical characteristics of the lower electrode are lowered and the characteristics of the phase change memory device including the lower electrode are deteriorated.

It is a first object of the present invention to provide a method for forming a contact having improved electrical properties through structural improvement.

It is a second object of the present invention to provide a method of manufacturing a phase change memory device having improved electrical characteristics by using the contact forming method.

In order to achieve the first object of the present invention, a contact forming method according to an embodiment of the present invention, forming an insulating film having a contact hole for exposing a portion of the substrate on a silicon substrate, and the resistive inside the contact hole A resistive material pattern is formed by partially etching the resistive material so that the resistive material is only embedded in the material, and the resistive material is present only at the bottom of the contact hole. Subsequently, after the resistive material remaining on the contact hole sidewall is removed using a cleaning solution, a conductive film is formed on the resistive material pattern so as to completely fill the contact hole.

At this time, the cleaning solution, the nitric acid, phosphoric acid, and acetic acid mixed in water has a volume ratio of 75: 15: 1, and the resistive material includes titanium and titanium nitride film.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a phase change memory device, including forming an interlayer insulating film on a substrate and forming a contact hole exposing a conductive region to the interlayer insulating film. A resistive material is formed in the contact hole. Subsequently, by partially etching the resistive material so that the resistive material is present only on the bottom of the contact hole, a resistive material pattern is formed, and the resistive material remaining on the sidewall of the contact hole is removed using a cleaning solution, and the resistive material is removed. The lower electrode, the phase change material film, and the upper electrode are sequentially formed on the pattern.

The resistive material includes titanium and a titanium nitride film, and the cleaning solution has a volume ratio of 75: 15: 1 of nitric acid, phosphoric acid, and acetic acid mixed with water. In this case, before forming the resistive material, a metal film is continuously formed on the contact hole and the interlayer insulating layer, and a metal silicide pattern is selectively formed on the bottom surface of the contact hole by reacting the metal included in the metal film with the silicon. To form. The metal layer may include cobalt, the metal silicide pattern may include cobalt silicide, and the phase change material may include a chalcogen compound.

Before forming the lower electrode, the method may further include forming nitride spacers on both sides of the lower electrode.

Before forming the interlayer insulating film, a transistor including a source, a drain, and a gate is formed on the substrate, a lower interlayer insulating film filling the transistor is formed, and the source and the drain are formed in the lower interlayer insulating film. The method may further include forming contact pads to be connected to each other, and forming conductive lines electrically connected to the contact pads to be connected to the drain.

The contact forming method and the method of manufacturing a phase change memory device using the same according to the present invention configured as described above have a small interfacial resistance of the contact by removing the titanium / titanium nitride film, which is a resistive material remaining on the sidewalls of the contact hole, using a cleaning solution. In addition, it is possible to form a contact having no abnormality in current driving, and to manufacture a phase change memory device capable of maintaining a constant electrical characteristic by using the above-described contact forming method.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and those skilled in the art will appreciate the technical spirit of the present invention. The present invention may be embodied in various other forms without departing from the scope of the present invention. In the accompanying drawings, the dimensions of the substrate, film, region, pad or patterns are shown to be larger than the actual for clarity of the invention. In the present invention, each film, region, pad or pattern is referred to as being formed on the "on", "top" or "top surface" of the substrate, each film, region or pads. Meaning that the pad or patterns are formed directly on the substrate, each film, region, pad or patterns, or another film, another region, another pad or other patterns may be additionally formed on the substrate. In addition, where each film, region, pad or pattern is referred to as "first," "second," and / or "third," it is not intended to limit these members but merely to define the respective film, region, pad or patterns To distinguish. Thus, "first", "second" and / or "third" may be used selectively or interchangeably for each film, region, pad or pattern, respectively.

Contact Formation Method

1 to 5 are schematic cross-sectional views illustrating a method for forming a contact according to an embodiment of the present invention.

Referring to FIG. 1, an insulating film (not shown) having a contact hole 104 exposing a portion of the substrate is formed on the silicon substrate 100. The insulating layer may be made of silicon oxide (SiO ₂ ). A photoresist pattern (not shown) is then formed on the insulating film to selectively expose the surface of the insulating film.

The exposed insulating layer is etched using the photoresist pattern as an etch mask to expose the semiconductor substrate 100 to form a contact hole 104. In this case, an insulating layer structure 102 including a contact hole 104 is obtained from the insulating layer by the etching process.

After forming the contact hole 104, the photoresist pattern is removed by an ashing or strip process.

Referring to FIG. 2, the metal layer 106 is continuously formed on the insulating layer structure 102 and the contact hole 104. Cobalt (Co) or the like may be used as the metal included in the metal film 106.

Referring to FIG. 3, a metal included in the metal layer 106, that is, cobalt, reacts with silicon contacting the bottom surface of the contact hole 104, and thus a cobalt silicide (CoSi) pattern 110 is formed on the bottom surface of the contact hole 104. ). In this case, a predetermined heat treatment may be performed to form the cobalt silicide pattern 110.

Meanwhile, the cobalt silicide pattern 110 may be naturally formed by a process of forming a titanium / titanium nitride layer (Ti / TiN, 108). In more detail, first, a titanium / titanium nitride film 108 is formed on the metal film 106 to sufficiently fill the inside of the contact hole (FIGS. 2 and 104).

The titanium / titanium nitride film 108 may be formed using a chemical vapor deposition process (CVD) or a physical vapor deposition process (PVD).

In this case, since the cobalt silicide pattern 110 may be formed by a process temperature for forming the titanium / titanium nitride layer 108, a predetermined heat treatment may be omitted to form the cobalt silicide pattern 110. .

By forming the titanium / titanium nitride film 108 on the cobalt film 106, a cobalt silicide pattern 110 and a titanium / titanium nitride film 108 are stacked in the contact hole (FIGS. 2 and 104). In addition, a cobalt film and a titanium / titanium nitride film 108 are stacked on the insulating film.

Referring to FIG. 4, the cobalt film 106 and the titanium / titanium nitride film 108 formed on the insulating film structure 102 and an additional cobalt silicon titanium film (not shown) are removed. The removal process may be performed by an etching process. As a result, the cobalt silicide pattern 110 and the titanium / titanium nitride layer 108a are stacked on the bottom of the contact hole 104.

Specifically, a dry etching process is performed such that the titanium / titanium nitride film 108 is filled to a predetermined height in the contact hole 104 in order to fill the conductive layer 112 in the contact hole (FIGS. 2 and 104) in a subsequent process. Do this.

In this case, due to the limitation of the etching process and the etching selectivity due to the high integration, the titanium / titanium nitride film remaining on the sidewall of the contact hole 104 may not be effectively removed. In order to remove the titanium / titanium nitride film remaining on the sidewalls of the contact hole, wet cleaning is performed using a PAN cleaning solution. The PAN cleaning solution is a cleaning solution containing phosphoric acid (H ₃ PO ₄ ), acetic acid (CH ₃ COOH) and nitric acid (HNO ₃ ) in a volume of 75: 25: 1, and the etching selectivity between the metal and the metal silicide is increased. high. That is, the metal silicide pattern 110 is hardly removed while the metal is etched and removed, and the titanium / titanium nitride film (not shown) remaining on the sidewalls of the contact hole may be effectively removed.

As a result of the cleaning process, the cobalt silicide pattern 110 and the titanium / titanium nitride layer 108a are formed only on the bottom surface of the contact hole 104 of the insulating layer structure 102 formed on the substrate 100.

Referring to FIG. 5, a contact conductive layer 112 is formed on the insulating layer structure 102 to fill the contact hole 104 to form a contact electrically connected to the semiconductor substrate 100. Typically, the conductive layer 112 includes tungsten (W), titanium aluminum nitride (TiAIN), or the like.

Manufacturing Method of Phase Change Memory Device

6 to 17 are schematic cross-sectional views illustrating a method of manufacturing a phase change memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 6, the device isolation layer 203 may be formed on the semiconductor substrate 200 by using a device isolation process such as a shallow trench isolation (STI) process or a local oxidation of silicon (LOCOS) process. By forming the semiconductor substrate 200, the semiconductor substrate 200 is divided into an active region and a field region.

A gate structure 212 in which a gate insulating layer pattern 206, a gate electrode 208, and a hard mask pattern 210 are stacked on the semiconductor substrate 200 is formed. Nitride is deposited on both sidewalls of the gate structure 212 and the substrate 200 and then etched anisotropically to form gate spacers 214 on both sidewalls of the gate structure 212. The gate electrode 108 may be formed of a single layer such as a doped polysilicon film or a metal film, or may be formed in a multilayer structure including the doped polysilicon film and a metal film.

Next, source / drain regions 216 and 218 are formed by implanting impurities into both sides of the gate structure 212 using the gate structure 212 as an ion implantation mask. Accordingly, a transistor consisting of the source / drain 216 and 218 and the gate structure 212 is formed on the substrate. The transistor serves as a switch in a unit cell of a phase change memory device.

Referring to FIG. 7, a lower interlayer insulating layer 220 is formed on the semiconductor substrate 200 while covering the transistor. The lower interlayer insulating layer 220 is formed by depositing an oxide such as TEOS, USG, SOG, or HDP-CVD. After forming the lower interlayer insulating layer 120, the lower interlayer insulating layer 120 is planarized by using a chemical mechanical polishing (CMP) process, an etch back process, or a combination of chemical mechanical polishing and etch back. The process may be further performed.

Next, the first interlayer insulating layer 220 is partially etched through the photolithography process to form a first contact hole exposing the top surface of the source 216 and a second contact hole exposing the drain (not shown). Form each. A first conductive layer (not shown) is formed to fill the first contact hole and the second contact hole, and the lower interlayer insulating layer 220 is exposed to the surface by a CMP or etch back process. By planarizing as much as possible, the first contact pad 222 and the second contact pad 224 are formed. Examples of the conductive material that may be used as the first conductive layer may include a metal material such as polysilicon doped with impurities or copper, tantalum, tungsten, aluminum, or the like.

Referring to FIG. 8, a second conductive layer (not shown) is formed on the first contact pad 222, the second contact pad 224, and the lower interlayer insulating layer 220. As the second conductive layer, a metal material such as polysilicon doped with impurities or tantalum, tungsten or aluminum may be used. Next, the second conductive film is patterned to form a lower wiring line 226 for connecting with the first contact pad 222 and a conductive pattern 228 for connecting with the second contact pad 224, respectively.

Alternatively, when the lower wiring line 226 and the conductive pattern 228 are formed of copper, a damascene method is typically used. That is, after further depositing an interlayer insulating film, a first opening is formed in a portion where the lower wiring line and the first conductive pattern are to be formed. Next, after embedding a copper film in the first opening, the copper film is polished.

Referring to FIG. 9, a first preliminary interlayer insulating layer 230 is formed on the lower interlayer insulating layer 227 on which the lower wiring line 226 and the conductive pattern 228 are formed. Here, the first preliminary interlayer insulating film 230 is formed by depositing an oxide-based material, and preferably, may be formed using TEOS, USG, SOG, or HDP-CVD oxide. Subsequently, the first preliminary interlayer insulating layer 230 is partially etched by a conventional photolithography process to form a first opening 232 exposing the top surface of the conductive pattern 128.

A silicon oxynitride film is formed along the profile of the upper surface of the first preliminary interlayer insulating film 230 and the first opening 232, and a silicon nitride film is formed on the silicon oxynitride film. Next, the silicon nitride film and the silicon oxynitride film are etched anisotropically until the upper surface of the conductive pattern 228 is exposed to form a preliminary spacer 234 on the sidewall of the first opening 232. When the process is performed as described above, the preliminary spacer 234 has a structure of a double spacer in which a silicon oxynitride layer and a silicon nitride layer are stacked.

Alternatively, a single spacer may be formed on the sidewall of the first opening 232 by depositing and anisotropically etching any one of the silicon oxynitride layer and the silicon oxide layer.

By forming the preliminary spacer 234 as described above, the open size of the first opening 132 may be reduced below the limit resolution of the photo process. Accordingly, the size of the lower electrode formed in the first opening 232 may be reduced, thereby minimizing the size of the programming region, which is a portion in which data is programmed by generating a phase change in the phase change layer pattern. have. As the programming area is reduced, it is possible to reduce the current required to make a phase change.

10 and 11, a metal film 236 is continuously formed on the first opening 232 and the first preliminary interlayer insulating layer 230 on which the spacer 134 is formed. Cobalt (Co) or titanium (Ti) may be used as the metal included in the metal film 236. In this embodiment, cobalt will be used.

Subsequently, a metal included in the metal layer 236, that is, cobalt reacts with silicon contacting the bottom surface of the first opening 232 to form a cobalt silicide (CoSi) pattern 240 on the bottom surface of the first opening 232a. Form. In this case, a predetermined heat treatment may be performed to form the cobalt silicide pattern 240.

Meanwhile, the cobalt implementation side pattern 240 may be naturally formed by a process of forming a titanium / titanium nitride layer (Ti / TiN), which may be omitted. In this case, the heat treatment may be omitted. A titanium / titanium nitride film 238 is formed on the metal film 236 to sufficiently fill the inside of the first opening 232.

The titanium / titanium nitride film 238 may be formed using a chemical vapor deposition process (CVD) or a physical vapor deposition process (PVD).

In the above process, a cobalt silicide pattern 240 and a titanium / titanium nitride film 238 are stacked on the bottom of the first opening 232. A cobalt film 236 and a titanium / titanium nitride film 238 are stacked on the insulating film. In addition, a cobalt silicon titanium film Co _x Si _y Ti _z may be additionally generated.

Referring to FIG. 12, the cobalt film 236 formed on the insulating film 230, the titanium / titanium nitride film 238, and the additionally formed cobalt silicon titanium film are removed by an etching process. As a result, the cobalt silicide pattern 110 and the titanium / titanium nitride layer 108a are stacked on the bottom of the contact hole 104.

Specifically, in order to fill the third conductive layer 242 in the first opening 232 in a subsequent process, dry etching is performed such that the titanium / titanium nitride film 238 is filled to a predetermined height in the first opening 232. Perform the process.

In this case, due to the limitation of the etching process due to the high integration, the dry etching process may not effectively remove the titanium / titanium nitride film formed on the sidewall of the first opening 232.

The remaining amount of the titanium / titanium nitride film remaining on the sidewalls of the first opening 232 is difficult to control, so that a subsequent lower electrode is formed unevenly. As a result, the electrical characteristics of the phase change memory device including the lower electrode may not be maintained constantly. In order to remove the titanium / titanium nitride film (not shown) remaining on the sidewall of the first opening 232, a wet cleaning is performed using a PAN cleaning solution. The PAN cleaning solution is a cleaning solution containing phosphoric acid (H ₃ PO ₄ ), acetic acid (CH ₃ COOH) and nitric acid (HNO ₃ ) in a volume of 75: 25: 1, and the etching selectivity between the metal and the metal silicide is increased. high. That is, while the metal is etched and removed, the cobalt silicide pattern 240 is hardly removed, and the titanium / titanium nitride film remaining on the sidewall of the first opening 232 may be effectively removed.

As a result of the cleaning process, the cobalt silicide pattern 240 and the titanium / titanium nitride film pattern 238a are formed only on the bottom surface of the first opening 232 of the insulating film structure 102 formed on the substrate 200.

By the above cleaning process, the lower electrodes (FIGS. 14 and 236) may be constantly formed, and a phase change memory device having improved electrical characteristics may be manufactured.

13 and 14, a third conductive layer 242 is formed on the first preliminary interlayer insulating layer 230 while filling the first opening (see FIG. 12.123a). Here, the third conductive layer 242 may be formed of a metal such as doped polysilicon, tantalum, copper, tungsten, titanium, aluminum, or the like. Alternatively, it may be formed using a metal nitride such as titanium nitride, titanium titanium nitride, or the like. In the present embodiment, the third conductive film 242 is formed of titanium aluminum nitride.

Next, the third conductive film is planarized by performing a CMP process or an etch back process until the upper surface of the first preliminary interlayer insulating film 230 is exposed. By the above process, the lower electrode 236 filling the first opening 232 is formed. The preliminary lower electrode 136 serves to apply heat by Joule heating to a subsequently formed phase change film pattern. When the process is performed, the upper surface of the preliminary lower electrode 236, the preliminary spacer 234, and the first preliminary interlayer insulating layer 230 are exposed.

Referring to FIG. 15, a phase change material layer 246 is formed on the lower electrode 236 and the first preliminary interlayer insulating layer 230. The phase change material layer 246 deposits the chalcogenide compound by the sputtering method. Here, the chalcogen compound is germanium-antimony-tellurium (Ge-Sb-Te), tin-antimony-tellurium (Sn-Sb-Te), indium-antimony-tellurium (In-Sb-Te), indium Antimony-germanium (Sn-Sb-Ge) -based materials. In addition, the phase change material layer 140 may be formed of a chalcogen compound doped with oxygen or nitrogen. The most suitable chalcogenide compound for use as the phase change material layer 140 is germanium-antimony-tellurium (GST), which is formed to a thickness of about 1000 to 2000 μs.

Next, a capping conductive layer 248 is formed on the phase change material layer 246. The capping conductive layer 248 is formed by depositing titanium or titanium nitride. Alternatively, the capping conductive layer is formed by depositing titanium and then depositing titanium nitride on the titanium.

Referring to FIG. 16, the capping conductive layer 248 and the phase change material layer 246 are partially etched to contact the lower electrode 136a and the capping conductive pattern 248a and the phase change material layer pattern. 246a is formed.

Next, a second interlayer insulating film 250 is formed to fill the capping conductive pattern 248a and the phase change material layer pattern 246a, and a predetermined portion of the second interlayer insulating film 250 is etched to form the image. A second opening exposing the top surface of the change material layer pattern 246a is formed.

A top electrode 252 is formed by filling and planarizing a conductive material in the second opening. The conductive material may be a conductive material, a metal or a metal silicide containing a nitrogen element.

The conductive material containing the nitrogen element may include titanium nitride, tantalum nitride, molybdenum nitride, niobium nitride, titanium-silicon nitride, titanium-aluminum nitride, titanium-boron nitride, zirconium-silicon nitride, tungsten-silicon nitride, tungsten- Boron nitride, zirconium-aluminum nitride, molybdenum-silicon nitride, molybdenum-aluminum nitride, tantalum-silicon nitride, tantalum-aluminum nitride, titanium oxynitride, titanium-aluminum oxynitride, or tungsten oxynitride, tantalum oxynitride.

In addition, the conductive material may be a metal or metal silicide such as titanium, tungsten, molybdenum, tantalum, titanium silicide or tantalum silicide. In addition, any conductive material capable of flowing a sufficient current as a conductor can be used.

Next, an upper wiring 254 connected to the upper electrode 252 is formed to complete a phase change memory device.

As described above, the method for forming a contact according to an embodiment of the present invention may form a contact having an improved structure and improved electrical properties by removing the titanium / titanium nitride film remaining on the sidewall of the contact hole using a cleaning solution. have.

In addition, when the above-described contact forming method is used, there is no abnormality in current driving, constant characteristics are maintained, and a phase change memory device having improved reliability can be manufactured.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (12)

Forming an insulating film having a contact hole exposing a portion of the substrate on a silicon substrate; Filling the inside of the contact hole with a resistive material; Forming a resistive material pattern by partially etching the resistive material such that the resistive material is present only at the bottom of the contact hole; Removing the resistive material remaining on the contact hole sidewalls using a cleaning solution; And And forming a conductive film on the resistive material pattern to completely fill the contact hole. The method of claim 1, wherein the cleaning solution has a volume ratio of 75: 15: 1 in nitric acid, phosphoric acid, and acetic acid mixed with water. The method of claim 1, wherein the resistive material comprises titanium and a titanium nitride film. Forming an interlayer insulating film on the substrate; Forming a contact hole exposing a conductive region in the interlayer insulating film; Forming a resistive material in the contact hole; Forming a resistive material pattern by partially etching the resistive material such that the resistive material is present only at the bottom of the contact hole; Removing the resistive material remaining on the contact hole sidewalls using a cleaning solution; And And sequentially forming a lower electrode, a phase change material film, and an upper electrode on the resistive material pattern. The method of claim 1, wherein the resistive material comprises titanium and a titanium nitride film. The method of claim 4, wherein the cleaning solution has a volume ratio of 75: 15: 1 in nitric acid, phosphoric acid, and acetic acid mixed with water. The method of claim 4, prior to forming the resistive material, And continuously forming a metal film on the contact hole and the interlayer insulating film. The method of claim 6, further comprising forming a metal silicide pattern on the bottom surface of the contact hole by reacting the metal included in the metal film with the silicon. The method of claim 7, wherein the metal layer comprises cobalt, and the metal silicide pattern comprises cobalt silicide. The method of claim 4, wherein the phase change material comprises a chalcogen compound. The method of claim 4, before forming the lower electrode, And forming a nitride spacer on both sides of the lower electrode. The method of claim 4, before forming the interlayer insulating film, Forming a transistor comprising a source, a drain, and a gate on the substrate; Forming a lower interlayer insulating film filling the transistor; Forming a contact pad in the lower interlayer insulating layer to which the source and the drain are respectively connected; And And forming a conductive line electrically connected to the contact pad that is connected to the drain.

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