KR100610009B1 - Semiconductor device for low power consumption - Google Patents

Abstract

The present invention is to implement a semiconductor device that consumes low power by preventing or minimizing the leakage current of the semiconductor device, one of the semiconductor device having a standby mode and an active mode for low power consumption according to the present invention, At least one P-channel transistor connected to a sub power supply terminal, a source region and a body region connected to the electrostatic power supply terminal, and turned on in a standby mode, and at least one at least one source connected to the sub power supply terminal and turned on in a standby mode A logic block including an N-channel transistor; A first switching unit for supplying a first power supply voltage to the electrostatic source terminal in an active mode and a second power supply voltage to the electrostatic source terminal in a standby mode; And a second switching unit for grounding the sub power supply terminal in an active mode and supplying a back bias voltage to the sub power supply terminal in a standby mode.

Low Power, Threshold Voltage Leakage Current, Switching Units, Logic Blocks

Description

Semiconductor device for low power dissipation             

1 is a circuit diagram of a conventional semiconductor device for low power consumption

2 is a block diagram of another semiconductor device for conventional low power consumption.

3 is a block diagram of a semiconductor device for low power consumption according to an embodiment of the present invention.

4 to 7 are circuit diagrams showing concrete application examples of FIG. 3, respectively.

8 is a block diagram of a semiconductor device for low power consumption according to another embodiment of the present invention.

9 to 10 are circuit diagrams showing concrete application examples of FIG. 8, respectively.

* Description of the symbols for the main parts of the drawings *

110: logic block 122: first switching unit

124: second switching unit VPP: second power supply voltage

VCC: first power supply voltage, power supply voltage VSS: ground voltage

VBB: Back Bias Voltage

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device for low power consumption as a semiconductor device having a standby mode and an active mode.

In general, the semiconductor device increases its power consumption in proportion to the square of the level of the power supply voltage supplied. Therefore, techniques for lowering the operating voltage of the semiconductor device have been proposed to reduce the power consumption of the semiconductor device. However, when the power supply voltage level, which is the operating voltage of the semiconductor device, is lowered, a problem arises in that performance decreases. In general, when the threshold voltage is lowered to prevent this, high-speed operation is possible.

For this reason, a method of lowering a supply voltage and a threshold voltage has been used for high speed operation and low power consumption of a semiconductor device. However, a semiconductor device designed with such a low threshold voltage reduces power consumption during its operation. On the other hand, there is also a problem that the subthreshold leakage current increases when the semiconductor device is not operated. The methods for reducing the subthreshold leakage current include a method of cutting off the source power of the transistor or controlling the back-bias of the transistor. The situation is being proposed.

One example of a method of cutting off the source power supply of the transistor is described in U.S. Pat. No. 6,100,563, which is shown in FIG.

As shown in FIG. 1, the semiconductor device for low power consumption according to the related art includes a plurality of inverters 12a (three on the drawing) connected in series with an electrostatic source terminal VCC *, a sub power supply terminal VSS *, and a series connection. 12b, 12c, PMOS transistor MP9 and NMOS transistor.

Inverters 12a, 12b, and 12c constituted of the PMOS transistors MP6, MP7, and MP8 and the NMOS transistors MN6, MN7, and MN8 are connected to the electrostatic source terminal VCC * and the sub-power terminal VSS *. The input signal Vin is input to the inverter 12a, which is composed of the first stage PMOS transistor MP6 and the NMOS transistor MN6, and the last stage PMOS transistor (not shown). An output signal is output from an inverter (not shown) composed of an NMOS transistor (not shown).

The power supply terminal VCC * is supplied with a power supply voltage VCC in an active mode by the PMOS transistor MP9 and floats in a standby_by mode. The sub power supply terminal VSS * is supplied with the ground voltage VSS in the active mode by the NMOS transistor MN9 and floated in the standby mode. Therefore, in the active mode, the inverters 12a, 12b, and 12c are supplied with the power supply voltage VCC and the ground voltage VSS to perform a normal inverting operation.

In the case of the conventional semiconductor device described above, in the standby mode, the inverters 12a, 12b, and 12c are separated from the power supply voltage VCC and the ground voltage VSS. Therefore, even if a subthreshold voltage leakage current flows through the PMOS transistors MP6, MP7, and MP8 and the NMOS transistors MN6, MN7, and MN8 constituting the inverters 12a, 12b, and 12c, the PMOS transistor MP9. And the sub-threshold voltage leakage current is prevented from flowing to the power supply voltage VCC or the ground voltage VSS because the NMOS transistor MN9 is blocked by the NMOS transistor MN9. Therefore, there is an advantage that the current consumption can be reduced during the standby mode. However, the threshold voltage drop of the PMOS transistor MP9 and the NMOS transistor MN9 decreases the swing width of the operating voltage during the operation of the inverters 12a, 12b, and 12c. A separate full latch means must be provided at the output stage, and there is a problem that a speed delay occurs. In addition, the power supply terminal VCC * and the sub power supply terminal VSS * are floated in the standby mode, thereby preventing the logic level of the input / output terminal from being properly maintained.

2 is a block diagram of a conventional semiconductor device showing one example of a conventional method for controlling the back bias of the transistor described above.

As shown in FIG. 2, the semiconductor device for low power consumption in the related art includes a plurality of inverters 16a (two in the drawing) connected in series with an electrostatic source terminal VCC *, a sub-power terminal VSS *, and a series connection. 16b), a first switching unit 22, a second switching unit 24 and a clock generator 30.

Inverters 16a and 16b constituted by the PMOS transistors P2 and P4 and NMOS transistors N2 and N4 have the electrostatic source terminal VCC in the respective body regions of the PMOS transistors P2 and P4. (*) Is connected, and the sub-power terminal (VSS *) is connected to each of the body regions of the NMOS transistors (N2, N4), the power supply voltage (VCC) and ground voltage (VSS) It is connected to the structure to operate.

In addition, a power supply voltage VCC is supplied to the electrostatic source terminal VCC * in the active mode by the first switching unit 22, and is more constant than the power supply voltage VCC in a standby_by mode. The external power supply voltage VPP having a voltage level higher than the voltage level is supplied. The second power supply unit VSS * is supplied with the ground voltage VSS in the active mode and the back bias voltage VBB in the standby mode.

The first switching unit 22 and the second switching unit 24 are connected to the electrostatic source terminal VCC * and the sub-power terminal according to a signal of the clock generator 30 that distinguishes between an active mode and a standby mode. To supply voltages of different levels to (VSS *), it is configured to include a level shift circuit and a transmission gate circuit.

In the case of the conventional semiconductor device, the external power supply voltage VPP is supplied to the body regions of the PMOS transistors P2 and P4 in the standby mode, and the back bias is applied to the body regions of the NMOS transistors N2 and N4. The power consumption can be reduced by supplying the voltage (BBB) to prevent or minimize the subcritical voltage leakage current. In the active mode, the power supply voltage VCC is supplied to the body regions of the PMOS transistors P2 and P4, and the ground voltage VSS is supplied to the body regions of the NMOS transistors N2 and N4. speed) operation is possible.

However, in the case of the above-described conventional semiconductor device, the power supply voltage VCC and ground at the electrostatic source terminal VCC * and the sub power supply terminal VSS * are irrespective of the frequency of the circuit operated in the active mode. It is configured to operate by supplying a voltage VSS. Therefore, when a circuit which does not require high-speed operation is connected to the electrostatic source terminal VCC * and the sub power supply terminal VSS *, the electrostatic source terminal VCC * and the sub power supply terminal VSS are configured. When the supply voltage VCC and the ground voltage VSS are supplied to *), a subcritical voltage leakage current may be generated.

Accordingly, an object of the present invention is to provide a semiconductor device for low power consumption that can overcome the above-mentioned conventional problems.

Another object of the present invention is to provide a semiconductor device for low power consumption that can prevent or minimize generation of negative threshold voltage leakage current.

Still another object of the present invention is to provide a semiconductor device capable of preventing or minimizing a subthreshold voltage leakage current while performing high speed operation.

It is still another object of the present invention to provide a semiconductor device for low power consumption that can prevent or minimize generation of negative threshold voltage leakage current even in an active mode.

According to an aspect of the present invention for achieving some of the technical problems described above, a semiconductor device having a standby mode and an active mode according to the present invention, the electrostatic source terminal, the sub-power terminal, and the electrostatic source terminal A logic block including at least one P-channel transistor connected to a source region and a body region and turned on in a standby mode, and at least one N-channel transistor connected to the sub-power terminal and turned on in a standby mode; A first switching unit for supplying a first power supply voltage to the electrostatic source terminal in an active mode and a second power supply voltage to the electrostatic source terminal in a standby mode; And a second switching unit for grounding the sub power supply terminal in an active mode and supplying a back bias voltage to the sub power supply terminal in a standby mode.

The first power supply voltage has an internal power supply voltage level, the second power supply voltage may have a level higher than or equal to a predetermined level higher than the first power supply voltage level, and the back bias voltage is a voltage level lower than or equal to a predetermined level lower than the ground level. Can have The source region and the body region of the P-channel transistor may be connected to the electrostatic source terminal, and the source region of the N-channel transistor may be connected to the sub-power terminal. The first switching unit may include a first PMOS transistor operated in an active mode to supply a first power supply voltage to the electrostatic source terminal and receiving a second power supply voltage to a body region, and operated in a standby mode to provide a second power supply. And a second PMOS transistor configured to supply a voltage to the electrostatic source terminal and receive a second power supply voltage to the body region, wherein the second switching unit is operated in an active mode to ground the sub-power terminal to ground the body region. The first NMOS transistor may receive a back bias voltage, and the second NMOS transistor may be operated in a standby mode to supply a back bias voltage to the sub-power terminal and to receive a back bias voltage to a body region.                         

According to another aspect of the present invention for achieving some of the above technical problems, a semiconductor device having a standby mode and an active mode according to the present invention, one end of the electrostatic source terminal, the sub-power supply terminal, and the electrostatic source terminal At least one first transistor including a first transistor to be connected, and a second transistor having one end connected to a power supply voltage terminal, the second transistor having a size smaller than that of the first transistor and connected in parallel to the first transistor to have an input / output in common. A third circuit having one circuit portion, a third transistor having one end connected to the sub-power supply terminal, and one end connected to the ground terminal and having a size smaller than that of the third transistor and connected in parallel to the third transistor to have input / output in common; A logic block including at least one second circuit portion including four transistors; A first switching unit which supplies a power supply voltage to the electrostatic source terminal in an active mode and floats the electrostatic source terminal in a standby mode; And a second switching unit for grounding the sub power terminal in the active mode and floating the sub power terminal in the standby mode.

The first transistor and the second transistor may be PMOS transistors, and the third transistor and the fourth transistor may be NMOS transistors. The first switching unit may include a PMOS transistor operated in an active mode, and the second switching unit may include an NMOS transistor operated in an active mode, and the logic block may include the at least one first. It may include an inverter circuit, a NAND circuit or a NOR circuit comprising a circuit portion and the at least one second circuit portion.                         

According to another aspect of the present invention for achieving some of the above technical problem, a semiconductor device having a standby mode and an active mode according to the present invention is connected to the electrostatic source terminal, the sub-power terminal, the electrostatic source terminal A logic block including at least one P-channel transistor and at least one N-channel transistor connected to the sub-power terminal; A first switching unit for supplying a first power supply voltage to the electrostatic power source terminal in response to a first control signal and for supplying a second power supply voltage to the electrostatic power supply terminal in response to a second control signal; A second switching unit for grounding the sub power supply terminal in response to a first control signal, and supplying a back bias voltage to the sub power supply terminal in response to a second control signal; And a control block for outputting a second control signal in a standby mode and outputting a first control signal or a second control signal by comparing a clock latency or an operating frequency of the logic block with a reference clock in an active mode.

The first power supply voltage has an internal power supply voltage level, the second power supply voltage may have a level higher than or equal to a predetermined level higher than the first power supply voltage level, and the back bias voltage is a voltage level lower than or equal to a predetermined level lower than the ground level. Can have

The body region of the P-channel transistor may be connected to the electrostatic source terminal, and the body region of the N-channel transistor may be connected to the sub-power terminal, and the source region of the P-channel transistor may be connected to the sub-power terminal. A source region of the N-channel transistor may be connected to a terminal. The control block includes: a frequency detector for comparing a clock latency or an operating frequency with a reference clock in an active mode; A NAND gate responsive to an output signal of the frequency detector and an active mode and standby mode enable signal; It may include at least one inverter for buffering the output of the NAND gate.

The first switching unit and the second switching unit may include a level shift circuit or a transfer gate circuit.

According to the device configuration of the present invention described above, it is possible to prevent or minimize the sub-threshold voltage leakage current, it is possible to implement a semiconductor device for low power consumption.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, without any other intention than to provide a thorough understanding of the present invention to those skilled in the art.

3 is a block diagram of a semiconductor device for low power consumption according to an embodiment of the present invention.

As shown in FIG. 3, the semiconductor device according to the embodiment is a semiconductor device having an active mode and a standby mode, and includes a logic block 110, a first switching unit 122, and a second switching unit 124. ).

The logic block 110 may include a logic circuit unit (not shown) connected to the electrostatic source terminal VCC *, the sub power supply terminal VSS *, and the electrostatic source terminal VCC * and the sub power supply terminal VSS *. Include. The logic circuit unit may include a circuit of a plurality of inverters connected in series, a single inverter circuit, a NAND circuit, a NOR circuit, and other circuits.

The first switching unit 122 and the second switching unit 124 may be in an active mode or a standby mode in the electrostatic source terminal VCC * and the sub power supply terminal VSS * constituting the logic block 110. According to the present invention, voltages VPP, VCC, VSS, and VBB having different levels are supplied or the electrostatic source terminal VCC * and the sub-power terminal VSS * are floated.

The first switching unit 122 and the second switching unit 124 may include MOS transistors operated in an active mode or a standby mode.

FIG. 4 is a circuit diagram showing an application example of FIG. 3.

As shown in FIG. 4, the semiconductor device according to an application example of FIG. 3 includes a logic block 110a, a first switching unit 122a, and a second switching unit 124a.

The logic block 110a is configured under the assumption that a logic 'low' level is input to an input signal in an active mode and a logic 'high' level is input to an input signal in a standby mode. And a power supply terminal VCC *, a sub power supply terminal VSS *, and logic circuits 112a, 112b, 112c, and 112d.

The logic circuits 112a, 112b, 112c, and 112d are connected to the electrostatic source terminal VCC * and at least one P-channel transistor MP107 and MP109 turned on in a standby mode and the sub-power terminal VSS *. And at least one N-channel transistor (MN106, MN108) coupled to and turned on in a standby mode.

The logic circuits 112a, 112b, 112c, and 112d may be configured by connecting at least one or more inverter circuits 112a, 112b, 112c, and 112d in series. That is, the first inverter circuit includes a PMOS transistor MP106 receiving the power supply voltage VCC to the source region and the body region, and an NMOS transistor MN106 having a source region connected to the secondary power supply terminal VSS *. 112a), a second inverter circuit 112b including a PMOS transistor NP107 having a source region and a body region connected to the electrostatic source terminal VCC * and an NMOS transistor MN107 having a source region and a body region grounded, A third inverter circuit 112a including a PMOS transistor MP108 that receives a power supply voltage VCC from a source region and a body region, and an NMOS transistor MN108 having a source region connected to the sub-power terminal VSS *, A fourth inverter circuit 112b including a PMOS transistor NP109 having a source region and a body region connected to the electrostatic source terminal VCC * and an NMOS transistor MN109 having a source region and a body region grounded are connected in series. Can be configured The.

The logic circuits 112a, 112b, 112c, and 112d may include a single inverter circuit, may be configured by connecting more inverter circuits in series, and other common knowledge in the art to which the present invention pertains. Naturally, the exciter can be easily configured with other logic circuits. In addition, the logic circuit configuration is based on the assumption that a logic 'high' level is input to an input signal in an active mode and a logic 'low' level is input to an input signal in a standby mode. Those skilled in the art may easily be configured differently from the present embodiment.

The first switching unit 122a is configured to supply a first power supply voltage VCC to the electrostatic source terminal in an active mode and a second power supply voltage VPP to the electrostatic source terminal in a standby mode. The first switching unit 122a is operated in an active mode to supply a first power supply voltage VCC to the electrostatic source terminal VCC * and receive a second power supply voltage VPP to a body region. The second PMOS transistor MP110 which is operated in the transistor MP112 and in the standby mode, supplies a second power supply voltage VPP to the electrostatic source terminal VCC *, and receives a second power supply voltage VPP in the body region. It may be configured to include).

The second switching unit 124a is configured to ground the sub power supply terminal VSS * in an active mode and supply a back bias voltage VBB to the sub power supply terminal VSS * in a standby mode. The second switching unit 124a is operated in an active mode to ground the sub-power terminal VSS * and receive a back bias voltage VBB to a body region, and to the standby mode. The second NMOS transistor MN110 may be operated to supply a back bias voltage VBB to the sub power supply terminal VSS * and to receive a back bias voltage VBB to the body region.

Here, the first power supply voltage VCC may have an internal power supply voltage level, and the second power supply voltage VPP may have a predetermined level or more higher than the first power supply voltage VCC level. In addition, the back bias voltage VBB may have a voltage level (eg, −0.4 V) lower than a predetermined level than the ground level VSS, 0V.

  The operation of the semiconductor device having the configuration as described above is as follows.

First, in the standby mode, a logic 'high' signal is input to the input, and the second power supply voltage VPP is supplied to the electrostatic power source terminal VCC * by the first switching unit 122a, and the negative power supply terminal ( VSS *) is supplied with a back bias voltage VBB. Therefore, the level of the source region of the NMOS transistors MN106 and MN108 connected to the negative power supply terminal VSS * becomes the back bias voltage VBB level, and the PMOS transistors connected to the electrostatic source terminal VCC * The level of the source region of MP107 and MP109 becomes the second power supply voltage VPP level. The NMOS transistors MN106 and MN108 and the PMOS transistors MP107 and MP109 are turned on due to the input of the logic 'high' signal. Accordingly, there is a possibility that a subthreshold voltage leakage current is generated in the PMOS transistors MP106 and MP108 and the NMOS transistors MN107 and MN109 that are not turned on. However, since the NMOS transistors MN106 and MN108 are turned on, the voltage level between the gate and the source region of the NMOS transistors MN107 and MN109 becomes a negative voltage level, thereby blocking the subthreshold voltage leakage current. In addition, since the PMOS transistors MP107 and MP109 are turned on, the voltage level between the gate and the source region of the PMOS transistors MP106 and MP108 becomes a positive voltage level so that the negative threshold voltage leakage current is blocked. Accordingly, power consumption can be prevented or minimized in the standby mode, and floating of the electrostatic source terminal VCC * and the sub-power terminal VSS * is prevented.

Next, in the active mode, a logic 'low' signal is input to the input, and a first power supply voltage VCC is supplied to the electrostatic power source terminal VCC * by the first switching unit 122a, and a negative power supply terminal. (VSS *) is grounded. Thus, the level of the source region of the NMOS transistors MN106 and MN108 connected to the sub-power terminal VSS * becomes the ground level VSS, and the PMOS transistors MP107 connected to the electrostatic source terminal VCC *. The level of the source region of MP109 becomes the first power supply voltage VCC level. Due to the input of the logic 'low' signal, the PMOS transistor MP106, the NMOS transistor MN107, the PMOS transistor MP108, and the NMOS transistor MN109 are sequentially turned on to perform high-speed operation as in the prior art. .

FIG. 5 is a circuit diagram illustrating another application example of FIG. 3.

As illustrated in FIG. 5, the semiconductor device according to another application example of FIG. 3 includes a logic block 110b, a first switching unit 122b, and a second switching unit 124b.

The logic block 110b may include a static electricity source terminal VCC *, a secondary power supply terminal VSS *, at least one first circuit portion 111 and 112, and at least one (one figure in the drawing). The second circuit unit 113 is included.

The first circuit unit 111 has a size of a first transistor MP101 having one end connected to the electrostatic source terminal VCC * and one end connected to a power supply voltage VCC terminal and smaller than the first transistor MP101. It includes a second transistor (MP102) having a (size) and connected in parallel to the first transistor (MP101) in common input / output.

The first transistor MP101 and the second transistor MP102 may be configured as PMOS transistors, and the second transistor MP102 may have a minimum size or width that can be stably operated. It can be configured as.

In addition, a source region of the first transistor MP101 is connected to the electrostatic source terminal VCC *, and a second transistor MP102 is supplied with a power supply voltage VCC to a source region, and the first transistor MP101 is provided. MP101) and the gate and the drain can be configured in common.

The first circuit part 112 may include a first transistor MP103 having one end connected to the electrostatic source terminal VCC *, and one end connected to a power supply voltage VCC terminal, and more than the first transistor MP103. It includes a second transistor (MP104) having a small size and connected in parallel to the first transistor (MP103) in common input / output.

The first transistor MP103 and the second transistor MP104 may be configured as PMOS transistors, and the second transistor MP104 may have a minimum size or width capable of operating stably. It can be configured as.

In addition, a source region of the first transistor MP103 is connected to the electrostatic source terminal VCC *, and a second transistor MP104 receives a power supply voltage VCC to a source region of the first transistor MP103, and the first transistor MP103. MP103) and the gate and the drain can be configured in common.

The second circuit 113 has a third transistor MN102 having one end connected to a sub power terminal VSS *, and one end thereof connected to a ground terminal VSS, and has a size smaller than that of the third transistor MN102. A fourth transistor MN103 connected in parallel to the third transistor MN102 and having input / output in common is included.

The third transistor MN102 and the fourth transistor MN103 may be configured as NMOS transistors, and the fourth transistor MN103 has a minimum size or width capable of operating stably. It can be configured as.

In addition, a source region of the third transistor MN102 is connected to the sub power supply terminal VSS *, and a source region of the fourth transistor MN103 is grounded, and a gate and a drain of the third transistor MN102 are connected to each other. It may be configured to be common.

The logic block 110b may further include a fifth transistor MN101 that is an NMOS transistor.

The logic block 110c may include the first transistor MP101 constituting the first circuit unit 111, the first transistor MP103 constituting another first circuit unit 112, and the second circuit unit 113. Including the third transistor (MN102) and the fifth transistor (MN101) constituting a), the input signal (A, B) is input to the gate of each of the first transistor (MP101, MP103) and the fifth transistor ( A NAND operation is performed by receiving the input signal A through the gate of the MN101 to output an output signal using the common drains of the first transistors MP101 and MP103 and the fifth transistor MN101 as output nodes. ) May be configured as a logic NAND circuit.

The first switching unit 122b supplies a power supply voltage VCC to the electrostatic source terminal VCC * in an active mode and floats the electrostatic source terminal VCC * in a standby mode. The first switching unit 122b may include a PMOS transistor MP105.

The second switching unit 124b grounds the sub power terminal VSS * in the active mode and floats the sub power terminal VSS * in the standby mode. The second switching unit 124b may include an NMOS transistor MN104.

In the semiconductor device according to another application example of FIG. 3 described above, when the input signals A and B each have a logic 'high' or logic 'low' level in the standby mode, The electrostatic source terminal VCC * and the sub-power terminal VSS * are floated by the first switching unit 122b and the second switching unit 124b, and thus the first transistors MP101 and MP103. ) And the subthreshold leakage current that may exist in the third transistor MN102 are cut off. In addition, the input and output signals of the input / output terminals are formed by the second transistors MP102 and MP104 and the fourth transistor MN103 connected in parallel with each of the first transistors MP101 and MP103 and the third transistor MN102. The logic state of A, B, output) can maintain the logic 'high' or logic 'low' level. The leakage currents of the second transistors MP102 and MP104 and the fourth transistor MN103 are negligible because the sizes of the second transistors MP102 and MP104 and the fourth transistor MN103 are very small. Only a leakage current of exists.

In the active mode, the power supply voltage VCC is supplied to the electrostatic source terminal VCC * by the first switching unit 122b, and the sub power supply terminal VSS * is supplied by the second switching unit 124b. Since it has a ground level (VSS), it operates with a normal NAND circuit.

FIG. 6 is a circuit diagram illustrating still another application example of FIG. 3.

As illustrated in FIG. 6, a semiconductor device according to another application example of FIG. 3 includes a logic block 110c, a first switching unit 122c, and a second switching unit 124c.

The logic block 110c may include at least one of the first power supply unit VCC *, the second power supply terminal VSS *, at least one first circuit unit 114 (one on the drawing), and at least one (two on the drawing). Second circuit portions 115 and 116 are included.

The first circuit unit 114 includes a first transistor MP106 having one end connected to the electrostatic source terminal VCC * and one end connected to a power supply voltage VCC terminal and smaller than the first transistor MP106. It includes a second transistor (MP107) having a size (size) and connected in parallel to the first transistor (MP106) in common input / output.

The first transistor MP106 and the second transistor MP107 may be configured as PMOS transistors, and the second transistor MP107 may have a minimum size or width capable of operating stably. It can be configured as.

In addition, a source region of the first transistor MP106 is connected to the electrostatic source terminal VCC *, and a second transistor MP107 is supplied with a power supply voltage VCC to the source region, and the first transistor MP106 is provided. MP106) and gate and drain in common.

The second circuit unit 115 has a third transistor MN106 whose one end is connected to the sub power terminal VSS *, and one end thereof is connected to the ground terminal VSS, and has a size smaller than that of the third transistor MN106. The fourth transistor MN107 is connected to the third transistor MN106 in parallel and has a common input / output.

The third transistor MN106 and the fourth transistor MN107 may be configured as NMOS transistors, and the fourth transistor MN107 may have a minimum size or width capable of operating stably. It can be configured as.

In addition, a source region of the third transistor MN106 is connected to the negative power supply terminal VSS *, and a source region of the fourth transistor MN107 is grounded, and a gate and a drain of the third transistor MN106 are grounded. It may be configured to be common.

The second circuit unit 116 has a third transistor MN109 having one end connected to a sub power supply terminal VSS *, and one end thereof connected to a ground terminal VSS and smaller than the third transistor MN109. And a fourth transistor MN108 having a common input / output connection to the third transistor MN109 in parallel.

The third transistor MN109 and the fourth transistor MN108 may be configured as NMOS transistors, and the fourth transistor MN108 has a minimum size or width capable of operating stably. It can be configured as.

In addition, a source region of the third transistor MN109 is connected to the sub power supply terminal VSS *, and a source region of the fourth transistor MN108 is grounded, and the gate and the drain of the third transistor MN109 are grounded. It may be configured to be common.

The logic block 110c may further include a fifth transistor MP108 that is a PMOS transistor.

The logic block 110c includes the first transistor MP106 constituting the first circuit part 114, the third transistor MN106 constituting the second circuit part 115, and the second second circuit part 116. Including the third transistor (MN109) and the fifth transistor (MN101) constituting a), and receives the input signal (A) to the gate of each of the first transistor (MP106) and the third transistor (MN106) The NOR operation is performed by receiving an input signal B through the gates of the fifth transistor MP108 and the third transistor MN109, and performing the NOR operation on the third transistors MN106 and MN109 and the fifth transistor MP108. And a logic NOR circuit for outputting an output signal.

The first switching unit 122c supplies a power supply voltage VCC to the electrostatic source terminal VCC * in an active mode, and floats the electrostatic source terminal VCC * in a standby mode. The first switching unit 122c may include a PMOS transistor MP109.

The second switching unit 124c grounds the sub power terminal VSS * in the active mode and floats the sub power terminal VSS * in the standby mode. The second switching unit 124c may include an NMOS transistor MN110.

The semiconductor device according to still another application example of FIG. 3 described above, when each of the input signals A and B has a logic 'high' or logic 'low' level in the standby mode. In addition, the electrostatic source terminal VCC * and the sub power supply terminal VSS * are floated by the first switching unit 122c and the second switching unit 124c, and thus the first transistor MP106 and The subthreshold leakage current that may exist in the third transistors MN106 and MN109 is cut off. In addition, the input and output signals of the input / output terminals are formed by the second transistors MP107 and the fourth transistors MN107 and MN108 connected in parallel with the first transistor MP106 and the third transistors MN106 and MN109, respectively. The logic state of A, B, output) can maintain the logic 'high' or logic 'low' level. In addition, the leakage currents of the second and fourth transistors MP107 and MN107 and MN108 may be negligible because the sizes of the second and fourth transistors MP107 and MN107 and MN108 are very small. Only a leakage current of exists.

In the active mode, the power supply voltage VCC is supplied to the electrostatic source terminal VCC * by the first switching unit 122c, and the sub power supply terminal VSS * is supplied by the second switching unit 124c. Since it has a ground level (VSS), it operates in a normal NOR circuit.

FIG. 7 is a circuit diagram illustrating still another application example of FIG. 3.

As illustrated in FIG. 7, a semiconductor device according to another application example of FIG. 3 includes a logic block 110d, a first switching unit 122d, and a second switching unit 124d.

The logic block 110d includes at least one first circuit portion 118a and 118b and at least one (two on the drawing) of the electrostatic source terminal VCC *, the auxiliary power supply terminal VSS *, and at least one (two on the drawing). ) Includes a second circuit portion 117a. The logic block 110d is connected in series with a structure of another first circuit part 118b and a second circuit part 117b having the same connection structure as that of the first circuit part 118a and the second circuit part 117a. The structure is repeated. Therefore, for the sake of convenience, only the configuration and operation of the first circuit section 118a and the second circuit section 117a will be described, and the first circuit section 118b and the first transistor section MP118 and the second transistor section MP115 will be described. A description of the configuration and operation of the second circuit unit 117b including the third transistor MN114 and the fourth transistor MN115 is omitted.

The first circuit unit 118a has a first transistor MP112 having one end connected to the electrostatic source terminal VCC * and one end connected to a power supply voltage VCC terminal and smaller than the first transistor MP112. It includes a second transistor (MP113) having a (size) and connected in parallel to the first transistor (MP112) in common input / output.

The first transistor MP112 and the second transistor MP113 may be configured as PMOS transistors, and the second transistor MP113 may have a minimum size or width that may be stably operated. It can be configured as.

In addition, a source region of the first transistor MP112 is connected to the electrostatic source terminal VCC *, and a second transistor MP113 receives a power supply voltage VCC to a source region of the first transistor MP112, and the first transistor MP112. MP112) and the gate and the drain can be configured in common.

The second circuit unit 117a has a third transistor MN112 having one end connected to the sub power terminal VSS * and one end connected to the ground terminal VSS and having a size smaller than that of the third transistor MN112. The fourth transistor MN113 is connected to the third transistor MN112 in parallel and has a common input / output.

The third transistor MN112 and the fourth transistor MN113 may be configured as NMOS transistors, and the fourth transistor MN113 may have a minimum size or width capable of operating stably. It can be configured as.

In addition, a source region of the third transistor MN112 is connected to the sub power supply terminal VSS *, and a source region of the fourth transistor MN113 is grounded, and the gate and the drain of the third transistor MN112 are grounded. It may be configured to be common.

The logic block 110d includes the first transistor MP112 constituting the first circuit portion 118a and the third transistor MN112 constituting the second circuit portion 117a. An input signal is input to the common gate of the MP112 and the third transistor MN112 and inverted, thereby outputting the common drain of the first transistor MP112 and the third transistor MN112 as an output node. ) May be configured as a single logic inverter circuit 119a. In addition, the logic block 110d may further include at least one or more inverter circuits 119c connected in series to the inverter circuit 119a.

The first switching unit 122d supplies a power supply voltage VCC to the electrostatic source terminal VCC * in an active mode, and floats the electrostatic source terminal VCC * in a standby mode. The first switching unit 122d may include a PMOS transistor MP116.

The second switching unit 124d grounds the sub power terminal VSS * in the active mode and floats the sub power terminal VSS * in the standby mode. The second switching unit 124d may include an NMOS transistor MN116.

The semiconductor device according to still another application example of FIG. 3 described above, when the input signal has a logic 'high' or logic 'low' level in the standby mode, the semiconductor device. The electrostatic source terminal VCC * and the sub power supply terminal VSS * are floated by the first switching unit 122d and the second switching unit 124d, and thus the first transistor MP112 and the third transistor. The subthreshold leakage current that may be present at (MN112) is cut off. In addition, the logic of the input and output signals of the input and output terminals by the second transistor MP113 and the fourth transistor MN113 connected in parallel with each of the first transistor MP112 and the third transistor MN112. The state may maintain a logic 'high' or logic 'low' level. Since the leakage currents of the second transistor MP113 and the fourth transistor MN113 are very small in size, the leakage currents of the second transistor MP113 and the fourth transistor MN113 are so small that only a negligible leakage current exists. do.

In the active mode, the power supply voltage VCC is supplied to the electrostatic source terminal VCC * by the first switching unit 122d, and the sub power supply terminal VSS * is supplied by the second switching unit 124d. Since it has a ground level (VSS), it operates in a normal inverter circuit.

8 is a block diagram of a semiconductor device for low power consumption according to another embodiment of the present invention.

As shown in FIG. 8, a semiconductor device according to another embodiment of the present invention is a semiconductor device having an active mode and a standby mode, and includes a logic block 210, a first switching unit 222, and a second switching unit 224. ) And the control block 230.

The logic block 210 may include a logic circuit unit (not shown) connected to the electrostatic source terminal VCC *, the sub power supply terminal VSS *, and the electrostatic source terminal VCC * and the sub power supply terminal VSS *. Include. The logic circuit unit may include a circuit of a plurality of inverters connected in series, a single inverter circuit, a NAND circuit, a NOR circuit, and other circuits.

The first switching unit 222 and the second switching unit 224 may include the electrostatic source terminal VCC * constituting the logic block 210 in response to control signals output from the control block 230, and Voltages VPP, VCC, VSS, and VBB of different levels are respectively supplied to the sub power supply terminals VSS *.

The first switching unit 222 and the second switching unit 224 may include a level shift circuit or a transmission gate circuit operated in an active mode or a standby mode.

The control block 230 may include the first switching unit 222 based on information such as clock latency, clock frequency or clock cycle time of the logic block 230, an active mode enable signal, or the like. ) And the second switching unit 224.

FIG. 9 is a circuit diagram illustrating an application example of FIG. 8.

As shown in FIG. 9, the semiconductor device according to an application example of FIG. 8 includes a logic block 210a, a first switching unit 222a, a second switching unit 224a, and a control block 230a. do.

The logic block 210a may include at least one P-channel transistor P202 connected to the electrostatic source terminal VCC *, the sub-power terminal VSS *, and the electrostatic source terminal VCC * (two in the drawing). P204 and logic circuits 207a and 207b including at least one (two in the figure) N-channel transistors N202 and N204 connected to the sub-power terminal VSS *.

The logic circuit units 207a and 207b may be configured by at least one inverter circuit 207a and 207b connected in series. That is, the PMOS transistor P202 and the source region having the power supply voltage VCC supplied to the source region and the body region connected to the electrostatic source terminal VCC * are grounded, and the body region is connected to the sub power supply terminal VSS *. PMOS transistor P204 and a source in which a first inverter circuit 207a composed of an NMOS transistor N202 and a power supply voltage VCC are supplied to a source region and a body region is connected to the electrostatic source terminal VCC *. A second inverter circuit 207b or the like configured of an NMOS transistor N204 having a region grounded and a body region connected to the sub power terminal VSS * may be connected in series.

The logic circuits 207a and 207b may be configured to include a single inverter circuit, and may be configured by connecting a plurality of inverter circuits in series, respectively. Naturally, the exciter can be easily configured with other logic circuits.

The first switching unit 222a supplies a first power supply voltage VCC to the electrostatic source terminal VCC * in response to a first control signal, and supplies the first source voltage VCC * in response to a second control signal. ) To supply the second power supply voltage VPP.

The second switching unit 224a grounds the sub power supply terminal VSS * in response to a first control signal, and a back bias voltage VBB at the sub power supply terminal VSS * in response to a second control signal. It is to supply.

The first switching unit 222a and the second switching unit 224a may include a level shift circuit or a transfer gate circuit.

Here, the first power supply voltage VCC may have an internal power supply voltage level, and the second power supply voltage VPP may have a predetermined level or more higher than the first power supply voltage VCC level. In addition, the back bias voltage VBB may have a voltage level (eg, −0.4 V) lower than a predetermined level than the ground level VSS, 0V.

The control block 230a outputs a second control signal in a standby mode, and outputs a first control signal or a second control signal by comparing a clock latency or an operating frequency of the logic block 210a with a reference clock in an active mode. The first switching unit 222a and the second switching unit 224a are controlled.

The control block 230a is a frequency detector 232a for comparing the clock latency or operating frequency of the logic block 210a with a reference clock in an active mode, and an output of the frequency detector 232a. And a NAND gate 234a in response to the signal, an active mode and a standby mode enable signal, and at least one inverter circuit 236a and 238a buffering an output of the NAND gate 234a.

The operation in the semiconductor device as one application example of FIG. 8 as described above is as follows.

In the standby mode, the standby mode enable signal stand_by becomes an input of the NAND gate 234a constituting the control block 230a at a logic 'low' level, so that the output signal of the frequency detector 232a Regardless, the control block 230a outputs a second control signal having a logic 'high' level. Accordingly, the first switching unit 222a and the second switching unit 224a supply a second power supply voltage VPP to the electrostatic source terminal VCC * in response to the second control signal, and supply the secondary power supply. The terminal VSS * supplies a back bias voltage VBB to prevent or minimize leakage current.

Next, in the active mode, the clock latency or operating frequency of the logic block 210a is compared with the reference clock, and if the clock latency or operating frequency is higher than the reference clock, the logic 'High' in the frequency detector 232a. When the clock latency or the operating frequency is lower than the reference clock, the output signal of the logic 'Low' level is output from the frequency detector 232a.

As the output signal of the frequency detector 232a of the logic 'low' level becomes the input of the NAND gate 234a, the control block 230a is independent of the active mode enable signal Active. Outputs a second control signal having a logic 'high' level. Accordingly, the first switching unit 222a and the second switching unit 224a supply a second power supply voltage VPP to the electrostatic source terminal VCC * in response to the second control signal, and supply the secondary power supply. The terminal VSS * supplies a back bias voltage VBB to prevent or minimize leakage current.

The output signal of the frequency detector 232a having a logic 'high' level is NAND-operated at the active mode enable signal Active and the NAND gate 234a so that an output signal having a logic 'low' level is output. Is output. The logic 'low' level output signal is buffered so that the first control signal having a logic 'low' level is output from the control block 230a. Accordingly, the first switching unit 222a and the second switching unit 224a supply a first power supply voltage VCC to the electrostatic source terminal VCC * in response to the first control signal, and supply the sub-power source. Ground terminal VSS * to a state suitable for high speed operation.

Therefore, the clock latency or the operating frequency of the circuit operated not only in the standby mode but also in the active mode is determined. When the circuit operated is composed of a circuit which does not require high-speed operation, the power supply terminal VCC * and the fault By controlling the level of the original terminal (VSS *) as in the standby mode, leakage current can be prevented or minimized.

FIG. 10 is a circuit diagram illustrating another application example of FIG. 8.

As shown in FIG. 10, the semiconductor device according to another application example of FIG. 8 includes a logic block 210b, a first switching unit 222b, a second switching unit 224b, and a control block 230b. .

The logic block 210b includes at least one P-channel transistor P206 connected to the electrostatic source terminal VCC *, the sub-power terminal VSS *, and the electrostatic source terminal VCC * (two in the drawing). P208 and logic circuits 209a and 209b having at least one (two in the figure) N-channel transistors N206 and N208 connected to the sub power supply terminal VSS *.

The logic circuit units 209a and 209b may be configured such that at least one or more inverter circuits 209a and 209b are connected in series to each other. That is, a first inverter circuit 209a including a PMOS transistor P206 having a source region connected to the electrostatic source terminal VCC * and an NMOS transistor N206 having a source region connected to the sub power supply terminal VSS *. ) And a second inverter circuit including a PMOS transistor P208 having a source region connected to the electrostatic source terminal VCC * and an NMOS transistor N208 having a source region connected to the sub-power terminal VSS *. 209b) and the like may be configured in series.

The logic circuits 209a and 209b may include a single inverter circuit, and may be configured by connecting a plurality of inverter circuits in series, and other common knowledge in the art to which the present invention pertains. Naturally, the exciter can be easily configured with other logic circuits.

Descriptions of the configuration or operation of the first switching unit 222b, the second switching unit 224b, and the control block 230b are the same as those described with reference to FIG. .

The description of the above embodiments is merely given by way of example with reference to the drawings for a more thorough understanding of the present invention, and should not be construed as limiting the present invention. In addition, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the basic principles of the present invention. For example, it is clear that in other cases, the circuit configuration of the logic block, the first switching unit, the second switching unit, the control block, or the like may be changed or the internal components of the circuit may be replaced with other equivalent elements.

As described above, according to the present invention, it is possible to prevent or minimize generation of leakage current in the semiconductor device. That is, while performing high-speed operation, it is possible to simultaneously prevent or minimize the subcritical voltage leakage current, and in the active mode, there is an effect of preventing or minimizing the generation of the subcritical voltage leakage current.

Claims (20)

In a semiconductor device having a standby mode and an active mode: A power source terminal, a sub-power terminal, at least one P-channel transistor connected to a source region and a body region and turned on in a standby mode, and a source region connected to the sub-power terminal and turned on in a standby mode A logic block comprising at least one N-channel transistor; A first switching unit for supplying a first power supply voltage to the electrostatic source terminal in an active mode and a second power supply voltage to the electrostatic source terminal in a standby mode; And a second switching unit for grounding the sub power supply terminal in an active mode and supplying a back bias voltage to the sub power supply terminal in a standby mode. The method of claim 1, And the first power supply voltage has an internal power supply voltage level, and the second power supply voltage has a predetermined level higher than the first power supply voltage level. The method of claim 2, And the back bias voltage has a voltage level at least a predetermined level lower than the ground level. (delete) The method of claim 3, The first switching unit is operated in an active mode to supply a first power supply voltage to the electrostatic source terminal and to receive a second power supply voltage to a body region, and to operate in a standby mode to supply a second power supply voltage. And a second PMOS transistor supplied to the electrostatic source terminal and supplied with a second power supply voltage to the body region. The method of claim 5, The second switching unit is operated in an active mode to ground the sub power supply terminal and receives a back bias voltage to a body region, and is operated in a standby mode to supply a back bias voltage to the sub power supply terminal. And a second NMOS transistor supplied with a back bias voltage to the body region. The method of claim 6, And said logic block comprises at least one inverter circuit comprising a PMOS transistor and an NMOS transistor having a common drain and connected in series. In a semiconductor device having a standby mode and an active mode: A power supply terminal, Negative power supply terminal, A first transistor having one end connected to the electrostatic source terminal and a second transistor having one end connected to a power supply voltage terminal and having a smaller size than the first transistor and connected in parallel to the first transistor in common; At least one first circuit portion comprising: A third transistor having one end connected to a sub-power terminal, and a fourth transistor having one end connected to the ground terminal and having a size smaller than that of the third transistor and connected in parallel to the third transistor to have input / output in common; A logic block including at least one second circuit unit; A first switching unit which supplies a power supply voltage to the electrostatic source terminal in an active mode and floats the electrostatic source terminal in a standby mode; And a second switching unit for grounding the sub power supply terminal in an active mode and floating the sub power supply terminal in a standby mode. The method of claim 8, And the first transistor and the second transistor are PMOS transistors, and the third transistor and the fourth transistor are NMOS transistors. The method of claim 9, And the first switching unit includes a PMOS transistor operated in an active mode, and the second switching unit includes an NMOS transistor operated in an active mode. The method of claim 10, And the logic block comprises an inverter circuit comprising the at least one first circuit portion and the at least one second circuit portion. The method of claim 10, And the logic block comprises a NAND circuit including the at least one first circuit portion and the at least one second circuit portion. The method of claim 10, And the logic block comprises a NOR circuit comprising the at least one first circuit portion and the at least one second circuit portion. In a semiconductor device having a standby mode and an active mode: A logic block comprising a power supply terminal, a sub power supply terminal, at least one P-channel transistor connected to the power supply terminal, and at least one N-channel transistor connected to the sub power supply terminal; A first switching unit for supplying a first power supply voltage to the electrostatic power source terminal in response to a first control signal and for supplying a second power supply voltage to the electrostatic power supply terminal in response to a second control signal; A second switching unit for grounding the sub power supply terminal in response to a first control signal, and supplying a back bias voltage to the sub power supply terminal in response to a second control signal; And a control block outputting a second control signal in a standby mode and outputting a first control signal or a second control signal by comparing a clock latency or an operating frequency of the logic block with a reference clock in an active mode. Device. The method of claim 14, And the first power supply voltage has an internal power supply voltage level, and the second power supply voltage has a predetermined level higher than the first power supply voltage level. The method of claim 15, And the back bias voltage has a voltage level at least a predetermined level lower than the ground level. The method of claim 16, And the body region of the P-channel transistor is connected to the electrostatic source terminal, and the body region of the N-channel transistor is connected to the sub-power terminal. The method of claim 16, And the source region of the P-channel transistor is connected to the electrostatic source terminal, and the source region of the N-channel transistor is connected to the sub-power terminal. The method of claim 17 or 18, wherein the control block, A frequency detector for comparing a clock latency or an operating frequency with a reference clock in an active mode;  A NAND gate responsive to an output signal of the frequency detector and an active mode and standby mode enable signal; And at least one inverter for buffering the output of the NAND gate. The method of claim 19, And the first switching unit and the second switching unit comprise a level shift circuit or a transfer gate circuit.

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