KR100504689B1 - Nand type flash memory device and method for manufacturing the same - Google Patents

Abstract

The present invention discloses a NAND type flash memory device having a high insulation effect between a bit line BL and a common source line CSL, and a method of manufacturing the same. The present invention disclosed is a semiconductor substrate; A string including a string select line, a word line, and a ground select line arranged on the substrate and extending in the same direction and arranged in parallel; A bit line extending in a direction substantially perpendicular to a direction in which each line constituting the string extends; A contact plug in electrical connection with the drain of the string select line and the bit line; And a common source line including a lower layer electrically connected to the source of the ground selection line and an upper layer electrically insulated from the bit line. According to the present invention, there is an effect that the insulation effect between the bit line and the common source line is increased. In addition, by lowering the overall height of the insulating film, there is an effect that the subsequent process becomes easy.

Description

NAND type flash memory device and manufacturing method thereof {NAND TYPE FLASH MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

The present invention relates to a NAND flash memory device and a method of manufacturing the same, and more particularly to a NAND flash memory device having a high insulation effect between the bit line (BL) and the common source line (CSL) and a method of manufacturing the same.

Generally, semiconductor devices are classified into memory devices and non-memory devices, and memory devices are classified into volatile memory devices and nonvolatile memory devices. A volatile memory device does not maintain a write state when a power supply is interrupted. The volatile memory device may be a dynamic random access memory device, that is, a DRAM device. In contrast, the nonvolatile memory device is a flash memory device that can be electrically programmed and erased even when the power supply is interrupted. have. Flash memory devices are generally classified into a NOR type, which is advantageous for speeding up operation speed, and a NAND type, which is advantageous for high integration because several cells can be controlled by one bundle body.

1 is a plan view showing a part of a NAND type flash memory device according to the prior art.

Referring to FIG. 1, a NAND type flash memory device includes several word lines 20 between a string selection line 30 and a ground selection line 40 on a silicon substrate 10. Lines are connected to form a string. These strings are connected to several bit lines 70 to form one block. Here, the drain of the string select line 30 is electrically connected to the bit line 70 by the contact plug 60, and the source of the ground select line 40 is electrically connected to the common source line 50. All strings in the block share a common source line 50.

FIG. 2 is a cross-sectional view taken along line II of FIG. 1.

Referring to FIG. 2, in a NAND type flash memory device, several word lines 20 (WL) are arranged between a string select line (SSL) 30 and a ground select line 40 (GSL) formed on a silicon substrate 10. To form a string. The source 14 of the ground select line 40 (GSL) is electrically connected to the common source line 50 (CSL) to provide a reference potential for programming, erasing, and reading the device. . The drain 12 of the string selection line 30 (SSL) is electrically connected to the bit line 70 (BL) through a contact plug 60 passing through the first insulating layer 45 and the second insulating layer 55. Optionally supply a potential to (String). Although not shown in FIG. 2, the bit lines 70 in which several are arranged in a direction perpendicular to the longitudinal direction of the common source line 50 are spaced apart from each other by a third insulating film (not shown).

3 is a cross-sectional view taken along the line II-II of FIG. 1.

Referring to FIG. 3, the common source line 50 and the bit line 70 formed on the silicon substrate 10 are insulated by the second insulating layer 55. The bit lines 70 are arranged in parallel in the longitudinal direction of the common source line 50, and as described above, each of the bit lines 70 is spaced apart from each other by the third insulating layer 65.

As described above, in the NAND type flash memory device, the bit line 70 and the contact plug 60 must be directly connected. However, the bit line 70 and the common source line 50 must be electrically insulated completely. However, the second insulating layer 55 that insulates the bit line 70 and the common source line 50 is composed of an oxide film. The effect is low. In addition, the contact plug 60 and the bit line 70 may be formed by a process of selectively etching the second insulating layer 55. Therefore, in order to prevent the bit line 70 and the common source line 50 from being connected to each other, the second insulating layer 55 should be formed thick. In this case, since the thick second insulating layer 55 needs to be etched when the contact plug 60 is formed, there is a problem in that a small size of the contact plug 60 is formed according to the recent high integration trend.

Accordingly, an object of the present invention is to provide a NAND flash memory device having a high insulation effect between a bit line and a common source line, and a method of manufacturing the same.

Another object of the present invention is to provide a NAND type flash memory device having a low insulating film thickness between a bit line and a common source line, and a method of manufacturing the same.

According to an aspect of the present invention, there is provided a NAND flash memory device comprising: a semiconductor substrate; A string including a string select line, a word line, and a ground select line arranged on the substrate and extending in the same direction and arranged in parallel; A bit line extending in a direction substantially perpendicular to a direction in which each line constituting the string extends; A contact plug in electrical connection with the drain of the string select line and the bit line; And a common source line including a lower layer electrically connected to the source of the ground selection line and an upper layer electrically insulated from the bit line.

One layer of an interlayer insulating film is formed between the substrate and the bit line, and the contact plug penetrates the interlayer insulating film to electrically conduct the drain and the bit line of the string selection line, and the common source line is the interlayer insulating film. The conductive material is electrically connected to the source of the ground selection line by the lower layer and is electrically insulated from the bit line by the upper layer.

Alternatively, two interlayer insulating films including a first interlayer insulating film and a second interlayer insulating film are formed between the substrate and the bit line, and the contact plug passes through the first interlayer insulating film and the second interlayer insulating film to select the string. A drain line of the line and a bit line are electrically connected to each other, and the common source line passes through the first interlayer insulating layer, and is electrically connected to the source of the ground selection line by the lower layer. The film is electrically insulated by the second interlayer insulating film.

The lower layer constituting the common source line is a polysilicon layer, and the upper layer is a nitride layer.

According to an aspect of the present invention, there is provided a method of manufacturing a NAND flash memory device, the method including: providing a semiconductor substrate; Forming a string including a string select line, a word line, and a ground select line on the substrate; Forming an interlayer insulating film on an entire surface of the substrate on which the string is formed; Selectively removing the interlayer insulating layer to expose a drain of the ground select line to form a first contact hole; Filling the first contact hole with the first conductor and the insulator sequentially to form a lower layer formed of the first conductor and an upper layer formed of the insulator, thereby forming a common source line including the lower layer and the upper layer; ; Selectively removing the interlayer insulating layer to expose a drain of the string select line to form a second contact hole; Filling the second contact hole with a second conductor to form a contact plug; And forming a bit line on the interlayer insulating layer, the bit line being electrically insulated from the common source line by the upper layer and electrically connected to the contact plug.

The forming of the common source line may include depositing a first conductor on the interlayer insulating layer to fill the first contact hole; The first conductor is etched to expose the interlayer insulating layer, and a portion of the first conductor deposited in the first contact hole is etched to constitute the first conductor and has a height lower than that of the first contact hole. Forming a lower layer in electrical communication with the drain of the ground select line; Depositing an insulator on the interlayer insulating film such that the remaining portion of the first contact hole in which the lower layer is formed is not buried; And planarizing the insulator by chemical mechanical polishing so that the interlayer insulating layer is exposed, thereby forming an upper layer composed of the insulator and electrically insulated from the bit line.

The lower layer constituting the common source line is formed of a polysilicon layer, and the upper layer is formed of a nitride layer.

In addition, a method of manufacturing a NAND flash memory device according to another embodiment of the present invention for achieving the above object comprises the steps of providing a semiconductor substrate; Forming a string including a string select line, a word line, and a ground select line on the substrate; Forming a first interlayer insulating film on an entire surface of the substrate on which the string is formed; Selectively removing the first interlayer insulating layer to expose a drain of the ground select line to form a first contact hole; Filling the first contact hole with the first conductor and the insulator sequentially to form a lower layer formed of the first conductor and an upper layer formed of the insulator, thereby forming a common source line including the lower layer and the upper layer; ; Forming a second interlayer insulating film on the first interlayer insulating film; Selectively removing the second interlayer dielectric layer and the first interlayer dielectric layer so that the drain of the string select line is exposed to form a second contact hole; Filling the second contact hole with a second conductor to form a contact plug; And forming a bit line on the second interlayer insulating layer, the bit line being electrically insulated from the common source line by the upper layer and the first interlayer insulating layer and electrically connected to the contact plug. .

The forming of the common source line may include depositing a first conductor on the first interlayer insulating layer to fill the first contact hole; The first conductor is etched to expose the first interlayer insulating layer, and a portion of the first conductor deposited in the first contact hole is also etched to form a height lower than the height of the first contact hole. Forming a bottom layer having a bottom layer and electrically connected to a drain of the ground select line; Depositing an insulator on the first interlayer insulating film such that the remaining portion of the first contact hole in which the lower layer is formed is not buried; And planarizing the insulator by chemical mechanical polishing so that the first interlayer insulating film is exposed, thereby forming an upper film composed of the insulator and electrically insulated from the bit line.

The lower layer constituting the common source line is formed of a polysilicon layer, and the upper layer is formed of a nitride layer.

According to the present invention, the insulating effect between the bit line and the common source line is increased, and the overall height of the insulating film is lowered.

Hereinafter, a NAND flash memory device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of films and regions are exaggerated for clarity. Also, where a film is said to be "on" another film or substrate, it may be formed directly on another film or substrate, or a third film may be interposed therebetween. Like numbers refer to like elements throughout the specification.

4 is a plan view illustrating a NAND flash memory device according to the present invention, and FIGS. 5 and 6 are cross-sectional views taken along line II of FIG. 4. 7 to 14 are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to an embodiment of the present invention, and FIG. 15 illustrates a common source line of a NAND flash memory device according to an embodiment of the present invention. It is sectional drawing cut in the longitudinal direction. 16 to 22 are cross-sectional views illustrating a method of manufacturing a NAND flash memory device according to another embodiment of the present invention, and FIG. 23 is a common source line of a NAND flash memory device according to another embodiment of the present invention. Is a cross-sectional view taken in the longitudinal direction.

(Example)

In the NAND type flash memory device according to the present invention, as shown in FIG. 4, a string selection line 300 extended and arranged in parallel in the same direction on a semiconductor substrate 100 such as silicon (Si). And a string 110 including a plurality of word lines 200 between a ground selection line 400 and a ground selection line 400. The bit line 700 extends in a direction substantially perpendicular to the direction in which the lines 200, 300, and 400 of the string 110 extend. Here, the drain of the string select line 300 (see 120 of FIG. 5) and the bit line 700 are electrically connected by a contact plug 600 made of a conductor. In addition, a common source line including a lower layer 510 electrically connected to a source of the ground select line 400 (see 140 in FIG. 5) and an upper layer 520 electrically insulated from the bit line 700. A common source line 500 is formed between the ground select lines 400. In the common source line 500, since the lower layer 510 should have an electrically conductive property, the lower layer 510 is preferably formed of a conductor such as polysilicon, and the upper layer 520 must have an electrically insulating property. In particular, it is preferable to form the nitride film having a high dielectric constant.

In such a structure, the source 140 of the ground select line 400 is electrically connected to the common source line 500 to provide a reference potential for programming, erasing, and reading the device. to provide. The drain 120 of the string select line 300 is electrically connected to the bit line 700 via the contact plug 600 to selectively provide a potential to the string 110.

On the other hand, between the substrate 100 and the bit line 700, an interlayer insulating film having a single layer structure or an interlayer insulating film having a multilayer structure having two or more layers is formed, which is a cross-sectional view taken along the line I-I of FIG. This will be described with reference to FIGS. 5 and 6.

Referring to FIG. 5, only one layer of the interlayer insulating layer 450 may be formed between the substrate 100 and the bit line 700. Here, the contact plug 600 penetrates the interlayer insulating film 450 to electrically conduct the drain 120 and the bit line 700 of the string select line 300. The common source line 510 penetrates the interlayer insulating film 450 and is electrically connected to the source 140 of the ground select line 400 by the lower layer 510 made of a conductor such as polysilicon. The 700 is electrically insulated from the upper film 520 made of a high dielectric constant material such as a nitride film. Accordingly, the common source line 500 and the bit line 700 are sufficiently insulated by the upper layer 520 made of a high dielectric constant material such as a nitride layer without intervening a separate interlayer insulating layer. In addition, since a separate interlayer insulating film for insulating between the common source line 500 and the bit line 700 is not formed, the height of the entire device is lowered.

Referring to FIG. 6, two layers of an interlayer insulating film including a first interlayer insulating film 450 ′ and a second interlayer insulating film 650 ′ may be formed between the substrate 100 ′ and the bit line 700 ′. . Here, the contact plug 600 'penetrates through the first interlayer insulating film 450' and the second interlayer insulating film 550 'to drain the bit 120' and the bit line 700 'of the string select line 300'. It is electrically conductive. The common source line 500 'penetrates through the first interlayer insulating layer 450' and is formed by a lower layer 510 'formed of a conductor such as polysilicon with the source 140' of the ground select line 400 '. Electrically conductive, the bit line 700 'is electrically insulated from the upper layer 520' made of a high dielectric constant material such as a nitride film and the second interlayer insulating film 550 'made of an oxide film or the like. Therefore, the common source line 500 'and the bit line 700' are electrically insulated by the second interlayer insulating film 550 'in addition to the upper film 520' made of a high dielectric constant material such as a nitride film, thereby maximizing the insulating effect. do.

Hereinafter, a method of manufacturing a NAND flash memory device according to an embodiment of the present invention will be described with reference to FIGS. 7 to 15.

In the method of manufacturing a NAND flash memory device according to one embodiment of the present invention, as shown in FIG. 7, first, a semiconductor substrate 100 made of a semiconductor element such as silicon is prepared. Next, the string 110 including the string select line 300, the word line 200, and the ground select line 400 through deposition of a predetermined material on the substrate 100, and provision of etching and ion implantation. ). In this case, the word line 200 is formed in a structure including a floating gate for storing data, and the string select line 300 or the ground select line 400 includes a floating gate because it does not require a floating gate for storing data. It is formed in a structure that does not. Subsequently, an interlayer insulating film 450 is formed by depositing an oxide film or the like on the entire surface of the substrate 100 on which the string 110 is formed.

Next, as shown in FIG. 8, a photoresist pattern (not shown) having a predetermined shape is formed on the interlayer insulating layer 450 by a photo process, and then a dry etching process using the photoresist pattern (not shown) as a mask is used. Thus, the interlayer insulating film 450 is selectively removed to expose the drain 140 of the ground select line 400. Thus, a first contact hole 470 is formed through the interlayer insulating film 450 to open the drain 140 of the ground select line 400. Next, a first conductor 510a is deposited on the interlayer insulating layer so as to fill the first contact hole 470.

Next, as illustrated in FIG. 9, the first conductor 510a is etched to expose the interlayer insulating film 450. At this time, a part of the first conductor 510a deposited in the first contact hole 470 is also etched to constitute the first conductor 510a, and has a height lower than that of the first contact hole 470 and the ground selection line. A lower layer 510 is formed to be electrically connected to the drain 140 of 400. Since the lower layer 510 should be electrically conductive, the lower layer 510 may be formed of a polysilicon layer, and may be formed of another conductive material.

Next, as shown in FIG. 10, an insulator 520a is deposited on the interlayer insulating layer 470 so that the remaining portion which is not buried in the first contact hole 470 in which the conductive lower layer 510 is formed is buried. do.

Next, as shown in FIG. 11, the insulator 520a is planarized by chemical mechanical polishing (CMP) so that the interlayer insulating film 450 is exposed. Thus, an upper film 520 formed of the insulator 520a and electrically insulated from the bit line (see 700 of FIG. 14) formed in a subsequent process is formed. Accordingly, the lower layer 510 is electrically connected to the source 140 of the ground select line 400, and is electrically insulated from the subsequent bit line (see 700 in FIG. 14) formed on the lower layer 510. The common source line 500 formed of the upper layer 520 is formed. The upper film 520 is preferably formed of a nitride film having excellent insulating properties, and of course, may be formed of another insulating material.

Next, as illustrated in FIG. 12, the interlayer insulating layer 450 is selectively removed to expose the drain 120 of the string select line 300 to form a second contact hole 570. Subsequently, the second contact hole 570 is buried by deposition of the second conductor on the interlayer insulating film 450, a chemical mechanical polishing process, or the like to form a contact plug 600.

Next, as shown in FIG. 13, a predetermined oxide film 640a is formed on the interlayer insulating film 450 on which the common source line 500 and the contact plug 600 are formed. At this time, the oxide film 640a is to insulate the space between the bit lines (see 700 of FIG. 14) formed subsequently. Meanwhile, in order to protect the interlayer insulating film 450 formed under the oxide film 640a from etching damage during the etching process on the oxide film 640a before the oxide film 640a is formed, a predetermined etching protective film 620a is further added. Can be formed.

Next, as shown in FIG. 14, after the oxide film 640a is patterned by using a photo process and an etching process, the bit lines 700 spaced apart from each other by the patterned oxide film (see 640 of FIG. 15) are formed. Form. In this case, the bit line 700 is electrically connected to the contact plug 600, but is electrically insulated from the common source line 500 by the upper layer 520 formed of a nitride film having excellent insulation. If the etching protection film 620a is further formed, the etching protection film 620a is patterned like the oxide film 640a.

As shown in FIG. 15, taken along the line II-II of FIG. 4, the common source line 500 is electrically connected to the substrate 100 by the conductive underlayer 510 and to the relief and the source of the ground selection line. Is conducted. In addition, the common source line 520 is sufficiently electrically insulated from the bit line 700 by the upper layer 520 having excellent insulation property. Therefore, a separate insulating film is not required to electrically insulate between the common source line 520 and the bit line 700. Meanwhile, the bit lines 700 are spaced apart from each other by the patterned oxide layer 640 or the patterned oxide layer 640 and the etching protection layer 620.

Subsequently, a subsequent process is performed to form a common source line consisting of a conductive lower layer and an insulating upper layer, thereby eliminating the need for a separate interlayer insulating layer for electrical insulation between the common source line and the bit line. Complete the device.

Hereinafter, a method of manufacturing a NAND flash memory device according to another embodiment of the present invention will be described with reference to FIGS. 16 to 23.

As shown in FIG. 16, a method of manufacturing a NAND flash memory device according to another exemplary embodiment of the present invention may include a string select line 300 'and a word line 200' on a semiconductor substrate 100 '. After forming the string 110 ′ including the ground select line 400 ′, an oxide layer or the like is deposited on the entire surface of the substrate 100 ′ on which the string 110 ′ is formed to form a first interlayer dielectric layer 450 ′. do.

Next, as shown in FIG. 17, the first interlayer insulating film 450 ′ is selectively removed to expose the drain 140 ′ of the ground select line 400 ′. Thus, a first contact hole 470 'is formed through the first interlayer insulating film 450' to open the drain 140 'of the ground select line 400'. Next, a lower layer having a height lower than that of the first contact hole 470 'and electrically connected to the drain 140' of the ground select line 400 'by using the deposition and etching process of the first conductor. 510 '. The lower film 510 'is formed of a polysilicon film or other conductor film.

Subsequently, as shown in FIG. 18, the remaining unfilled portion of the first contact hole 470 ′ in which the lower layer 510 ′ is formed is filled with an insulator using deposition and chemical mechanical polishing processes. Thus, an upper film 520 'is electrically insulated from the subsequent bit line (see 700' in FIG.). As a result, a lower layer 510 'electrically conductive with the source 140' of the ground select line 400 ', and a subsequent bit line formed on the lower layer 510' (see 700 'in FIG. 22). ) Is formed with a common source line 500 ', which is composed of an upper layer 510' electrically insulated from each other. The upper film 520 'is preferably formed of a nitride film having excellent insulating properties, and of course, may be formed of another insulating material.

Next, as illustrated in FIG. 19, an oxide film or the like is deposited on the first interlayer insulating film 450 ′ on which the common source line 500 ′ is formed to form a second interlayer insulating film 550 ′.

Next, as shown in FIG. 20, the second interlayer insulating film 550 ′ and the first interlayer insulating film 450 ′ are selectively removed to expose the drain 120 ′ of the string select line 300 ′. A contact hole 570 'is formed. Thereafter, the second contact hole 570 'is filled with the second conductor by deposition of the second conductor on the second interlayer insulating film 550', chemical mechanical polishing, or the like to form a contact plug 600 '. do.

Next, as shown in FIG. 21, a predetermined oxide film 640a 'is formed on the second interlayer insulating film 550'. At this time, the oxide film 640a 'is to insulate the space between the subsequent formed bit lines (see 700' of FIG.). Meanwhile, in order to protect the second interlayer insulating film 550 'formed under the oxide film 640a' during the etching process on the oxide film 640a 'before forming the oxide film 640a', the predetermined etching is performed. The passivation layer 620a 'may be further formed.

Next, as shown in FIG. 22, after patterning the oxide film 640a 'using a photo process and an etching process, the bit lines 700' spaced apart from each other by the patterned oxide film (see 640 of FIG. 23). To form. At this time, the bit line 700 'is electrically connected to the contact plug 600', but the upper layer 520 'and the first interlayer insulating layer 450 formed of a nitride film having excellent insulation with the common source line 500'. Electrically insulated by '). If the etching protection film 620a 'is further formed, the etching protection film 620a' is patterned like the oxide film 640a '.

Referring to FIG. 23 in which the common source line 500 'is cut in the longitudinal direction, the common source line 500' is formed by the conductive lower layer 510 ', which is a substrate 100', and a relief line is a ground selection line. Is electrically connected to the source. In addition, the common source line 500 ′ is sufficiently electrically insulated from the bit line 700 ′ by the upper layer 520 ′ formed of the first interlayer insulating layer 450 ′ and the nitride film having excellent insulation property. Therefore, since the second interlayer insulating film 550 'and the upper film 520' having excellent insulating property are formed between the common source line 500 'and the bit line 700', they are electrically sufficiently insulated. Meanwhile, the bit lines 700 ′ are spaced apart from each other by the patterned oxide layer 640 ′, or the patterned oxide layer 640 ′ and the etching protection layer 620 ′.

Subsequently, a subsequent process is performed to form a common source line composed of a conductive lower layer and an insulating upper layer, thereby completing a NAND type flash memory device having excellent insulation effect between the bit line and the common source line.

As described above, according to the NAND-type flash memory device and the manufacturing method thereof according to the present invention, there is an effect that the insulation effect between the bit line and the common source line is increased. In addition, by lowering the overall height of the insulating film, there is an effect that the subsequent process becomes easy.

1 is a plan view illustrating a NAND type flash memory device according to the prior art.

FIG. 2 is a cross-sectional view taken along line II of FIG. 1.

3 is a cross-sectional view taken along the line II-II of FIG. 1.

4 is a plan view illustrating a NAND flash memory device according to the present invention.

5 and 6 are cross-sectional views taken along the line II of FIG. 4.

7 to 14 are cross-sectional views illustrating processes for manufacturing a NAND flash memory device according to an embodiment of the present invention.

15 is a cross-sectional view of a common source line of the NAND type flash memory device cut in the length direction according to an embodiment of the present invention.

16 to 22 are cross-sectional views of processes illustrating a method of manufacturing a NAND flash memory device according to another embodiment of the present invention.

FIG. 23 is a cross-sectional view taken along a length of a common source line of a NAND type flash memory device according to another exemplary embodiment of the present inventive concept.

Explanation of symbols on main parts of drawing

100; A semiconductor substrate 110; String

120; Drain 140 of string select line; Source of ground select line

200; Word line 300; String select line

400; Ground select line 450; Interlayer insulation film

470; First contact hole 500; Common source line

510; Bottom layer 520; Top film

570; Second contact hole 600; Contact plug

700; Bit line

Claims (10)

Semiconductor substrates; A string including a string select line, a word line, and a ground select line arranged on the substrate and extending in the same direction and arranged in parallel; A bit line extending in a direction substantially perpendicular to a direction in which each line constituting the string extends; A contact plug in electrical connection with the drain of the string select line and the bit line; And A common source line including a lower layer made of a conductor electrically connected to the source of the ground selection line and an upper layer made of an insulator electrically insulated from the bit line; NAND flash memory device comprising a. The method of claim 1, One layer of interlayer insulating film is formed between the substrate and the bit line, The contact plug electrically penetrates the drain and the bit line of the string select line through the interlayer insulating layer. The common source line penetrates the interlayer insulating layer, and is electrically connected to the source of the ground selection line by the lower layer, and is electrically insulated from the bit line by the upper layer. Memory elements. The method of claim 1, Two interlayer insulating films comprising a first interlayer insulating film and a second interlayer insulating film are formed between the substrate and the bit line; The contact plug electrically connects the drain and the bit line of the string select line through the first interlayer insulating film and the second interlayer insulating film. The common source line penetrates through the first interlayer insulating layer, and is electrically connected to the source of the ground selection line by the lower layer, and is electrically insulated from the bit line by the upper layer and the second interlayer insulating layer. NAND flash memory device, characterized in that. The method according to any one of claims 1 to 3, And the upper layer is a polysilicon layer, and the upper layer is a nitride layer. Providing a semiconductor substrate; Forming a string including a string select line, a word line, and a ground select line on the substrate; Forming an interlayer insulating film on an entire surface of the substrate on which the string is formed; Selectively removing the interlayer insulating layer to expose a drain of the ground select line to form a first contact hole; The first contact hole is sequentially filled with a first conductor and an insulator, and is formed of the first conductor and is electrically connected to the source of the ground selection line, and the insulator is electrically connected to the bottom layer. Forming a common source line including an insulated top layer; Selectively removing the interlayer insulating layer to expose a drain of the string select line to form a second contact hole; Filling the second contact hole with a second conductor to form a contact plug; And And forming a bit line on the interlayer insulating layer, the bit line being electrically insulated from the common source line by the upper layer and electrically connected to the contact plug. . The method of claim 5, Forming the common source line, Depositing a first conductor on the interlayer insulating film to fill the first contact hole; The first conductor is etched to expose the interlayer insulating layer, and a portion of the first conductor deposited in the first contact hole is etched to constitute the first conductor and has a height lower than that of the first contact hole. Forming a lower layer in electrical communication with the drain of the ground select line; Depositing an insulator on the interlayer insulating film such that the remaining portion of the first contact hole in which the lower layer is formed is not buried; And And planarizing the insulator by chemical mechanical polishing so that the interlayer insulating film is exposed, thereby forming an upper film composed of the insulator and electrically insulated from the bit line. The method according to claim 5 or 6, And the lower layer is formed of a polysilicon layer, and the upper layer is formed of a nitride layer. Providing a semiconductor substrate; Forming a string including a string select line, a word line, and a ground select line on the substrate; Forming a first interlayer insulating film on an entire surface of the substrate on which the string is formed; Selectively removing the first interlayer insulating layer to expose a drain of the ground select line to form a first contact hole; The first contact hole is sequentially filled with a first conductor and an insulator, and is formed of the first conductor and is electrically connected to the source of the ground selection line, and the insulator is electrically connected to the bottom layer. Forming a common source line including an insulated top layer; Forming a second interlayer insulating film on the first interlayer insulating film; Selectively removing the second interlayer dielectric layer and the first interlayer dielectric layer so that the drain of the string select line is exposed to form a second contact hole; Filling the second contact hole with a second conductor to form a contact plug; And And forming a bit line on the second interlayer insulating layer, the bit source being electrically insulated from the common source line by the upper layer and the first interlayer insulating layer and electrically connected to the contact plug. Method of manufacturing type flash memory device. The method of claim 8, Forming the common source line, Depositing a first conductor on the first interlayer insulating film to fill the first contact hole; The first conductor is etched to expose the first interlayer insulating layer, and a portion of the first conductor deposited in the first contact hole is also etched to form a height lower than the height of the first contact hole. Forming a bottom layer having a bottom layer and electrically connected to a drain of the ground select line; Depositing an insulator on the first interlayer insulating film such that the remaining portion of the first contact hole in which the lower layer is formed is not buried; And planarizing the insulator by chemical mechanical polishing so that the first interlayer insulating film is exposed, thereby forming an upper film composed of the insulator and electrically insulated from the bit line. Way. The method according to claim 8 or 9, And the lower layer is formed of a polysilicon layer, and the upper layer is formed of a nitride layer.