KR20010027677A - Flash memory device and manufacture method thereof - Google Patents

Abstract

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a flash memory device and a method for manufacturing the same. A flash memory device according to the present invention includes a drain and a source formed in an active region extending in the longitudinal direction, a floating gate formed on a channel between the drain and the source, an interlayer dielectric film formed on the floating gate, and a word extended in the horizontal axis direction. A stacked gate as a control gate as a line, a first bit line contact and a common source line contact formed on a drain and a source in a self-matching contact manner, and extending in a direction parallel to the active region connected to the first bit line contact; And a common source line extending in a direction parallel to the bit line and a word line connected to the common source line contact.

Description

Flash memory device and method for manufacturing same

TECHNICAL FIELD The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a flash memory device and a method for manufacturing the same.

Electrically Programmable Read Only Memory (EPROM), widely used as a nonvolatile memory device, can program data electrically, but in order to erase the input data, it is necessary to separate the chip from the system and scan ultraviolet rays. Accompanied by remorse. In addition, in order to expose a cell to ultraviolet rays, a light transmitting window is required in the package. In order to overcome this complexity in data erasing, a flash EEPROM was introduced by Masuoka in 1984 in IEDM p.464 as a nonvolatile memory device capable of electrically writing and erasing data.

Flash EEPROM is divided into NOR type and NAND type according to the type of cell connected to the bit line. The basic structure of stacked gate flash EEPROM cells, which are widely used among NOR flash EEPROMs, was described in US Pat. No. 4,203,158 by Froman-Bentchkowsky. Such stacked cells are characterized by programming and erasing data by Fowler-Nordheim tunneling.

A cell transistor constituting another type of stacked gate flash EEPROM has been introduced by Mukher jee in US Pat. No. 4,698,787, the structure of which is shown in FIG. The cell is programmed by forming channel hot electrons near the drain 16 and injecting them into the floating gate 12 from the side of the drain, followed by Fowler-Nordheim tunneling. Electrons injected into the N-channel are discharged to a channel near the source 18 to be erased. In FIG. 1, reference numeral 10 denotes a semiconductor substrate, and 14 denotes a control gate.

In the cell structure of the NOR flash EEPROM, two cell transistors are connected in series to one bit line contact, and these two cell transistors share a common source line. The same equivalent circuit can be simplified.

According to the cell structure of the NOR flash EEPROM, as the degree of integration of semiconductor devices increases, the ratio of the area of the bit line contact to the cell becomes larger. An increase in the occupancy ratio of the bit line contacts for such a cell is described with reference to the top view of FIG.

First, referring to FIG. 3, since the bit line contact R4 and the word line (ie, the control gate) R3 should not be electrically connected to each other, a minimum separation distance L1 is required and is common from the word line R3. Even the source active R1 requires a minimum separation distance L2. That is, the NOR-type flash EEPROM cells of FIGS. 3 and 4 have minimum separation distances L1 and L2 from bit line contact R4 to word line R3 and from word line R3 to common source active R1, respectively. This minimum separation distance must be maintained even if the total cell area is reduced, so that the percentage of bit line contacts to the cell increases with increasing density. There is also a limit to cell area reduction.

In FIG. 3, reference numeral "R2" denotes a floating gate, "R5" denotes a bit line, and in FIG. 4, reference numeral "20" denotes a semiconductor substrate and "22" denotes a tunneling oxide film. Where "24" is the floating gate, "26" is the interlayer dielectric, "28" is the polysilicon layer of the control gate (i.e. word line), "30" is the silicide layer of the control gate, "32" Is a spacer, "34" is a drain, "36" is a common source active, "38" is an interlayer insulating film, "40" is a bit line contact, and "42" is a bit line.

The bit line contacts 40 and the control gates (ie word lines) 28 and 30 are spaced apart by a minimum separation distance L1, as shown in FIG. 3, for electrical isolation. Therefore, there is a limit to the reduction of the cell area by this minimum separation distance L1.

SUMMARY OF THE INVENTION An object of the present invention is to provide a flash memory device capable of reducing the area ratio of the bit line contact to the cell and facilitating the reduction of the cell area.

Another object of the present invention is to provide a manufacturing method most suitable for manufacturing the flash memory device.

1 is a cross-sectional view illustrating a cell transistor of a conventional stacked flash memory device.

2 is an equivalent circuit diagram of a NOR type EEPROM.

3 is a plan view of portion A of FIG. 2.

4 is a cross-sectional view of portion B of FIG. 2.

5 is a plan view of a flash memory device according to an embodiment of the present invention.

6 is a cross-sectional view taken along line VI-VI ′ of FIG. 5.

7 to 15 are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention in order of process.

In order to achieve the above object, a flash memory device according to the present invention includes a drain and a source formed in an active region extended in a longitudinal axis direction, a floating gate formed on a channel between the drain and the source, and formed on the floating gate. An interlayer dielectric layer, a stacked gate formed of a control gate as a word line extending in the horizontal axis direction, a first bit line contact and a common source line contact formed on a drain and a source in a self-matching contact manner, and connected to the first bit line contact; And a bit line extending in a direction parallel to the active region, and a common source line extending in a direction parallel to the word line connected to the common source line contact.

And a second bit line contact connected to the bit line on the first bit line contact, wherein the common source line is formed in a damascene manner.

According to another aspect of the present invention, there is provided a method of fabricating a flash memory device, the method including forming a stacked gate on a semiconductor substrate, forming a spacer on the sidewall of the stacked gate, and forming a spacer between the stacked gates. Forming a drain and a source in the active region, forming a first interlayer insulating layer, and then forming contact holes on the drain and the source in a self-matching contact manner, respectively, and filling the contact holes with a metal material. Forming a first bit line contact connected to the drain and a common source line contact connected to the source, forming a second interlayer insulating layer, and then damming a common source line connected to the common source line contact The second bit line contact connected to the first bit line contact after forming the semiconductor layer, and forming a third interlayer insulating layer. And forming a bit line connected to the first bit line contact through the second bit line contact.

Therefore, according to the present invention, the area ratio of the bit line contact to the cell can be reduced, and the cell area can be easily reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and the like of the elements in the drawings are exaggerated to emphasize a more clear description, and the elements denoted by the same reference numerals in the drawings means the same elements.

5 is a plan view of a flash memory device according to an embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line VI-VI 'of FIG. 5.

In FIG. 5, "R10" represents an active region, "R12" represents a word line, "R14" represents a bit line contact, "R16" represents a common source line contact, "R18" represents a common source line, and "R20" represents a bit line.

Flash memory device according to an embodiment of the present invention, unlike the prior art (see FIGS. 3 and 4) that first connected the source of each cell transistor through the source active, through a common source line (R18, 78) of metal Connect to each other. In this case, the common source line is connected to the source 68 of each cell transistor through the common source line contacts R16 and 74. Since the common source line contacts R16 and 74 and the first bit line contacts R14 and 72 are formed in a self-aligned manner, a minimum between the conventional bit line contacts R14 and the word lines R12 is conventional. The separation distance (L1 and L2 in FIGS. 3 and 4) can be eliminated, and the minimum separation distance between the source active and the word line can also be eliminated because the source of each cell transistor is connected to a common source line.

That is, since the first bit line contacts R14 and 72 are formed by the self-matching contact method, the distance from the word lines R12 and 61 to the first bit line contacts R16 and 74 can be eliminated, and Instead of the conventional structure in which the source is connected to the active line, the common source line contacts R16 and 74 are formed on the source 68 in a self-matching contact manner, and then the damin is parallel to the word lines R12 and 61. Since the source lines of the cell transistors are connected by forming the common source lines R18 and 78 according to the method, the minimum separation distance from the word lines R12 and 61 to the source 66 can be eliminated. Therefore, the cell area can be effectively reduced.

More specifically, there is a drain 66 and a source 68 formed in the active region R10 extending in the longitudinal direction, and the floating gate 54 is formed on the channel between the drain 66 and the source 68. There is an interlayer dielectric film 56 and a control gate 61 as a word line R12 extending in the horizontal axis direction, and first bit line contacts R14 and 72 formed on the drain 66 and the source 68 in a self-matching manner, respectively. ) And common source line contacts (R16, 74). The first bit line contacts R14 and 72 are connected to the bit lines R20 and 84 extending in a direction parallel to the active region R10 through a second bit line contact 82 and the common source line. The contacts R16 and 74 are connected to the common source lines R18 and 78 formed in a damascene manner extending in a direction parallel to the word lines R12 and 61.

7 to 15 are cross-sectional views illustrating a method of manufacturing a flash memory device according to an embodiment of the present invention in order of process.

First, referring to FIG. 7, a tunnel oxide film 52 having a thickness of about 100 μs is formed on a P well (not shown) formed in the silicon substrate 50, and extends in a direction parallel thereto on the active region. After forming the polysilicon layer having a thickness of about 1,000 mW to be used as the floating gate 54, the interlayer dielectric film 56, the polysilicon layer 58, and the tungsten silicon film WSi having a thickness of about 2,000 mW ( 60) and a silicon nitride film 62 having a thickness of about 3,000 mm 3 in order.

Referring to FIG. 8, the silicon nitride layer 62, the tungsten silicon layer 60, the polysilicon layer 58, the interlayer dielectric layer 56, and the floating gate 54 are sequentially etched through a photolithography process. Form a stacked gate. In this case, the floating gate 54 is formed to be isolated in each channel region of the cell transistor, and includes a control gate (ie, word lines R12 and 61) formed of a polysilicon layer 58 and a tungsten silicon layer 60. ) Is formed to extend in the direction orthogonal to the active region R10.

Referring to FIG. 9, a drain 66 and a source 68 of the cell transistor are formed through an ion implantation process, and a nitride layer is deposited and then etched to form spacers 64 on the sidewalls of the stacked gates.

Referring to FIG. 10, a first interlayer insulating layer 70a is formed by depositing a boron phosphorus doped silicon glass (BPSG) insulating film to a thickness of about 5,000 μs and then planarizing the surface thereof through a planarization process.

Referring to FIG. 11, a bit line contact hole (drain) of a shape that is self-aligned to a stacked gate by etching the first interlayer insulating layer 70 through a photolithography process using a mask pattern having the same shape as R14 and R16 of FIG. 5. (66) holes and a common source line contact hole (holes on the source 68) are formed. At this time, the etching condition is performed such that the selectivity ratio between the BPSG insulating material constituting the first interlayer insulating layer 70 and the silicon nitride film constituting the spacer 64 is 10: 1 or more, and the stacked gate is not exposed. Therefore, since the minimum separation distance between the bit line contact hole and the stacked gate does not need to be considered, the cell area can be effectively reduced.

Referring to FIG. 12, the tungsten (W) is deposited to fill contact holes, and then chemical mechanical poly (CMP) is performed until the first interlayer insulating layer 70 is exposed, thereby connecting to the drain 66. The first bit line contacts R14 and 72 are formed and the common source line contacts R16 and 74 are connected to the source 68.

Referring to FIG. 13, after forming the second interlayer insulating layer 76, the second interlayer insulating layer 76 is patterned to expose the common source line contact 74 through a photolithography process. Thereafter, after depositing tungsten (W), the common source line 78 is formed by leaving only the tungsten on the common source line contact 74 through the chemical mechanical polysilicon. The above processes for forming the common source line 78 are the same as the conventional damascene process.

Referring to FIG. 14, after forming the third interlayer insulating layer 80, the bit line is connected on the first bit line contact 72 to the drain 66 through the first bit line contact 72. The second bit line contact 82 is formed in the same manner as the method of forming the common source line in the damascene process.

Referring to FIG. 15, a metal material such as aluminum (Al) is formed to a thickness of about 6,000 Å, and thereafter, bit lines R20 and 84 are formed to extend in a direction parallel to the active region through a photolithography process.

According to the flash memory device and the manufacturing method thereof according to the present invention, since the bit line contact is formed by the self-matching contact method, the minimum separation distance from the bit line contact to the word line can be removed, and the source is formed by the self-matching contact method Connecting to a common source line via a common source line contact eliminates the minimum separation distance from the word line to the source active, thereby reducing the area ratio of the bit line contact to the cell and at the same time reducing the cell area. can do.

Claims (6)

A drain and a source formed in the active region extended in the longitudinal axis direction; A stacked gate formed of a floating gate formed on the channel between the drain and the source, an interlayer dielectric film formed on the floating gate, and a control gate as a word line extending in the horizontal axis direction; A first bit line contact and a common source line contact formed on the drain and the source in a self-matching contact manner; A bit line extending in a direction parallel to the active region connected to the first bit line contact; And And a common source line extending in a direction parallel to the word line connected to the common source line contact. The method of claim 1, And a second bit line contact connected to the bit line on the first bit line contact. The method of claim 1, And said common source line is formed in a damascene manner. Forming a stacked gate on the semiconductor substrate; Forming a spacer on the stacked gate sidewalls; Forming a drain and a source in an active region between the stacked gates; After forming the first interlayer insulating layer, forming contact holes on the drain and the source in a self-matching contact manner, respectively; Filling the contact holes with a metal material to form a first bit line contact connected to the drain and a common source line contact connected to the source; After forming a second interlayer insulating layer, forming a common source line connected to the common source line contact; And And forming a bit line connected to the first bit line contact after forming a third interlayer insulating layer. The method of claim 4, wherein And forming a second bit line contact connected to the first bit line contact in a damascene manner after forming a third interlayer insulating layer. The method of claim 4, wherein The common source line is a method of manufacturing a flash memory device, characterized in that formed in the damascene method.