KR100386575B1 - PN code correlator and Method for acquisition received signal's synchronization using the same - Google Patents

Abstract

The present invention relates to a receiver of a communication system, and more particularly, to a PN code correlator and a method of acquiring signal synchronization thereof, which are suitable for reducing the synchronization acquisition time of a received signal in a code division multiple access communication system. The PN code correlator according to the present invention comprises a code generator for generating a pseudo noise sequence, a code mixer for multiplying the generated pseudo noise sequence by a received signal, and dividing the total accumulation time into a plurality of partial accumulation times. An accumulator for accumulating the output signal of the code mixer based on each set accumulating time, a control signal generator for generating a code shift control signal for adjusting a pseudo noise sequence of the code generator at each set accumulating time, The code generator receives the accumulated value for each partial accumulation time and the code shift control signal from an accumulator, and determines the synchronization possibility of the received signal for each partial accumulated time, and generates the code shift control signal based on the determination result. Determination unit provided to, and when accumulating the total from the accumulator Comparing the final accumulated value accumulated over a predetermined period and the predetermined threshold value to determine whether or not the synchronization of the received signal is finally determined, it is possible to quickly determine whether to obtain the synchronization PN code of the received signal without having to take a predetermined accumulation time As a result, the synchronization acquisition time for the received signal is reduced.

Description

PN code correlator and method for acquisition received signal's synchronization using the same}

The present invention relates to a receiver of a communication system, and more particularly, to a PN code correlator and a method for acquiring a received signal synchronization using the same in a code division multiple access method of a mobile communication system.

In general, in a code division multiple access communication system, a transmitter spreads information to be transmitted in a wide band by using spread spectrum communication, and a receiver inverts a signal to an original bandwidth. Despreading to receive.

In this case, as the spread spectrum communication method, a direct sequence method, a frequency hopping method, a time hopping method, and a hybrid method have been proposed. In particular, the direct sequence method uses a high data rate pseudo noise sequence (PN). (Abbreviated as code) to spread and despread to communicate.

In such a communication system, a PN code correlator is provided in a receiver to perform synchronization of a received signal.

1 is a block diagram illustrating a conventional PN code correlator.

Referring to FIG. 1, a conventional PN code correlator includes a PN code generator 105 generating a PN code, a code mixer 100 multiplying a received signal by a PN code generated by the PN code generator 105, and despreading the received signal. Whether or not the received signal is synchronized by comparing an N bit accumulator 101 that accumulates an output signal of the code mixer 100 for a predetermined accumulating time with a correlation threshold already set with an output of the N bit accumulator 101. Code shift control at a predetermined time to determine a comparator 102 for generating a lock signal when synchronization is obtained and a PN code generated by the PN code generator 105. A code shift control signal generator 104 that generates a signal and provides it to the PN code generator 105, and a PN clock generator that provides a basic PN clock to the PN code generator 105 and the code shift control signal generator 104. (10 3) consists of.

The operation of the conventional PN code generator configured as described above is as follows.

First, the received signal is input to the code mixer 100, and the code mixer 100 despreads the received signal by multiplying the received signal by the PN code generated by the PN code generator 105.

The output of this code mixer 100 is input to the N-bit accumulator 101, which accumulates the output of the code mixer 100 for a certain accumulation time (i.e., M time). Here, the constant accumulation time M coincides with the generation period of the code shift control signal generated by the code shift control signal generator 104 every predetermined time.

Subsequently, the N-bit accumulator 101 outputs the accumulated value of the accumulated n-bits to the comparator 102, and the comparator 102 compares the input accumulated value with a previously set correlation threshold. At this time, the comparator 102 determines that the synchronization of the received signal is acquired if the accumulated value of the input is greater than the threshold value, and generates a lock signal. If the accumulated value is less than the threshold value, the synchronization of the received signal is lost. It is determined that it is not obtained and does not generate a synchronization acquisition signal.

Then, the code shift control signal generator 104 shifts the PN code generated by the PN code generator 105 at a predetermined constant accumulation time M when the synchronization acquisition signal is not generated by the comparator 102. On the other hand, if the synchronization acquisition signal is generated in the comparator 102, the code shift control signal is not generated.

Accordingly, the PN code generator 105 generates the PN code according to the code shift control signal generated by the code shift control signal generator 104. Occurs by shifting by chip.

The operation of the PN code correlator described so far is repeated until synchronization of the received signal is obtained.

FIG. 2 is a signal timing diagram illustrating a code shift control signal generated at a predetermined accumulation time M in a conventional code shift control signal generator.

Referring to FIG. 2, it can be seen that the code shift control signal and the constant accumulation time M of the N-bit accumulator have the same time period.

However, such a conventional PN code generator acquires the synchronization of the reception signal by accumulating the reception signal continuously despread for a predetermined predetermined accumulation time (M) in order to know whether the reception signal is synchronized with the PN code generated by itself. There is a problem that takes a lot of time.

Accordingly, an object of the present invention is to provide a PN code correlator and a signal synchronization acquisition method thereof that can reduce the synchronization acquisition time of a received signal.

According to an apparatus feature of the present invention for achieving the above object, a PN code correlator includes a code generator for generating a pseudo noise sequence, a code mixer for multiplying the generated pseudo noise sequence by a received signal, and a plurality of total accumulation times. The partial partial accumulation time, the accumulator for accumulating the output signal of the code mixer based on the set partial accumulation time, and the code shift control signal for adjusting the pseudo noise sequence of the code generator. A control signal generator that is generated every time, the accumulated value for each partial accumulation time and the code shift control signal are received from the accumulator, and the possibility of synchronization acquisition of the received signal is determined according to the corresponding partial accumulation time, and according to the determination result. Providing the generated code shift control signal to the code generator And a determiner and a comparator for finally determining whether the received signal is synchronized by comparing a final accumulated value accumulated during the total accumulation time in the accumulator with a preset threshold.

Preferably, the determination unit receives a multiplication of the accumulated value for the desired partial accumulation time from the accumulator, and receives a code shift control signal from the control signal generator and multiplies and multiplies the AND gates. And OR logic for receiving the output of the sum operation and outputting the result to the code generator.

According to the method feature of the present invention for achieving the above object, by setting the total accumulation time divided into a plurality of partial accumulation time, the accumulator is despread to accumulate the input signal based on the set partial accumulation time Outputs each partial accumulation value for the corresponding partial accumulation time. Then, the determining unit checks whether each of the output partial accumulated values is a value obtained by synchronizing with the received signal, and according to the check result, the output partial accumulated value is a received signal at the corresponding partial accumulation time. If the synchronization is not an acquired value, a code shift control signal for adjusting a pseudo noise sequence is provided to a code generator, and if the output partial accumulation value is a value obtained by synchronizing a received signal at the corresponding partial accumulation time, pseudo noise The code shift for adjusting the sequence does not provide a control signal to the code generator.

Preferably, the partial accumulation time is divided and set by the time at which the k-th bit of the N-bit accumulator becomes 1, and each of the outputted partial accumulator values is the k-th bit of the N-bit accumulator (k = 1 to N). to be. In the adjusting step, when the output partial accumulation value is not a value obtained by synchronizing a received signal at a corresponding partial accumulation time, a code shift control signal for adjusting a pseudo noise sequence is provided to a code generator. The code shift control signal for adjusting the pseudo noise sequence is not provided to the code generator when the partial accumulated value is a value obtained by synchronizing the reception signal at the corresponding partial accumulation time.

1 is a block diagram showing a conventional PN code correlator.

FIG. 2 is a signal timing diagram illustrating a code shift control signal generated at a predetermined accumulation time M in a conventional code shift control signal generator. FIG.

3 is a block diagram illustrating a PN code correlator according to the present invention;

FIG. 4 is a detailed circuit diagram illustrating a determination unit shown in FIG. 3.

5 is a signal timing diagram illustrating a code shift control signal generated by a code shift control signal generator at every partial accumulation time in accordance with the present invention.

6 is a flowchart illustrating a method of obtaining synchronization of a received signal of a PN code correlator according to the present invention;

* Description of the symbols for the main parts of the drawings *

300: code mixer 301: N-bit accumulator

302: comparator 303: determination unit

304: code shift control signal generator 305: PN code generator

306: PN Clock Generator

Hereinafter, a configuration and an operation according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

The present invention proposes a PN code correlator and a signal synchronization acquisition method thereof that can reduce the synchronization acquisition time of a received signal.

The PN code correlator according to the present invention divides a predetermined total accumulation time to set a plurality of auxiliary accumulation times, and checks the accumulated accumulation value during the set auxiliary accumulation time to determine in advance whether to acquire synchronization with respect to the received signal.

To this end, the PN code correlator according to the present invention further includes a determining unit which determines whether the received signal is synchronized by checking the accumulated value during the auxiliary accumulation time.

In particular, the present invention can reduce the synchronization acquisition time by detecting in advance that synchronization is not obtained by generating a code shift control signal for shifting the PN code generated by the PN code generator according to the set auxiliary accumulation time.

3 is a block diagram illustrating a PN code correlator according to the present invention.

Referring to FIG. 3, the PN code correlator according to the present invention multiplies the PN code generator 305 generating the PN code with the PN code generated by the PN code generator 305 to despread the received signal. 300, an N-bit accumulator 301 that accumulates the output of the code mixer 300 based on a plurality of set partial accumulation times, and a correlation threshold that is already set with an output of the N-bit accumulator 301. A final slew of the comparator 302 and a PN code generated by the PN code generator 305 and a comparator 302 for finally determining whether the received signal is synchronized and generating a lock signal when synchronization is obtained are obtained. The code shift control signal generator 304 for generating a code shift control signal for each partial accumulation time set to be set, and the code shift according to the accumulated value accumulated for each partial accumulation time in the N-bit accumulator 301. Control unit 303 for providing the code shift control signal generated by the control signal generator 304 to the PN code generator 305, and the PN code generator 305 and the code shift control signal generator 304. And a PN clock generator 306 that provides a clock. That is, the decision unit 303 receives a signal corresponding to the code shift signal of the code control signal generator 304 and the partial accumulation time of the accumulator 301, and thus the final code shift. If the output of the accumulator 301 exceeds the threshold value, a synchronization acquisition occurs, so that the code shift does not occur during the entire accumulation time M, and the partial accumulation periods n, 2n, 4n, ... During the 2 (a-1) n, M) (a: 1,2,3 ...), the decision unit 303 uses the signals received from the accumulator 301 to determine the possibility of synchronization acquisition, Accordingly, the code shift control signal of the code shift control signal generator 304 is generated by the PN code generator 305 or , Does not occur. At this time, as shown in Table 2, the number of partial accumulations can be set to 20 or 40 times to reduce the synchronization acquisition time. The code shift control signal generator 304 receives the synchronization acquisition signal of the comparator 302 to accumulate each partial accumulation time. Each time, the PN code generator 305 generates a control signal for a necessary code shift. The comparator 302 compares the accumulated value and the threshold value accumulated from the accumulator 301 with a preset threshold to synchronize the received signal. Is generated, a synchronization acquisition signal is generated. If the synchronization acquisition signal is received, the code shift control signal generator 304 generates the code shift control signal to the decision unit 303. If the synchronization acquisition signal is not received, the code shifting control signal is not generated to the decision unit 303. Although the code shift control signal is generated once in the total accumulation time, in the present invention, the partial accumulation time (n, 2n, 4n, ..., 2 (a-1) n, M) (a: 1, 2, 3 ...) The difference is that the code shift can generate a control signal.

The operation of the PN code correlator configured as described above is as follows.

First, the received signal is input to the code mixer 300, and the code mixer 300 despreads the received signal by multiplying the received signal by the PN code generated by the PN code generator 305.

The output of the code mixer 300 is input to the N-bit accumulator 301, and the N-bit accumulator 301 accumulates the output of the code mixer 300 for a predetermined accumulation time M. At this time, the N-bit accumulator 301 divides the total accumulation time into a plurality of partial accumulation times and accumulates the output of the code mixer 300 based on the set partial accumulation time.

Here, the partial accumulation time is 2 ^(a-1) n (a = 1, 2, ...), where n is the k th (k = 1) of the registers of the N-bit accumulator under the condition that synchronization of the received signal is normally obtained. , 2, ... N) Accumulation time at which the bit value becomes one.

Subsequently, the N-bit accumulator 301 outputs the accumulated total accumulated value for the total accumulated time to the comparator 302, and the comparator 302 compares the total accumulated value with the previously set correlation threshold. At this time, the comparator 302 finally determines that the synchronization of the received signal is acquired when the total accumulated value is greater than the correlation threshold, and generates a lock signal. When the accumulated value is less than the threshold, the received signal is synchronized. Is finally obtained as not obtained and does not generate a synchronization acquisition signal.

On the other hand, the determination unit 303 receives the k-th bits of the register of the N-bit accumulator 301 for each set partial accumulation time, and also the code generated from the code shift control signal generator 304 at the corresponding partial accumulation time. The shift receives a control signal.

Then, the determiner 303 performs an AND operation on the code shift control signal and the inverted value of the k-th bits of the register of the N-bit accumulator 301 and transmits the result to the PN code generator 305.

For example, if the k th bit is 0, the code shift control signal is input to the PN code generator 305 according to the result of the AND operation. If the k th bit is 1, the code shift control signal is PN according to the result of the AND operation. There is no input to the code generator 306.

The structure of such a crystal part is shown in FIG.

Referring to FIG. 4, the AND gates 400 to 403 receive the inverted values of the k-th values in the register of the n-bit accumulator 301, and receive the code shift control signal from the code shift control signal generator 304. The result of the AND and OR operation of the two signals is transmitted to the PN code generator 305.

In this way, the determination unit 303 determines in advance whether or not the received signal is synchronized for each set partial accumulation time 2 ^(a-1) n (a = 1, 2, ...), and accordingly, the PN code generator 305 is controlled. At this time, the determination unit 303 determines whether or not synchronization is obtained in the N-bit accumulator 301 for each of the set partial accumulation times 2 ^(a-1) n (a = 1, 2, ...). Therefore, even if synchronization is acquired during the previous partial accumulation time, it is determined whether the synchronization up to the last partial accumulation time thereafter is obtained.

Therefore, the PN code correlator according to the present invention does not determine whether or not the received signal is synchronized every predetermined total accumulation time M, and the set partial accumulation time 2 ^(a-1) n (a = 1, 2, ... It is possible to significantly reduce the synchronization acquisition time by determining in advance whether or not the received signals are synchronized in each case.

Meanwhile, the PN code generator 305 applies the PN code to the code shift control signal transmitted from the determination unit 303. Occurs by shifting by chip.

5 is a signal timing diagram illustrating a code shift control signal generated by a code shift control signal generator at every partial accumulation time according to the present invention.

Referring to Fig. 5, in the present invention, since the total accumulation time M is divided and a plurality of partial accumulation times 2 ^(a-1) n (a = 1, 2, ...) are set, the code shift The control signal generator generates a code shift control signal for each of the set partial accumulation times 2 ^(a-1) n (a = 1, 2, ...).

The operation of the PN code correlator according to the present invention will now be described in detail as an embodiment.

First, when the N-bit accumulator 301 is a 9-bit accumulator and the output of the code mixer 300 is partially accumulated 20 times under the condition that synchronization is to be obtained, the sixth bit value of the N-bit accumulator register is '000101000'. Assuming n is 20 and the kth bit is the 6th bit of the register.

Therefore, in the circuit of the determining unit shown in Fig. 3, the AND gate 400 is inputted with 0 in which the sixth bit value 1 of the register is inverted, and the shift control signal generated at the partial accumulation time of 20 is input.

Then, since the AND gate 400 outputs 0, the code shift control signal for shifting the PN code is not transmitted to the PN code generator 305. Therefore, the PN code generator 305 is generated by fixing the PN code position.

After that, the determination unit 303 continuously determines whether the received signal is synchronized for the next partial accumulation time.

On the other hand, in another case, when the phase of the PN code of the received signal and the generated PN code differ by more than one chip, it is difficult to obtain the synchronization of the received signal, that is, when the output of the code mixer 300 is accumulated 20 times. If the value of the sixth bit is '000001000' which is 0, the AND gate 400 is inputted with an inverted 1 of the sixth bit value 0 of the register, and a code shift control signal generated at a partial accumulation time of 20 is inputted. do.

Then, the AND gate 400 outputs the code shift control signal to the OR logic 404, so that a code shift control signal for eventually shifting the PN code to the PN code generator 305 is transmitted. Accordingly, the PN code generator 305 shifts the position of the PN code according to the transmitted code shift control signal.

In this situation, without accumulating the remaining partial accumulation time, that is, 2 × n = 40, 2 ² × n = 80, ... M, the PN code position of the PN code generator 305 is immediately determined. Chip shift.

The operation described so far is shown in Tables 1 to 2 below.

Accumulation Count 9-bit accumulator register value Bit number 20 000100000 32 6 40 001000000 64 7 80 010000000 128 8

Table 1 shows the k-th bit for each set accumulation time.

number Bit value OR logic result Status by Accumulation Count Code shift 8 7 6 80 40 20 One ㆍ ㆍ 0 One . . failure practice 2 ㆍ 0 One One . failure Obtain practice 3 0 One One One failure Obtain Obtain practice 4 One One One 0 Obtain Obtain Obtain Not carried

Table 2 shows all cases that can operate in the PN code correlator according to the present invention.

Referring to Table 2, first, in the first case, if the sixth bit value of the accumulation result register up to the partial cumulative time 20 is 0, the AND gate 400 of the decision unit 303 has 1 inverted and code shift control. The code shift control signal generated by the signal generator 104 is input, and accordingly, the AND gate 400 transmits the code shift control signal to the PN code generator 305 through the OR logic 404 to transfer the PN code to a predetermined shift. Let's do it.

At this time, the N-bit accumulator stops the correlation operation at the current PN code position without performing further accumulation process. The PN code generator 305 generates a PN code according to the code shift control signal. Let the chip shift.

In the second case, when the sixth bit value of the accumulation result register up to partial accumulation time 20 is 1, 0 and a code shift control signal in which 1 is inverted are input to the AND gate 400 of the determination unit 303, and accordingly, AND gate 400 outputs zero.

Subsequently, the N-bit accumulator 301 accumulates until the next partial accumulation time 40, and if the seventh bit value of the accumulation result register is 0, 0 is inverted in the AND gate 401 of the determination unit 303. And a code shift control signal is input, and the AND gate 401 transmits the code shift control signal to the PN code generator 305 through the OR logic 404 to shift the PN code.

At this time, the N-bit accumulator stops the correlation operation at the current PN code position without performing further accumulation process. The PN code generator 305 then generates a PN code. Let the chip shift.

In the third case, when the sixth bit value of the accumulation result register up to the partial accumulation time 20 is 1, 0 and a code shift control signal in which 1 is inverted are input to the AND gate 400 of the determination unit 303. AND gate 400 outputs zero.

Subsequently, the N-bit accumulator 301 accumulates until the partial accumulation time 40. If the seventh bit value of the accumulation result register is 1, the AND gate 401 of the determination unit 303 has 0 inverted and The code shift control signal is input, and the AND gate 401 outputs zero accordingly.

Subsequently, the N-bit accumulator 301 accumulates until the partial accumulation time 80, and if the eighth bit value of the accumulation result register is 0, the AND gate 402 of the determination unit 303 has 1 inverted and 0; The code shift control signal is input, and accordingly, the AND gate 402 transmits the code shift control signal to the PN code generator 305 through the OR logic 404 to transmit the PN code. Let the chip shift.

At this time, the N-bit accumulator stops the correlation operation at the current PN code position without performing further accumulation process. The PN code generator 305 then generates a PN code. Let the chip shift.

In the fourth case, when the sixth bit value of the accumulation result register up to the partial accumulation time 20 is 1, 0 and a code shift control signal in which 1 is inverted are input to the AND gate 400 of the determination unit 303. AND gate 400 outputs zero.

Subsequently, the N-bit accumulator 301 accumulates until the partial accumulation time 40. If the seventh bit value of the accumulation result register is 1, the AND gate 401 of the determination unit 303 has 0 inverted and The code shift control signal is input, and the AND gate 401 outputs zero accordingly.

Subsequently, the N-bit accumulator 301 accumulates until the partial accumulation time 80, and if the eighth bit value of the accumulation result register is 1, the AND gate 402 of the determination unit 303 has 0 and 1 inverted. The code shift control signal is input, and the AND gate 402 outputs zero accordingly.

At this time, since the N-bit accumulator 301 has accumulated up to the predetermined accumulation time M, the comparator 302 compares the accumulated value up to the predetermined accumulation time M with a correlation threshold already set. At this time, when the accumulated value is lower than the correlation threshold, the PN code of the PN code generator 305 is shifted a predetermined amount. When the accumulated value is larger than the correlation threshold, it is determined that synchronization is finally performed and the synchronization acquisition process is terminated.

6 is a flowchart illustrating a method of obtaining synchronization of a received signal of a PN code correlator according to the present invention.

Referring to FIG. 6, first, a proper informing whether the N-bit accumulator acquires synchronization of the received signal at the total accumulation time M, the partial accumulation time n, the total correlation threshold CT, and the partial accumulation time. The threshold k is initialized (S600).

Next, the variable Accum_Cnt = 0 and C = 1 are set (S601). Here Accum_Cnt represents the accumulation count of the N-bit accumulator.

The set Accum_Cnt value is increased (S601), and the N-bit accumulator accumulates the despread received signal (S603).

Then, it is checked whether the increased Accum_Cnt value is equal to the partial accumulation time (S604). When the Accum_Cnt value increased according to the check result is equal to the partial accumulation time, it is checked whether the N-kth bit of the N-bit accumulator register is 1 (S605), and when the difference is different, the above steps (S602 to S604) are repeated.

At this time, if the k-th bit of the N-bit accumulator register is 1 according to the check result of step S605, it is checked whether the increased Accum_Cnt value is equal to the total accumulation time M (S606). Deviate the code.

At this time, if the Accum_Cnt value increased according to the check result of step S606 is equal to the total accumulation time M, it is finally checked whether the final accumulated value of the N-bit accumulator is larger than the correlation threshold already set in the comparator (S607). ). However, if the increased Accum_Cnt value is less than the total accumulated time M, the above steps S602 to S606 are repeated.

At this time, if the final accumulated value of the N-bit accumulator is larger than the correlation threshold already set in the comparator, the comparator determines that the received signal is synchronized and generates a lock signal.

As described above, the PN code correlator according to the present invention can quickly determine whether to acquire a synchronization signal for a PN code of a received signal without having a predetermined accumulation time, thereby reducing the synchronization acquisition time for a received signal. There is.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the examples, but should be defined by the claims.

Claims (6)

A code generator for generating a pseudo noise sequence, A code mixer for multiplying the generated pseudo noise sequence by a received signal; An accumulator configured to divide the total accumulation time into a plurality of partial accumulation times and accumulate an output signal of the code mixer based on each of the set partial accumulation times; A control signal generator for generating a code shifting control signal for adjusting the pseudo noise sequence of the code generator at each set partial accumulation time; The accumulator receives the accumulated value during the partial accumulation time and the code shift control signal from the accumulator, and determines the possibility of synchronizing the received signal according to the corresponding partial accumulation time, and determines the generated code shift control signal according to the determination result. Decision unit provided to the code generator, And a comparator configured to compare the final accumulated value accumulated during the total accumulation time with a threshold value already set in the accumulator and finally determine whether the received signal is synchronized. The method of claim 1, wherein the determining unit, A plurality of AND gates that receive an inversion value of an accumulated value with respect to a desired partial accumulation time from the accumulator, and multiply receive a code shift control signal from the control signal generator; And OR logic for receiving the outputs of the AND gates, sum operations, and output the result to the code generator. Dividing and setting the total accumulation time into a plurality of partial accumulation times; Accumulator despreading and accumulating the input signal based on the set partial accumulation time and outputting each partial accumulation value for the corresponding partial accumulation time; Checking whether the output partial accumulation value is a value obtained by synchronizing a received signal; If the output partial accumulation value according to the check result is not a value obtained by synchronizing a received signal at a corresponding partial accumulation time, a code shift control signal for adjusting a pseudo noise sequence is provided to a code generator, and the output portion When the accumulated value is a value obtained by synchronizing the received signal at the corresponding partial accumulation time, the method of acquiring signal synchronization of a PN code correlator, characterized in that the code shift control signal for adjusting the pseudo noise sequence is not provided to the code generator. . The method of claim 3, wherein in the setting step, And the partial accumulation time is divided into a time period in which the k-th bit of the N-bit accumulator becomes 1 and set. The method of claim 3, wherein in the output step: And the output partial accumulating value is a k-th bit (k = 1 to N) of an N-bit accumulator. delete