KR100296960B1 - Method for forming polysilicon layer of semiconductor device - Google Patents
Method for forming polysilicon layer of semiconductor device Download PDFInfo
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- KR100296960B1 KR100296960B1 KR1019960022873A KR19960022873A KR100296960B1 KR 100296960 B1 KR100296960 B1 KR 100296960B1 KR 1019960022873 A KR1019960022873 A KR 1019960022873A KR 19960022873 A KR19960022873 A KR 19960022873A KR 100296960 B1 KR100296960 B1 KR 100296960B1
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- polysilicon film
- flow rate
- polysilicon layer
- impurity
- polysilicon
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 94
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 94
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims description 34
- 238000005137 deposition process Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 abstract description 12
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 239000002019 doping agent Substances 0.000 abstract 4
- 238000001465 metallisation Methods 0.000 abstract 1
- 230000008021 deposition Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제1도는 종래 기술에 따라 반도체 기판 상에 폴리실리콘막이 형성된 상태를 보여주는 단면도.FIG. 1 is a cross-sectional view showing a state in which a polysilicon film is formed on a semiconductor substrate according to a conventional technique; FIG.
제2도는 본 발명에 따른 반도체 소자의 폴리실리콘막 형성방법을 설명하기 위한 단면도.FIG. 2 is a sectional view for explaining a method of forming a polysilicon film of a semiconductor device according to the present invention; FIG.
* 도면의 주요부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
1 : 반도체 기판 2 : 폴리실리콘막1: semiconductor substrate 2: polysilicon film
2A : 제1폴리실리콘막 2B : 제2폴리실리콘막2A: first polysilicon film 2B: second polysilicon film
2C : 제3폴리실리콘막 3 : 확산된 불순물2C: Third polysilicon film 3: Diffused impurity
[발명의 기술분야][0001]
본 발명은 반도체 소자의 폴리실리콘막 형성방법에 관한 것으로, 보다 상세하게는, 폴리실리콘막의 증착시 또는 증착후, 상기 폴리실리콘막 내에 도핑된 불순물이 외부로 확산되는 것을 억제시킬 수 있는 반도체 소자의 폴리실리콘막 형성방법에 관한 것이다.The present invention relates to a method of forming a polysilicon film on a semiconductor device, and more particularly, to a method of forming a polysilicon film on a semiconductor device which can suppress the diffusion of doped impurities into the polysilicon film during deposition or after deposition of the polysilicon film. And a method of forming a polysilicon film.
[종래 기술]BACKGROUND ART [0002]
주지된 바와 같이, 폴리실리콘막은 고온에 잘 견디는 특성을 갖기 때문에, 알루미늄을 대신하여 배선용 재료, 예를들어, 반도체 소자에서의 워드 라인, 비트 라인 및 캐패시터 전극의 재료로서 사용되어 왔다.As is well known, polysilicon films have been used as materials for wiring materials, for example, word lines, bit lines and capacitor electrodes in semiconductor devices instead of aluminum, because they have high temperature resistant properties.
한편, 상기한 폴리실리콘막은 배선 재료로서 유용하지만, 그 자체 저항이 높기 때문에 순수한 폴리실리콘막으로는 배선 재료로서 이용하기 어렵다. 따라서, 이러한 문제점을 해결하기 위해, 종래에는 폴리실리콘막의 증착시, 또는, 증착후, 막 내에 소정의 불순물, 예를들어, 인(Phosphorus)을 도핑하여 배선 재료로 사용하고 있다.On the other hand, the polysilicon film described above is useful as a wiring material, but since it has high resistance, it is difficult to use a pure polysilicon film as a wiring material. Therefore, in order to solve such a problem, conventionally, a predetermined impurity such as phosphorus is doped into the film at the time of depositing a polysilicon film or after deposition, and is used as a wiring material.
[발명이 이루고자 하는 기술적 과제][Technical Problem]
그러나, 단순히 폴리실리콘막의 증착시, 또는, 증착후에 상기 폴리실리콘막 내에 불순물을 도핑시키는 종래의 방법에서는 상기 폴리실리콘막의 증착시, 또는, 후속의 열 공정이 진행되는 동안, 제1도에 도시된 바와 같이, 폴리실리콘막(2) 내에 도핑된 불순물이 외부로 확산됨으로써, 확산된 불순물(3)에 의해 기판(1) 농도가 변화되거나, 또는, 상기 폴리실리콘막(2) 상에 형성되는 또 다른 막에서의 불순물 농도가 변화되는 현상이 초래되며, 이 결과로, 소망하는 소자 특성을 얻지 못하게 되는 문제점이 있다.However, in the conventional method of simply doping the polysilicon film with impurities in the polysilicon film during or after the deposition of the polysilicon film, during the deposition of the polysilicon film or during the subsequent thermal process, The concentration of the substrate 1 is changed by the diffused impurity 3 or the concentration of the impurity which is formed on the polysilicon film 2 is increased by diffusing the doped impurity into the polysilicon film 2 The impurity concentration in the other film is changed. As a result, the desired device characteristics are not obtained.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 폴리실리콘막 내에 도핑된 불순물이 외부로 확산되는 것을 억제시킬 수 있는 반도체소자의 폴리실리콘막 형성방법을 제공하는데, 그 목적이 있다.SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of forming a polysilicon film of a semiconductor device capable of suppressing the diffusion of doped impurities in the polysilicon film to the outside .
[발명의 구성 및 작용][Structure and operation of the invention]
상기와 같은 목적을 달성하기 위하여, 본 발명은 폴리실리콘막을 3단계 증착 공정을 통해 적층 구조로 형성하며, 특히, 그 하부 및 상부에 배치되는 제1 및 제3폴리실리콘막은 통상적으로 적용되는 불순물의 도핑 농도 보다 낮은 도핑 농도를 갖도록 형성하고, 그리고, 상기 제1 제1폴리실리콘막과 제3폴리실리콘막 사이에 배치되는 제2폴리실리콘막은 전도체로서 동작 가능한 정도의 충분한 도핑 농도를 갖도록 형성한다.In order to accomplish the above object, the present invention provides a method of forming a polysilicon film in a laminated structure through a three-step deposition process, in particular, a first and a third polysilicon film disposed under and over the polysilicon film, And the second polysilicon film disposed between the first first polysilicon film and the third polysilicon film is formed to have a sufficient doping concentration to such an extent as to be operable as a conductor.
본 발명에 따르면, 3단계 증착 공정을 통해 적층 구조로 폴리실리콘막을 형성하되, 하부 및 상부에 배치되는 제1 및 제3폴리실리콘막의 도핑 농도를 낮춤으로써, 상기 제1 및 제3폴리실리콘막에 도핑된 불순물이 외부로 확산되는 양을 줄이거나, 또는, 외부로 확산되는 것을 억제시킬 수 있으며, 이에 따라, 폴리실리콘막에 도핑된 불순물의 외부 확산에 기인하는 소자 특성의 저하를 방지할 수 있다.According to the present invention, by forming a polysilicon film in a laminated structure through a three-step deposition process, by lowering the doping concentrations of the first and third polysilicon films disposed on the lower and upper sides, It is possible to reduce the diffusion amount of the doped impurity to the outside or prevent the diffusion to the outside of the polysilicon film so that the deterioration of the device characteristics due to the external diffusion of the doped impurity in the polysilicon film can be prevented .
[실시예][Example]
이하, 본 발명의 바람직한 실시예를 첨부한 도면에 의거하여 보다 자세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.
제2도는 본 발명에 따른 반도체 소자의 폴리실리콘막 형성방법을 설명하기 위한 단면도이다.FIG. 2 is a cross-sectional view illustrating a method of forming a polysilicon film of a semiconductor device according to the present invention.
우선, 본 발명의 실시예에서의 반도체 기판(1)은 폴리실리콘막(2A, 2B, 2C)이 형성되기 이전 공정까지 형성된 구조물을 포함하는 것으로서. 예를들어, 상기 폴리실리콘막(2A, 2B, 2C)이 워드라인으로 사용되는 경우의 상기 반도체 기판(1)은, 도시되지는 않았으나, 소자분리막 및 게이트절연막이 형성된 상태를 포함하는 것이고, 상기 폴리실리콘막(2A, 2B, 2C)이 비트라인으로 사용되는 경우의 상기 반도체 기판(1)은, 도시되지는 않았으나, 소자분리막, 트랜지스터 및 상기 트랜지스터를 덮는 층간절연막이 형성되고, 상기 층간절연막에는 상기 트랜지스터의 드레인 전극을 노출시키는 콘택흘이 형성된 상태를 포함하는 것이다.First, the semiconductor substrate 1 in the embodiment of the present invention includes the structure formed up to the step before the formation of the polysilicon films 2A, 2B, 2C. For example, the semiconductor substrate 1 in the case where the polysilicon films 2A, 2B and 2C are used as word lines includes a state in which a device isolation film and a gate insulating film are formed, Although not shown, the semiconductor substrate 1 in the case where the polysilicon films 2A, 2B and 2C are used as a bit line is formed with an element isolation film, a transistor and an interlayer insulating film covering the transistor, And a contact hole exposing the drain electrode of the transistor.
계속해서, 도시된 바와 같이, 상기 반도체 기판(1) 상에 배선용 재료로서 폴리실리콘막을 형성하되, 상기 폴리실리콘막을 다단계, 바람직하게는, 3단계 증착 공정을 통해 적층구조로 형성한다. 이때, 적층 구조로 형성되는 제1, 제2 및 제3폴리실리콘막(2A. 23, 2C)은 하기와 같은 조건으로 각각 형성한다.Next, as shown in the figure, a polysilicon film is formed as a wiring material on the semiconductor substrate 1, and the polysilicon film is formed in a multilayer structure through a multistage, preferably three-step deposition process. At this time, the first, second, and third polysilicon films 2A, 23, and 2C formed in a laminated structure are formed under the following conditions, respectively.
먼저, 제1폴리실리콘막(2A)은 반응챔버 내에 유입되는 소오스 가스인 SiH4의 유량은 280 내지 320 SCCM 정도, 그리고, 불순물인 PH3의 유량은 통상의 폴리실리콘막 증착 공정에서 적용되는 유량 보다 상대적으로 매우 낮은 28 내지 30 SCCM 정도로 하는 제1단계 증착 공정을 통해 형성하며, 이때. 상기 제1단계 증착공정은 7 내지 9초 동안 수행한다.First, the flow rate of SiH 4 , which is a source gas flowing into the reaction chamber, of the first polysilicon film 2A is about 280 to 320 SCCM, and the flow rate of the impurity PH 3 is a flow rate applied in a conventional polysilicon film deposition process To about 28 to about 30 SCCM, which is relatively low. The first stage deposition process is performed for 7 to 9 seconds.
다음으로, 상기 제1폴리실리콘막(2A) 상에 형성되는 제2폴리실리콘막(2B)은 소오스 가스인 BiH4의 유량은 제1단계 증착 공정과 동일하지만, 불순물인 PH3의 유량은 상기 제1폴리실리콘막(2A) 및 이후에 형성하는 제3폴리실리콘막을 포함한 상기 제2폴리실리콘막(2B)이 전도체로서 동작 가능한 정도의 충분한 도핑 농도를 갖도록, 150 내지 170 SCCM 정도로 하는 제2단계 증착 공정을 통해 형성하며, 이때, 상기 제2단계 증착 공정은 32 내지 34초 동안 수행한다.Next, the first poly second polysilicon film (2B) is a flow rate of the source gas of a flow rate of BiH 4 is the same as the first step of the deposition process, but the impurity PH 3 formed on the silicon film (2A) is the The second polysilicon film 2B including the first polysilicon film 2A and the third polysilicon film to be formed thereafter has a sufficient doping concentration to the extent that the second polysilicon film 2B can operate as a conductor, Deposition process, wherein the second-stage deposition process is performed for 32 to 34 seconds.
이어서, 상기 제2폴리실리콘막(2B) 상에 형성되는 제3폴리실리콘막(2C)은 상기 제1폴리실리콘막(2A)을 형성하기 위한 제1단계 증착 공정과 동일하게 SiH4의 유량은 280 내지 320 SCCM 정도. 그리고, PH3의 유량은 28 내지 30 SCCM 정도로 하는 제3단계 증착 공정을 통해 형성하며, 이때, 제3단계 증착 공정은 7 내지 9초 동안 수행한다.The third polysilicon film 2C formed on the second polysilicon film 2B has a flow rate of SiH 4 similar to that of the first polysilicon film 2A to form the first polysilicon film 2A, About 280 to 320 SCCM. The flow rate of PH 3 is formed through a third step deposition process at about 28 to 30 SCCM, and the third step deposition process is performed for 7 to 9 seconds.
한편, 전술하지는 않았으나, 상기 제1, 제2 및 제3단계 증착 공정은 모두 650~670℃의 온도, 75∼85 Torr의 압력, 6.5 내지 7 정도의 메인(main) H2및 2.5 내지 3 정도의 슬릿(Slit) H2의 조건하에서 수행한다.Although not described above, the first, second and third stage deposition processes are all performed at a temperature of 650 to 670 ° C, a pressure of 75 to 85 Torr, a main H 2 of about 6.5 to 7 and a pressure of about 2.5 to 3 Lt; 2 > under a condition of a slit H2.
상기에서, 제1 및 제3폴리실리콘막(2A, 2C)을 형성하기 위한 제1 및 제3단계 증착 공정시에 불순물인 PH3의 유량을 통상적으로 적용되는 유량 보다 낮은 28 내지 30 SCCM 정도로 하는 것은 상기 제1 및 제3폴리실리콘막(2A, 2C) 내에 도핑되는 불순물, 즉, 인(P)의 도핑 농도를 낮추어, 상기 인(P)이 제1 및 제3폴리실리콘막(2A, 2C)의 증착 공정시, 또는, 후속의 열 공정 동안에 반도체 기판(1) 및 상기 제3폴리실리콘막(2C) 상에 형성되는 또 다른 막(도시안됨)으로 확산되는 불순물의 양을 줄이거나, 또는 외부로 확산되는 것을 억제시키는 것에 의해, 상기 반도체기판(1) 및 또 다른 막에서의 불순물 농도가 변화되는 것을 방지하기 위함이다.In the above, the flow rate of the impurity PH 3 in the first and third step deposition processes for forming the first and third polysilicon films 2 A and 2 C is set to about 28 to 30 SCCM lower than a conventionally applied flow rate (P) is doped in the first and third polysilicon films 2A and 2C so that the phosphorus P is doped into the first and third polysilicon films 2A and 2C , Or to reduce the amount of impurities diffused into the semiconductor substrate 1 and another film (not shown) formed on the third polysilicon film 2C during the deposition process of the third polysilicon film 2C or during the subsequent thermal process, So as to prevent the impurity concentration in the semiconductor substrate 1 and another film from being changed.
이에 반해, 제2단계 증착 공정에서 PH3의 유량을 제1 및 제3단계 증착 공정에서 보다 더 크게 하는 것은 제1, 제2 및 제3폴리실리콘막(2A, 2B, 2C)으로 이루어지는 적층 구조의 폴리실리콘막이 전도체로서 동작 가능하도록 함과 동시에, 상기 제2폴리실리콘막(2B)에 과도하게 도핑된 불순물이 그 증착시, 또는, 후속의 열 공정동안에 상대적으로 낮은 도핑 농도를 갖는 상기 제1 및 제3폴리실리콘막(2A, 2C)으로 확산되도록 함으로써, 상기 제1 및 제3폴리실리콘막(2A, 2C)에서의 부족한 불순물 농도가 보상되도록 하고, 그리고, 상기 제1, 제2 및 제3폴리실리콘막(2A, 2B, 2C)으로 이루어진 전체 폴리실리콘막의 자체 저항이 감소되도록 하기 위함이다.In contrast, in the second-stage deposition process, the flow rate of the PH 3 is made larger than that in the first and third-stage deposition processes because the lamination structure of the first, second and third polysilicon films 2A, 2B, 2C The polysilicon film of the first polysilicon film 2B can be operated as a conductor while the impurity which is heavily doped in the second polysilicon film 2B is doped at the time of its deposition or during the subsequent thermal process, And the third polysilicon film (2A, 2C) to compensate for the insufficient impurity concentration in the first and third polysilicon films (2A, 2C), and the first, second, and third polysilicon films 3 self-resistance of the entire polysilicon film composed of the polysilicon films 2A, 2B and 2C is reduced.
상기한 바와 같이, 3단계 증착 공정을 통해 폴리실리콘막을 형성하되, 각 단계에서의 불순물의 도핑 농도를 상이하게 하면, 기판(1)과 접촉되어진 제1폴리실리콘막(2A)과 외부로 노출된 제3폴리실리콘막(2C)은 불순물의 도핑 농도가 낮은 것에 기인하여, 외부로의 불순물의 확산을 감소시킬 수 있고, 이에 따라, 불순물의 외부확산에 기인된 소자 특성의 저하를 방지할 수 있게 된다. 또한, 제2폴리실리콘막(2B)은 제1 및 제3폴리실리콘막(2A, 2C)에 비해 상대적으로 높은 불순물 농도를 갖기 때문에 전체적인 폴리실리콘막의 불순물 도핑 농도는 균일하게 유지된다.As described above, when the polysilicon film is formed through the three-step deposition process and the doping concentrations of the impurities in the respective steps are different, the first polysilicon film 2A, which is in contact with the substrate 1, The third polysilicon film 2C can reduce the diffusion of the impurities to the outside due to the low doping concentration of the impurities, thereby preventing deterioration of the device characteristics due to the external diffusion of the impurities do. Since the second polysilicon film 2B has a relatively high impurity concentration as compared with the first and third polysilicon films 2A and 2C, the impurity doping concentration of the entire polysilicon film is uniformly maintained.
[발명의 효과][Effects of the Invention]
이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 폴리실리콘막 형성방법은 폴리실리콘막을 3단계 증착 공정을 통해 적층 구조로 형성하되, 기판과 접촉되는 제1폴리실리콘막 및 상부에 위치되는 제3폴리실리콘막은 그들의 증착시에 불순물의 유량을 낮게 함으로써, 그 내부에 도핑된 불순물이 외부로 확산되는 것을 억제시키거나, 또는, 그 양을 감소시킬 수 있으며, 이에 따라. 상기 폴리실리콘막에 도핑된 불순물의 외부 확산에 기인하는 소자 특성의 저하를 방지할 수 있다.As described above, the method for forming a polysilicon film of a semiconductor device according to the present invention comprises forming a polysilicon film in a laminated structure through a three-step deposition process, wherein a first polysilicon film is in contact with the substrate, The polysilicon film can reduce the amount of doped impurities diffused therein or reduce the amount thereof by lowering the flow rate of the impurities at the time of their deposition. It is possible to prevent degradation of device characteristics due to external diffusion of doped impurities into the polysilicon film.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.While specific embodiments of the present invention have been described and illustrated herein, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Therefore, the following claims are to be understood as including all modifications and variations as fall within the true spirit and scope of the present invention.
Claims (5)
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