JPH04159724A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the increase in leakage current by providing a semiconductor device structure, which includes a silicon substrate, a heavily phosphorus- doped layer containing a specified maximum phosphorus content, a first silicon layer, and a second silicon layer for device formation. CONSTITUTION:A semiconductor device has a structure including a silicon substrate 10, a heavily phosphorus-doped layer 11, a first silicon layer 12, and a second silicon layer 13. Specifically, the layer 11, having a phosphorus content of more than 1X10<19>cm<-3>, is located near the second silicon layer 13 for device formation. Therefore, the layer 11 includes a heavy-metal trap capable of efficiently capturing heavy metal particles that are contained in the second silicon layer 13. This prevents the increase in leakage current due to heavy metal particles.

Description

[Detailed description of the invention] [Table of contents] - Overview - Field of industrial application - Prior art (Fig. 8, Fig. 9) - Problems to be solved by the invention - Means and operation for solving the problems - Examples ■Example of the first and second inventions (Fig. 1) ■Example of the third invention (Figs. 2, 6, and 7) ■Example of the fourth invention (Fig. 3) (Fig.) ■Example of the fifth invention (Fig. 4) ■Example of the sixth invention (Fig. 5) ・Effects of the invention [Summary] Regarding the semiconductor device, in more detail, the elements of the Si substrate 1- Regarding wafers that have a phosphorus-rich layer that traps heavy metal particles near the Si layer as a formation layer, heavy metal particles can be efficiently removed from the element formation layer, and heavy metal particle traps and crystal defects caused by the phosphorus-rich layer can be removed. The purpose of the present invention is to provide a semiconductor device that can prevent an increase in leakage current of an element formed in an element formation layer due to
31 substrate on which a high phosphorus concentration layer containing phosphorus (P) particles of rr3 or more was formed on one surface, and a substrate with a concentration l×10110l7″−1×】019cm formed on the high phosphorus concentration layer.
A first Si layer containing impurity particles of one conductivity type of "J" and a second Si layer of one conductivity type formed on the first (7) Si layer.
The manufacturing method includes a layer having a maximum concentration of I
Concentration where a high phosphorus concentration layer containing phosphorus (P) particles north of the area is formed on one surface] XIO"Cm-"~I Xl019
A first Si substrate containing conductivity type impurity particles of cIn-' and a second Si substrate are bonded together such that one surface of the first Si substrate and the second Si substrate face each other. a step of removing the first Si substrate so that the high phosphorus concentration layer and the first Si substrate (first Si layer) other than the high phosphorus concentration layer remain; The method includes a step of forming a second Si layer of one conductivity type on the Si substrate.

[Industrial application field]

The present invention relates to a semiconductor device, and more specifically, the present invention relates to a semiconductor device, and more specifically, the present invention relates to a semiconductor device.
The present invention relates to a wafer having a high phosphorus concentration layer that captures heavy metal particles in the vicinity of 3[ as an element forming layer on the base.

[Conventional technology]

Conventionally, various methods have been used to remove heavy metal particles that soften the reverse direction characteristics of the device from the device forming layer. That is, as shown in FIG. 8(a), CZ containing a large amount of oxygen (
Czochralski) C
This is a so-called intrinsic gettering method in which oxygen precipitates are formed within the Z wafer l and heavy metal particles are captured in traps created by dirt.

■As shown in Figure 8(a), laser irradiation, polysilicon introduction, Zant blasting or high concentration (l x 1, Q19c
A so-called extrinsic gettering method in which a capture layer 6 in which traps of heavy metal particles are collected is formed on the back surface of the wafer 3 by introducing phosphorus particles (of m-3 or more), and the heavy metal particles are captured in the capture layer 6.

[Problem to be solved by the invention]

However, when using the intrinsic gettering method, firstly, there are traps caused by oxygen precipitates near the element formation layer on the surface of the CZ wafer 1, so although the effect of trapping heavy metal particles is large, the element formation There is a problem in that leakage current of elements formed in the layer increases. This is thought to be caused by carriers released from the trap.

Second, since this method is limited to CZ wafers, there is a problem that it is not versatile.

In addition, in the case of the extrin sink gettering method, a trapping layer 6 of heavy metal particle tramps generated by introducing phosphorus particles at a high concentration (1×10199 cm−3 or more), etc.
exists on the back surface of the wafer 3, which is aligned with the element formation layer 5 on the front surface, so the leakage current of the elements formed in the element formation layer 5 is small, but there is a problem that the effect of trapping heavy metal particles is small. Therefore, as shown in FIGS. 9(a) to (C),
It is conceivable to form an epitaxial layer 9 as an element formation layer on a high phosphorus concentration layer 8 formed by introducing high concentration (1×10 19 cm −3 or more) phosphorus particles into an n-type Si substrate 7. , there are the following problems.

■As in the case of the intrinsic gettering method, the high phosphorus concentration layer 8a exists directly under the element formation layer 9, and the leakage current of the element due to the release of carriers generated by the high phosphorus concentration layer 8a is reduced. An increase will be inevitable.

(2) Moreover, a large number of crystal defects occur in the phosphorus-rich layer 8, and the epitaxial layer 9 formed thereon also inherits these crystal defects, resulting in poor crystallinity.

The present invention has been made in view of such conventional problems, and it is possible to efficiently remove heavy metal particles from the element formation layer, and to prevent element formation caused by traps of heavy metal particles and crystal defects caused by the high concentration layer of phosphorus. It is an object of the present invention to provide a semiconductor device that can prevent an increase in leakage current of elements formed in a layer.

[Means to solve the problem]

First, the maximum concentration of the L problem is I Xl019c m
- A Si substrate with a high phosphorus concentration layer formed on one surface containing phosphorus (P) particles of 3 or more, and a phosphorus concentration layer with a concentration of 1 x 1017 cm-3 to 1 x 10110 l9 formed on the phosphorus concentration layer.
' is achieved by a semiconductor device having a first Si layer containing impurity particles of one conductivity type and a second Si layer of one conductivity type formed on the first Si layer; 1st
The Si layer/second Si layer is the n-type Si layer/n
This is achieved by the semiconductor device according to claim 1, characterized in that the semiconductor device is a type Si layer or a P type S1 layer/p type Si layer; ) A high-concentration phosphorus layer containing particles is formed on one surface, with a concentration of 1 xto17c m-'~I
a first Si substrate containing m-3 one conductivity type impurity particles;
bonding a second Si substrate such that one surface of the first Si substrate and the second Si substrate face each other; S
a step of removing the first Si substrate so that the i-substrate (first Si layer) remains; and a step of forming a second Si layer of one conductivity type on the remaining first Si substrate. Fourthly, phosphorus (phosphorus) having a maximum concentration of 1 x 10"9 cm-3 or more is achieved.
P) A third layer with a high phosphorus concentration layer containing particles formed on one surface.
and a fourth Si substrate such that one surface of the third Si substrate and the fourth Si substrate face each other, and at least the high phosphorus concentration layer remains. step of removing the third Si substrate, and sequentially performing concentration on the remaining third Si substrate] Xl017c
Achieved by a semiconductor device manufacturing method comprising a step of forming a first Si layer containing impurity particles of - conductivity type of m-' to I Fifth, the maximum concentration is 1 x 1017 cm-3 to 1 x 101
A fifth Si substrate of one conductivity type in which a high concentration layer containing impurity particles of one conductivity type of ``cm-3'' is formed on one surface, and phosphorus (P) particles having a maximum concentration of IXiO''c rrr3 or more. a step of laminating a sixth Si substrate of one conductivity type on one surface of which a high concentration layer of phosphorus containing a high concentration layer of phosphorus is formed so that one surface of the fifth Si substrate and the sixth Si substrate face each other;
removing a fifth Si substrate so that the high concentration layer (first Si layer) and a fifth Si substrate (second Si layer) other than the high concentration layer remain. Sixth, the maximum concentration achieved by the manufacturing method is
c m-J~l (P) An eighth Si substrate having a high concentration layer of phosphorus containing particles formed on one surface is attached so that one surface of the seventh Si substrate and one surface of the eighth Si substrate face each other. a step of removing the seventh Si substrate so that at least the high concentration layer (first Si layer) remains;
A second Si of one conductivity type is deposited on the remaining seventh Si substrate.
This is achieved by a method for manufacturing a semiconductor device characterized by comprising a step of forming a layer.

[Function] The semiconductor device of the present invention has a structure of Si substrate/high phosphorus concentration layer/first Si layer/second Si layer. That is, the maximum concentration is 1×1019c+ near the second Si layer.
Since there is a phosphorus-rich layer containing phosphorus (P) particles with an ffi of 3 or more, heavy metal particles contained in the second Si layer can be efficiently captured.

Moreover, a concentration I
Since it has the first Si layer containing a high concentration of one-conductivity type impurity particles of IO"cm-"~1×1019cm"3, carrier holes or electrons released from within the phosphorus-rich layer are is the high concentration IXIO” cm − of the first Si layer
3~I Xl019c m-3 majority carrier compensation. As a result, the emitted carriers do not affect the second Si layer, so when an element is formed in the second Si layer, an increase in leakage current of the element can be prevented.

Furthermore, according to the method of manufacturing a semiconductor device of the present invention, the semiconductor device having the structure described in "2" is manufactured by bonding wafers together, so compared to the conventional case where the semiconductor device is formed on a Si substrate by epitaxial growth etc. Therefore, the first and second Si layers have good crystallinity.

In addition, it is relatively easy to create a wafer having a complex structure of the above-mentioned Si-based substrate/high-concentration phosphorus layer-first conductive type high-concentration Sr layer/-second conductive type low-concentration Si layer. can do.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

(1) Embodiments of the first and second inventions FIG. 1 is a sectional view illustrating a wafer according to an embodiment of the first invention.

In FIG. 1, 10 is an n-type Si substrate, and 11 is a silicon substrate formed on the Si substrate 10 with a maximum concentration of 1×10110l9″.
The phosphorus preconcentration J〆, 12 with a thickness of about 3 μm containing the above phosphorus (P) particles is formed on the phosphorus high concentration layer 11 with a concentration of 1
x1017 cm-3 to 1 x 1019 cm'' containing phosphorus or arsenic particles and a film thickness of about 10 μm.
The layer (n'' type Si layer) 13 is formed on the first Si layer 12 and contains phosphorus or arsenic particles with a concentration of about 1×101101 S'', which is lower than the impurity concentration of the first Si layer 12. , a second Si layer (n-type Si layer) with a film thickness of approximately 5 μm, and elements such as transistors are normally formed here.

As described above, according to the wafer of the first embodiment of the invention,
Since the phosphorus high concentration layer 11 containing phosphorus (P) particles with a maximum concentration of 1×10 19 cm −3 or more is provided near the second Si layer 13 as the element forming layer, the phosphorus high concentration layer II contains Heavy metal particles are trapped, and the heavy metal particles contained in the second Si layer 13 can be captured with efficiency, b<. Thereby, an increase in leakage current due to heavy metal particles of the device formed in the second Si layer 13 can be prevented.

Further, between the second Si layer 13 and the phosphorus high concentration layer 11, a layer of lX1017cm1~ with a higher concentration than the second Si layer 13 is formed.
n containing phosphorus or arsenic particles of lXl019C-1)
Since the first Si layer 12 has a type 1, the holes of minority carriers emitted from the traps generated in the high concentration layer 11 are transferred to the high concentration majority carriers of the first Si layer 12. is compensated by the electrons of This makes it possible to reduce the number of minority carriers released, so the second Si layer 1
In the case where the element is formed in No. 3, an increase in leakage current of the pn junction of the element can be prevented.

In addition, in the embodiment, first Si layer 12/second Si layer 1
3, an n-type Si layer/n-type Si layer is formed, but a P-type Si layer/p-type Si layer may be formed as in the second invention. In this case, the Si crystal is 10° If, 12.
13 is n type.

■Embodiment of the third invention FIGS. 2(a) to 2(e) are cross-sectional views illustrating a method of manufacturing a wafer according to an embodiment of the third invention.

First, as shown in Figure (a), the concentration is 1×1017c.
Phosphorus (P) particles with a maximum concentration of 1X1O" cm-3 or more are heated or ionized onto one surface of the n-type first Si substrate 14 containing phosphorus or arsenic particles of m-" to I Xl0I9c m-3. The phosphorus is introduced by implantation to form a high phosphorus concentration layer 16 with a depth of approximately 3 μm.

Subsequently, the well-known bonding method was used to heat the film to a temperature of 1000
°C for 2 hours and 60 minutes, the first Si substrate 14 and another n-type second Si substrate 5 shown in FIG.
The phosphorus high concentration layer 16 of the Si substrate 14 and the second Si substrate (
(Si substrate) 15 are attached so that they face each other ((C) in the same figure).

Next, as shown in FIG. 2D, the back surface of the first Si substrate 14 is polished using an amine-based aqueous solution containing colloidal silica, and a layer with a thickness of about 10 μm is formed separately from the high phosphorus concentration layer 16. One Si substrate (first Si layer) 14a remains.

Next, a first Si substrate 14a is deposited on the remaining first Si substrate 14a.
Impurity concentration lower than that of the substrate 14a, 1×1017 cm
A 5 μm thick Si layer (
When the second Si layer 17 is formed by epitaxial growth, the wafer is completed (FIG. 3(e)).

As described above, according to the wafer manufacturing method of the embodiment of the third invention, the wafer having the structure of the embodiment of the first invention is bonded to two first and second Si substrates 14 and 15. Compared to the conventional case where it is formed on a Si substrate by epitaxial growth, S
The crystallinity of the i-layer 17 can be improved. Also, the first
Si substrate 10/high phosphorus concentration layer 11/- of the embodiment of the invention
A wafer having a complicated structure of a first Si layer 12 of a conductive type with a high concentration and a second Si layer 13 of a conductive type with a low concentration can be produced relatively easily.

■Embodiment of the fourth invention FIGS. 3(a) to 3(e) are cross-sectional views illustrating a method of manufacturing a wafer according to an embodiment of the fourth invention.

First, as shown in Figure (a), phosphorus (P) particles with a maximum concentration of 1 x to I9c m-3 or more are introduced onto one surface of the n-type third Si substrate 18 by thermal diffusion or ion implantation. Then, a high phosphorus concentration layer 20 having a depth of about 4 μm is formed.

Subsequently, the well-known bonding method was used to heat the film to a temperature of 1000
Under conditions of 1 hour and 60 minutes at °C, the third Si substrate 18 and another n-type fourth Si substrate (Si substrate) 1 shown in FIG.
9 and the phosphorus high concentration layer 20 of the third Si substrate 18 and the second
The two Si substrates 19 are bonded together so that they face each other (FIG. 3(C)).

Next, as shown in FIG. 4D, the third Si substrate 18 is polished from the back side using an amine aqueous solution containing colloidal silica, leaving a high phosphorus concentration layer 20a with a thickness of about 3 μm.

Next, on the remaining phosphorus high concentration layer 2Oa, the concentration becomes IX
A first Si layer 21 of 10 .mu.m in film thickness and containing phosphorus or arsenic particles of IO"cm" to I.sub.X1019cm-" is formed by continuous growth. Subsequently, on the first Si layer 21, a second layer 34 having a thickness of about 5 μm and containing phosphorus or arsenic particles at a lower concentration than the impurity concentration of the first Si layer 21 is formed. When the layer 22 is formed by epitaxial growth, the wafer is completed (FIG. 4(e)).

Next, Fig. 6(a) shows the results of investigating the trapping effect of heavy metal particles on a wafer prepared by such a method and the distribution of traps (considered to be crystal dislocations) occurring in the high phosphorus concentration layer 20a. ).

This will be explained with reference to (b) and FIGS. 7(a) and (b).

A sample wafer was prepared as follows. That is, for the initial wafer used in the experiment, the first Si layer 21 had a thickness of 10 μm, and the second 34 layers 22 had a thickness of 1! v-50μm
, was prepared in the same manner as in the above embodiment except that the phosphorus concentration of the phosphorus high concentration layer 20 was set to 2×10 cm”. Then, such a wafer was immersed in a solution containing 10 pma of Cu. A CII film was formed on the Si layer 22 of No. 2, and then this wafer was heat-treated at a temperature of 1150°C for 230 minutes in a nitrogen atmosphere.For comparison, CZ
The wafers were also subjected to the above treatment and investigated at the same time.

That is, first, the surface of the wafer is etched with a selective etchant (Secc).
.

After etching using an etchant), the surface was observed. The feature of this investigation is that if there is Cu precipitation, a shallow bit will be generated due to this and this part will be selectively etched, and the wafer having the structure of the present invention is shown in Fig. 6(a). As shown, the selectively etched area is small. This indicates that Cu is not deposited on the surface but exists inside the wafer.

Second, the concentration of Cu in the depth direction of the wafer was measured by well-known STMS analysis. The results are shown in Figure 7 (a
), (b), a high phosphorus concentration layer 20 in which traps (crystal dislocations) have occurred due to the introduction of high concentration phosphorus.
It can be seen that most of the Cu is captured in a.

As described above, according to the wafer manufacturing method of the embodiment of the fourth invention, the wafer of the embodiment of the first invention is produced by bonding two Si substrates 18 and 19. In the embodiment of the invention, S tJx 10/high concentration phosphorus layer 11/- conductivity type high concentration first Si layer 12/- conductivity type low concentration second Si layer 13 has a complicated structure. It is possible to relatively easily create a wafer having the following properties.

In the embodiment shown in FIG. 3, phosphorus is introduced into the third Si substrate 18 to form the phosphorus high concentration layer 20.
The entire i-substrate 1B may contain phosphorus particles of L Xl019c m-3 or more.

■Embodiment of the fifth invention FIGS. 4(a) to 4(d) are cross-sectional views illustrating a method of manufacturing a wafer according to an embodiment of the fifth invention.

, the maximum concentration is I
10" deep with phosphorus or arsenic particles of IO" cm
The high concentration layer (first Si layer) 25 with a concentration of about I
It is formed on one surface of the n-type fifth Si substrate 23 of XIO"cm"3 by thermal diffusion method or ion implantation method (see figure
In addition to a)), a phosphorus-rich layer 26 with a depth of approximately 3 μm containing phosphorus CP) particles having a maximum concentration of LXIO"cm-3 or more
is formed on one surface of the sixth Si substrate (Si substrate) 24 by thermal diffusion or ion implantation (FIG. 2(b)).

Next, the temperature is 1000° by the well-known laminating method.
Under the condition of C1 time 60 minutes, the fifth Si substrate 23 and the sixth Si substrate 24 are
and the high phosphorus concentration layer 26 of the sixth Sr substrate 24 are bonded together so as to face each other (FIG. 3(C)).

Next, an amine-based aqueous solution containing colloidal silica is used to remove the high concentration layer 25 and the fifth Si substrate (second Si layer) 23a having a thickness of approximately 5 μm except for the high concentration layer 25. When the Si substrate 23 of No. 5 is polished, a wafer is completed (FIG. 5(d)).

As described above, according to the wafer manufacturing method of the embodiment of the fifth invention, the wafer having the structure of the embodiment of the first invention is produced by bonding two Si substrates 23 and 24. The crystallinity of the remaining fifth Si substrate (second Si layer) 23a as an element formation layer is better than that in the conventional case where it is formed on a substrate by epitaxial growth or the like. Moreover, the Si substrate 10 having the structure of the embodiment of the first invention
A wafer having a complicated structure of /high concentration phosphorus layer 11/-first 34 layers of high concentration of conductivity type 12/-second layer of low concentration 5iNll of conductivity type can be produced relatively easily.

■Embodiment of the sixth invention FIGS. 5(a) to 5(e) are cross-sectional views illustrating a method of manufacturing a wafer according to an embodiment of the sixth invention.

First, on one surface of the n-type seventh 31 substrate 27, the maximum concentration is I
High concentration layer 2 with a depth of approximately 10 μm containing phosphorus or arsenic particles of
9 is formed by thermal diffusion method or ion implantation method (see the same figure (
With a)), the maximum concentration is I Xl019c rrr
A high phosphorus concentration layer 30 containing 3 or more phosphorus (P) particles and having a depth of approximately 3 μm is formed on one surface of the n-type eighth Si substrate 28 by thermal diffusion or ion implantation (FIG. 3(b)). ).

Then, by a well-known lamination method, the temperature is 1000
The seventh Si substrate 27 and the eighth Si substrate were
and the high concentration layer 2 of the seventh Si substrate 27.
9 and the high phosphorus concentration layer 30 of the eighth Si substrate 28 are bonded together so as to face each other (FIG. 3(C)).

Next, the seventh Si substrate 27 is polished using an amine-based aqueous solution containing colloidal silica to form a high concentration layer (first Si substrate 27).
(d) of the same figure).

After that, about 1×1011 is added to the remaining high concentration layer 29al.
N-type film containing 0l5'' phosphorus or arsenic particles, approximately 5μ thick
When a Si layer (second Si layer) 31 of m thickness is formed by epitaxial growth, a wafer is completed (FIG. 2(e)).

As described above, according to the wafer manufacturing method of the embodiment of the sixth invention, since the high concentration layer 29 is created by bonding two Si substrates 27 and 28, the crystallinity of the high concentration layer 29 is is relatively good. Since the Si layer 31 is further formed on this by epitaxial growth, the Si layer 31 is formed as an element forming layer, compared to the conventional case where the Si layer is directly formed on the high phosphorus concentration layer by epitaxial growth.
The crystallinity of L-31 is good. Further, the Si substrate 10/phosphorus high flow layer 11/-first 34 layers of high concentration of conductivity type 12/-second S of low concentration of conductivity type having the structure of the embodiment of the first invention
A wafer having a complicated structure such as the i-layer 11 can also be produced relatively easily.

In the embodiment shown in FIG. 5, phosphorus is introduced into the seventh Si 15 plate 27 to form the high concentration layer 29. 10”
It may contain impurities at a high concentration of cm-'.

〔Effect of the invention〕

As described above, according to the semiconductor device of the present invention, the structure is Si substrate/high concentration layer of phosphorus/first Si layer/second Si layer, and the maximum concentration is in the vicinity of the second Si layer. is I
Since the layer has a high phosphorus concentration layer containing P particles of Xl019c m-'' or more, the heavy metal particles contained in the second Si layer can be efficiently captured.

Further, a second Si layer is formed between the second Si layer and the high phosphorus concentration layer.
1xlO17c m-”~Ix1 with a higher concentration than the layer
The first Si containing impurity particles of one conductivity type of 019 cm-'
Because of the compensation effect of the majority carriers in the first Si layer, it is possible to prevent an increase in the leakage current of the element due to the release of minority carriers from the high phosphorus concentration layer.

Furthermore, according to the method of manufacturing a semiconductor device of the present invention, since the semiconductor device having the above structure is manufactured by laminating Si substrates, compared to the conventional case where the semiconductor device is formed on a substrate by epitaxial growth or the like, The crystallinity of the second Si layer serving as the element forming layer is good. Further, the above-mentioned Si base substrate/high concentration phosphorus layer-high concentration first Si layer of conductivity type/-
A wafer having a complex structure of a conductive type low concentration second Si layer can also be produced relatively easily.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a wafer according to an embodiment of the first and second inventions, FIG. 2 is a sectional view illustrating a method for producing a wafer according to an embodiment of the third invention, and FIG. FIG. 4 is a cross-sectional view explaining a method of manufacturing a wafer according to an embodiment of the fifth invention; FIG. FIG. 6 is a cross-sectional view illustrating a method for producing a wafer according to an embodiment of the fourth invention; FIG. FIG. 7 shows Cu1 in the wafer according to the fourth embodiment of the invention.
Fig. 8 is a cross-sectional view illustrating a wafer having a conventional trapping layer for heavy metal particles, and Fig. 9 is a diagram showing the preparation of a wafer having a conventional trapping layer for heavy metal particles. It is a sectional view explaining a method. [Explanation of symbols] ■...CZ wafer, 2...Oxygen precipitate, 3...Wafer, 4.7.10...Si substrate, 5...Element formation layer, 6...Capture Layer, 8.8a, 11, 16, 20.20a, 26.30...
・Phosphorus high concentration layer, 9...Epitaxial layer (element formation layer), 12.21
...First Si layer (n+ type Si layer), 13.22...
・Second Si layer (n-type Si layer), 14...first Si
Substrate, 14a... first Si substrate (first Si layer), 15.
...Second Si substrate (Si substrate), 17.31...S
i layer (second Si layer), 18... third Si substrate, 19... fourth Si substrate (Si substrate), 23... fifth Si substrate, 23a... fifth Si substrate (second Si layer), 24.
...Sixth Si substrate (Si substrate), 25, 29a-...
High concentration layer (first Si layer), 27... Seventh Si substrate, 2nd... Eighth Si substrate (Si substrate), 29... High concentration layer.

Claims (6)

[Claims] (1) A Si substrate on which a high phosphorus concentration layer containing phosphorus (P) particles with a maximum concentration of 1×10^1^9 cm^-^3 or more is formed on one surface, and a Si substrate formed on the high phosphorus concentration layer. The concentration is 1×10^1^
A first Si layer containing impurity particles of one conductivity type of 7 cm^-^3 to 1 x 10^1^9 cm^-^3, and a second Si layer of one conductivity type formed on the first Si layer. Si
A semiconductor device having a layer. (2) The first Si layer/second Si layer is n
2. The semiconductor device according to claim 1, wherein the semiconductor device is a ^+ type Si layer/n type Si layer or a p^+ type Si layer/p type Si layer. (3) A high phosphorus concentration layer containing phosphorus (P) particles with a maximum concentration of 1 x 10^1^9 cm^-^3 or more was formed on one surface, with a concentration of 1 x 10^1^7 cm^-^3 ~1×10^1
The first S containing one conductivity type impurity particles of ^9cm^-^3
a step of bonding an i-substrate and a second Si substrate such that one surface of the first Si substrate and the second Si substrate face each other, and the high phosphorus concentration layer and a layer other than the high phosphorus concentration layer. removing the first Si substrate so that the first Si substrate (first Si layer) remains; and depositing a second Si substrate of one conductivity type on the remaining first Si substrate.
1. A method for manufacturing a semiconductor device, comprising the step of forming a layer. (4) A third Si substrate on which a high phosphorus concentration layer containing phosphorus (P) particles with a maximum concentration of 1×10^1^9 cm^-^3 or more is formed on one surface, and a fourth Si substrate. the third S
a step of laminating one surface of the i-substrate and the fourth Si substrate so as to face each other;
a step of removing the i-substrate; and a step of sequentially depositing a 1×10
^1^7cm^-^3~1x10^1^9cm^-^3
A method for manufacturing a semiconductor device, comprising: forming a first Si layer containing impurity particles of one conductivity type; and a second Si layer of one conductivity type. (5) Maximum density is 1x10^1^7cm^-^3~1x
A fifth Si substrate of one conductivity type on which a high concentration layer containing impurity particles of one conductivity type of 10^1^9cm^-^3 was formed on one surface, and a maximum concentration of 1x10^1^9cm^- A sixth Si substrate of one conductivity type on one surface of which a high concentration layer of phosphorus (P) containing phosphorus (P) particles of 3 or more is formed, and one surface of the fifth Si substrate and the sixth Si substrate. a fifth Si substrate so that the high concentration layer (first Si layer) and a fifth Si substrate (second Si layer) other than the high concentration layer remain; A method for manufacturing a semiconductor device, the method comprising the step of removing. (6) Maximum density is 1x10^1^7cm^-^3~1x
A seventh Si substrate of one conductivity type in which a high concentration layer containing impurity particles of one conductivity type of 10^1^9 cm^-^3 was formed on one surface, and a maximum concentration of 1 × 10^1^9 cm^- An eighth Si substrate on which a high concentration layer of phosphorus (P) containing phosphorus (P) particles of ^3 or more is formed, one surface of the seventh Si substrate and one surface of the eighth Si substrate are At least the high concentration layer (first Si layer)
A semiconductor device comprising the steps of: removing a seventh Si substrate such that a seventh Si substrate remains; and forming a second Si layer of one conductivity type on the remaining seventh Si substrate. Production method.