JPS6379677U - - Google Patents
Info
- Publication number
- JPS6379677U JPS6379677U JP17347886U JP17347886U JPS6379677U JP S6379677 U JPS6379677 U JP S6379677U JP 17347886 U JP17347886 U JP 17347886U JP 17347886 U JP17347886 U JP 17347886U JP S6379677 U JPS6379677 U JP S6379677U
- Authority
- JP
- Japan
- Prior art keywords
- board
- side electrode
- substrate
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 238000005192 partition Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は本考案の一実施例を示す平面図、第2
図は第1図の―線断面図、第3図は従来の混
成集積回路装置を示す平面図、第4図は第3図の
―線断面図である。
1:基板、2:リードレスチツプキヤリア、3
:基板側電極、4:キヤリア側電極、5:ハンダ
、6:配線パターン、7:絶縁パターン。
Figure 1 is a plan view showing one embodiment of the present invention;
1, FIG. 3 is a plan view showing a conventional hybrid integrated circuit device, and FIG. 4 is a sectional view taken along the line in FIG. 3. 1: Board, 2: Leadless chip carrier, 3
: Board side electrode, 4: Carrier side electrode, 5: Solder, 6: Wiring pattern, 7: Insulating pattern.
Claims (1)
記基板に設けた接続用の基板側電極と前記リード
レスチツプキヤリアに設けた接続用のキヤリア側
電極とをハンダにより電気的に接続した混成集積
回路装置において、前記基板側電極の相互間に、
当該基板側電極の厚みよりも厚く且つ隣合う基板
側電極間を仕切る絶縁パターンを形成したことを
特徴とする混成集積回路装置。 In a hybrid integrated circuit device in which a leadless chip carrier is mounted on a board, and a board side electrode for connection provided on the board and a carrier side electrode for connection provided on the leadless chip carrier are electrically connected by solder. , between the substrate side electrodes,
A hybrid integrated circuit device characterized in that an insulating pattern is formed that is thicker than the thickness of the substrate-side electrode and partitions between adjacent substrate-side electrodes.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17347886U JPS6379677U (en) | 1986-11-12 | 1986-11-12 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17347886U JPS6379677U (en) | 1986-11-12 | 1986-11-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6379677U true JPS6379677U (en) | 1988-05-26 |
Family
ID=31110973
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17347886U Pending JPS6379677U (en) | 1986-11-12 | 1986-11-12 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6379677U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009212228A (en) * | 2008-03-03 | 2009-09-17 | Shinko Electric Ind Co Ltd | Wiring substrate and method of manufacturing the same |
JP2011134818A (en) * | 2009-12-24 | 2011-07-07 | Shinko Electric Ind Co Ltd | Semiconductor element built-in substrate |
-
1986
- 1986-11-12 JP JP17347886U patent/JPS6379677U/ja active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009212228A (en) * | 2008-03-03 | 2009-09-17 | Shinko Electric Ind Co Ltd | Wiring substrate and method of manufacturing the same |
JP2011134818A (en) * | 2009-12-24 | 2011-07-07 | Shinko Electric Ind Co Ltd | Semiconductor element built-in substrate |
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