JPH01174940U - - Google Patents
Info
- Publication number
- JPH01174940U JPH01174940U JP7134988U JP7134988U JPH01174940U JP H01174940 U JPH01174940 U JP H01174940U JP 7134988 U JP7134988 U JP 7134988U JP 7134988 U JP7134988 U JP 7134988U JP H01174940 U JPH01174940 U JP H01174940U
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- semiconductor element
- metal base
- copper
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 238000010292 electrical insulation Methods 0.000 claims 1
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
Description
第１図は、本考案による半導体素子搭載用絶縁
基板の一実施例を示す正面図。第２図ａ、及びｂ
は本考案の他の実施例を示した正面図である。第
３図ａは、従来の半導体素子搭載用絶縁基板を用
いて構成した半導体モジユールの平面図、ｂは正
面図、ｃは従来の半導体素子搭載用絶縁基板の正
面図である。
１……金属ベース。２……絶縁基板。３，５，
６……銅回路。４……半導体素子。７……銅板。
FIG. 1 is a front view showing an embodiment of an insulating substrate for mounting a semiconductor element according to the present invention. Figure 2 a and b
FIG. 3 is a front view showing another embodiment of the present invention. 3A is a plan view of a semiconductor module constructed using a conventional insulating substrate for mounting semiconductor elements, FIG. 3B is a front view, and FIG. 3C is a front view of a conventional insulating substrate for mounting semiconductor elements. 1...Metal base. 2...Insulating board. 3,5,
6...Copper circuit. 4...Semiconductor element. 7...Copper plate.
Claims (1)
上に半導体素子を搭載し、半導体素子と金属ベー
ス間に電気絶縁を施し、かつ外部電極を導出する
銅回路が形成される半導体素子搭載絶縁基板に於
て、近接する銅回路相互間の絶縁基板上の沿面距
離を増大した形状に絶縁基板に接着する銅回路の
側面に傾斜を持たせたことを特徴とする半導体素
子搭載用絶縁基板。 In an insulating substrate with a semiconductor element fixed to a metal base of a semiconductor module, a semiconductor element is mounted on it, electrical insulation is provided between the semiconductor element and the metal base, and a copper circuit is formed to lead out external electrodes. An insulating substrate for mounting a semiconductor element, characterized in that the side surfaces of the copper circuits bonded to the insulating substrate are sloped in a shape that increases the creepage distance on the insulating substrate between adjacent copper circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7134988U JPH01174940U (en) | 1988-05-30 | 1988-05-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7134988U JPH01174940U (en) | 1988-05-30 | 1988-05-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01174940U true JPH01174940U (en) | 1989-12-13 |
Family
ID=31296558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7134988U Pending JPH01174940U (en) | 1988-05-30 | 1988-05-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01174940U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001068623A (en) * | 1999-08-31 | 2001-03-16 | Mitsubishi Electric Corp | Semiconductor module |
-
1988
- 1988-05-30 JP JP7134988U patent/JPH01174940U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001068623A (en) * | 1999-08-31 | 2001-03-16 | Mitsubishi Electric Corp | Semiconductor module |
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