JPS6363285A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To output a video signal whose edge part is emphasized by compressing a time base in the edge part of an input video signal and expanding the time base before and/or after the edge. CONSTITUTION:The output signals (j) and l of subtractor circuits 14 and 15 are supplied to coefficient units 18 and 19 through full-wave rectifying circuits 16 and 17, and their level rate is set to 1 : 2, the both signals are taken out as signals (k) and (m). A signal (n) is outputted as a control voltage to a voltage controlled oscillator (VCO)23 from a subtractor circuit 20, and changes linear by so as to become shorter or longer according as its DC level is high or low. When the leading and tailing edges of input delay video signals from CCDs 26 and 27 show up, the output pulse period of the VCO 23 becomes shorter than when a writing action is made. The time width of output video signals from the reading CCDs 26 and 27 is a thing that the time base of a signal (o) is compressed. During a period just before and after the leading and tailing edges of the video signal (o), said time width is longer than that of an output pulse from an oscillator 24, and the video signal (o) with an expanded time base is read out. The amount that the time base is compressed is selected to be the same as a time base compressing amount in the edge.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal processing circuit, and more particularly to a processing circuit that sharpens rising and falling edges of a video signal.

BACKGROUND OF THE INVENTION FIG. 4 shows a block diagram of an example of a conventional video signal processing circuit. In the figure, a video signal a input to input terminal 1
are each delayed by a predetermined time by delay lines 2 and 3 connected in cascade. Here, input video signal a is shown in FIG.
When the video signal has a steep rising edge as shown in FIG. It has a rising edge.

The ohm circuit 4 subtracts the human input video signal a whose level has been adjusted by the attenuator 5 from the delayed video signal and the output delayed video signal C of the delay line 3 whose level has been adjusted by the attenuation S6, and calculates the result as shown in FIG. In (A), a video signal as shown by d is output. This video signal d is level-adjusted by an attenuator 7 and then supplied to an adder circuit 8, where it is added and synthesized with a delayed video signal having the same waveform as the original video signal a, as shown by e in FIG. 5(A). A video signal with a waveform like this is output to the output terminal 9.

This output video signal C has a waveform that emphasizes the rising edge portion of the original video signal a, and the edge portion (contour) of the image is sharpened.

Problems to be Solved by the Invention However, in the above conventional circuit, the input video signal is as shown in FIG.
[3) In the case of a waveform in which the edges are not steep but sloped and the rise time is long, as shown by a in [3], each output video signal of the delay lines 2 and 3, c, and the output video of the performance circuit 4. The signal d is as shown in FIG. 5(B), and the video signal output to the output terminal 9 is as shown in FIG. 5(B), as shown by e in FIG.
Although the rising edge of the original video signal waveform shown in a is somewhat emphasized, the time required for the rising edge is not reduced so much that the effect of sharpening the edges of the image is small.

In view of the above points, the present invention has a narrow band of the input video signal 8,
It is an object of the present invention to provide a video signal processing circuit capable of obtaining a video signal having a waveform with sharp edges even when the rise and fall times are long.

Means for Solving the Problems The video signal processing circuit of the present invention has a first level that is higher than a predetermined level when an edge of an input video signal is input, and a second level that is lower than a predetermined level at least immediately before or after the edge. A circuit that generates a control signal at a predetermined level when a video signal portion other than the edge and its vicinity is input, and a variable time axis that outputs the time axis of the input video signal by varying it according to the level of the control signal. It consists of means.

The action input video signal is supplied to each of the control signal generation circuit and the time axis variable means. By the time axis variable means, the input video signal is extracted with the time IB axis compressed at the edge portion, and the time axis is expanded and extracted at least one of immediately before and after the edge portion, and the input video signal is extracted with the time axis expanded at least one of immediately before and after the edge portion. The signal portion is extracted on the time axis as it is without being compressed/expanded on the time axis.

Embodiment FIG. 1 shows a block system diagram of an embodiment of the present invention. In the figure, an input video signal inputted to the input terminal 10 and having a waveform as shown in FIG.
8 delay line 12 with delay time 2τ and delay line 1 with delay time
3 is supplied to the cascade-connected circuit, and is also supplied to the subtraction circuit 14, where it is subtracted from the video signal taken out from the delay line 13 and delayed by 4τ (not shown by i in FIG. 2).

As a result, a signal indicated by j in FIG. 2 is taken out from the subtraction circuit 14. Furthermore, the video signal shown at 9 in FIG. 2 taken out from the delay line 11 and the video signal shown at h in the same figure taken out from the delay line 12 are reduced by the subtraction circuit 15 and are shown at 2 in the same figure. As shown, the waveform is generated at a portion corresponding to the edge portion of the input video signal and is converted into a triangular wave having a polarity corresponding to the direction of inclination of the edge.

The Yamada force signals j of the subtraction circuits 14 and 15 and the coefficients (level adjusters) 18 are passed through the double wave rectifier circuits 16 and 17.
．． 19, where the level ratio is set to 1:2 and the signals are taken out as signals shown as k and m in FIG.

The subtraction→circuit 20 performs the operation of subtracting the signal k from the signal m described above, and outputs a signal as shown by n in FIG. This signal n is a triangular wave of positive polarity when an edge of the input video signal f is input, a triangular wave of negative polarity both immediately before and after the edge, and a triangular wave of both positive and negative polarities when a video signal other than the edge and its vicinity is input. It is an intermediate level (center level).

The control voltage generation circuit 21 is constituted by the circuit described above, and the signal n is output from the subtraction circuit 20 as a control voltage to the voltage-controlled Al1 oscillator (VCO) 23 to variably control its oscillation cycle. (2) A VCO is used for the CO 23, which linearly changes its oscillation period so that when the DC level of the signal n is high, the oscillation period becomes short, and when the DC level of the signal n is low, the oscillation period becomes long. An example of such a VCO is, for example, Journal of the Society of Television Engineers, Vol. 31, No. 7, No. 5.
The one shown in FIG. 1(a) on page 60 (40) can be used. The output signal of this VCO 23 is sent to a charge coupled device (COD) 26 (described later) in the memory section 30.
and 27 are used as clock pulses for reading.

On the other hand, the input video signal f is delayed by 2τ by the delay line 22 in order to synchronize with the control voltage n.
After being made into a delayed video signal as shown in , C0D26 and 2
7, respectively. After the delayed video signal O of one horizontal scanning period (1H) is written to the CCDs 26 and 27,
This written video signal is read out at the IH. Further, when one of the CCDs 26 and 27 is performing a write operation, the other is performing a read operation, and the read and write operations are performed alternately every day.

However, the switching circuits 25, 28 and 2 are switched by switching pulses with a repetition frequency (1/2) fH.
9, during the 1H period when the switch circuits 25, 28 and 29 are connected to the terminals 25R, 28W and 29a, the output pulse of the VCO 23 is connected to the C through the switch circuit 25.
It is supplied to 0D26 as a read clock pulse,
While reading out the video signal written in the C0D 26 1H before, a pulse with a constant period taken out from the oscillator 24 is applied to the C0D 27 as a write clock pulse through the switch circuit 28, and has the same waveform as the input video signal f. The delayed video signal 0 is written. Here, the number of stages of the CCDs 26 and 27 and the period of the output pulse of the oscillator 24 are selected to obtain a delay time of 1H.

Furthermore, the period of the output pulse of the VCO 23 is the period rg1 of the output pulse of the oscillator 24 when the control voltage nB is at the center level.
is set to be the same as.

During the next 1H period, the switch circuits 25, 28 and 2 are switched and connected to the terminals 25W, 28R and 29b, respectively, and this time, C0D26 performs the writing operation of the delayed video signal 0 during the next 1HII11, and C0D27 is switched to the 1H Read out all the previously written video signals for one day. below,
The same operation as described above is repeated alternately every day, and the switch circuit 29 filters the output video signal of the COD which is always performing the read operation out of the CCDs 26 and 27 through a low-pass filter (LPF) for removing clock pulse frequency components. )31
The selected signal is selectively output to the output terminal 32 via.

Here, as mentioned above, the period of the output pulse of the VCO 23 is shorter at the rising edge and falling edge of the input fJat extended video signal 0 of the CCDs 26 and 27 than at the time of one slope (at the center of the slope (the shortest). For this reason V
C0 performs read operation by output pulse of CO23
The time axis of the output video signal of D26.27 is the time axis of the input delayed video signal 0 which is compressed. On the other hand, VCO2
The period of the output pulse No. 3 is approximately 24 times the period immediately before and after the rising edge and falling edge of the video signal O.
Since it is longer than that of the output pulse of C0D26.
27, the video signal 0 is read out with the time axis expanded. Here, this time axis expansion is selected to be the same as the amount of time axis compression at the edge.

In addition, in cases other than the above, the period of the output pulse of the VCO 23 is the same as the period of the output pulse of the oscillator 24, so the input delayed video signal 0 is not compressed/expanded on the time axis, but simply extended by 1)]''!1. As a result, as shown by p in FIG. It will be taken out.

By the way, in this embodiment, the video information stored in the CCD 26, 27 that is read out with respect to the control voltage n is delayed by 1 day, so the video signal regarding the picture with no line correlation is In time axis compression and expansion, the control voltage n does not correspond to the edges of the video information stored in the CCD 26, 27, resulting in a problem that edge correction (contour enhancement) cannot be performed sufficiently.

The video recording signal processing circuit shown in FIG. 3 is an embodiment of the present invention that solves this problem. In the figure, the same components as those in FIG.

In this embodiment, the control voltage from the control voltage generation circuit 21 is 1H.
It is applied to the VCO 23 with a delay of 1H by the n extension line 33.

Thereby, the time relationship between the video signal supplied to the memory section 30 from the delay line 22 and the clock pulse applied to the memory section 30 from the VCO 23 becomes the same. Note that the delay line 22 may be omitted and a delay circuit with a delay time (IH-2τ) may be provided in place of the 111 Chikanobu line 33.

',E,B,In the above embodiment, after writing/υ with a clock pulse of a constant period to C0D26.27,
Although the clock period is changed in the vicinity of the edge and in the edge portion during reading, the present invention is not limited to this, and the period of the write clock pulse is shortened in the vicinity before and after the edge of the input video signal, In order to control VCO23 so that it becomes long at
23, the W control voltage n may be inverted and applied. ),
Even if the output clock pulse of the oscillator 24 is used for reading, the desired effect can be obtained as well. in this case,
There is an advantage that the approximately 11'' time adjustment by the 11'' delay '633 is not required.

In addition, it is also possible to carry out the introspection only either immediately before or immediately after the input video signal. In this case as well, it is necessary to expand the time axis by 45 times by the amount of time axis compression so that there is no overall time axis variation. Further, in the above embodiment, COD is used as the time axis compression and expansion means, but the present invention is not limited to this, and a configuration consisting of a digital memory and an AD converter and an OA converter on the input/output side thereof may also be used.

Effects of the Invention As described above, according to the present invention, the time axis is compressed at the edge portion of the input video signal, and the time axis is expanded at either or both immediately before and after the edge. Even if the edge part of the signal has a slight slope, it is possible to output a video signal with the edge part emphasized better than before, making it possible to sharpen the edge part of the image. It has features such as:

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the circuit of the present invention;
2 is a signal waveform diagram for explaining the operation in the block system shown in FIG. 1, FIG. 3 is a block system diagram showing another embodiment of the circuit of the present invention, and FIG. 4 is a block system showing an example of the conventional circuit. Figure, Figure 5(A). (B) (This is a signal waveform diagram for explaining the operation in the block system shown in FIG. 4, respectively. 10... Video signal input terminal, 11 to 13, 22...
Delay line, 21... system! 11 voltage generation circuit, 23...
Voltage controlled oscillator (VCO), 24... oscillator, 26
．． 27...C0D (charge coupled device), 30...memory section, 32...video signal output terminal. Patent Applicant Victor Company of Japan Co., Ltd. Figure 2 8 Temple P = tl -1zum- Figure 5

Claims (2)

[Claims] (1) An input video signal is supplied, and when an edge of the input video signal is input, the first level is higher than a predetermined level, and at least either immediately before or after the edge, the second level is lower than the predetermined level. a circuit that generates a control signal at a predetermined level when a video signal portion other than an edge and its vicinity is input; and a circuit to which the input video signal and the control signal are respectively supplied, and when the control signal is at the first level; The time axis of the input video signal is compressed and output, the time axis is expanded when the input video signal is at the second level, and the video signal is output without compressing and expanding the time axis when the input video signal is at the predetermined level. 1. A video signal processing circuit comprising: time axis variable means; and configured to extract a video signal with emphasized edges from the time axis variable means. (2) The time axis variable means includes an oscillator that oscillates and outputs a first clock pulse with a constant period, a variable frequency oscillator that outputs a second clock pulse whose period changes depending on the control signal level, and Claim 1 comprising a memory section that writes the input video signal with one of the first and second clock pulses and reads out the written video signal with the other clock pulse. The video signal processing circuit described in .