JPS63281457A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To shorten a distance between a contact hole for a transistor and a gate electrode, and to reduce the area of a memory cell and improve the degree of integration by forming the contact hole for a memory-cell bit line onto flattened polycrystalline silicon shaped so as to be superposed on the gate electrode. CONSTITUTION:First layer polycrystalline silicon formed onto a p-type silicon substrate 1 through thin gate insulating films 12 or gate electrodes 3 as word lines for a memory cell are coated with insulating films 14 consisting of SiO2, etc., shaped in a self alignment manner. Polycrystalline silicon 6 is shaped to a storage capacitance section and polycrystalline silicon 8 as upper electrodes onto the polycrystalline silicon 6, and a contact hole on flattened polycrystalline silicon 61 is formed extending over the upper sections of the gate electrodes 3 in the contact section of a bit line. A MOS transistor has low-concentration drain structure, and source.drain regions 4, 5 being in contact with polycrystalline silicon 6, 61 are shaped in high-concentration n-type regions. Margins among the contact hole and the word lines 3 can be brought to zero.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and particularly to a dynamic MOS random access memory (hereinafter referred to as dynamic MO8-RAM) that can be highly integrated.

[Conventional technology]

As dynamic MO8-RAM becomes highly integrated, it is necessary to reduce the area of memory cells. To avoid this, the charge storage capacitor is connected to the word line 3 as shown in FIG.
The structure formed in a laminated manner on top of the
It is described in. One bottleneck in reducing the area of this stacked capacitive memory cell and improving the integration density of the memory cell is the connection method between the high concentration n-swelled diffusion layer 4 of the MOS transistor and the bit line electrode 10. . In the conventional structure, as shown in FIG. 2, since the bit line electrode 10 is in direct contact with the diffusion layer 4, a contact hole is formed on the diffusion layer. In order to prevent short circuits, the contact hole 11 must be separated from the word line 3 in consideration of mask misalignment, which has been an obstacle to reducing the memory cell area. In particular, in order to improve the withstand voltage of MOS transistors, a lightly doped drain (Lig.
When a MoS transistor having a Doped Drain (hereinafter abbreviated as LDD) structure is used in a memory cell, the contact hole 11 is formed in such a way that the contact hole 11 does not come into contact with the low concentration drain portion 13 even if there is mask alignment misalignment. It was necessary to further distance the memory cell from the gate electrode 3, which is a word line, making it even more difficult to reduce the memory cell area.

[Problem that the invention seeks to solve]

As described above, in the stacked capacitive DRAM memory cell having the conventional structure, the contact hole structure between the data line and the source/drain diffusion layer of the MOS transistor has been an obstacle in miniaturizing the memory cell.

An object of the present invention is to shorten the distance between the contact hole and the gate electrode of a MOS transistor in a memory cell, thereby reducing the memory cell area and improving DR.
The purpose is to improve the degree of integration of AM.

[Means for solving problems]

In order to achieve the above object, the present invention provides a multilayer capacitor type DR.
In AM memory cells, MOS that the bit line should contact
Flattened polycrystalline silicon is formed on the source/drain diffusion layer of the transistor so as to overlap with the gate electrode, and the diffusion layer and the polycrystalline silicon are brought into contact with each other in a self-aligned manner to form a contact for a pit line. The hole is formed on the planarized polycrystalline silicon layer.

[Effect]

In the present invention, since the contact hole for the memory cell bit line is provided on the flattened polycrystalline silicon formed so as to overlap the gate electrode, the contact hole is arranged so as to be located on the gate electrode of the MOS transistor. However, the contact hole never comes into direct contact with the gate electrode.

Therefore, there is no need to provide a margin for mask alignment between the gate electrode, which is the word line of the memory cell, and the contact hole, and the memory cell area can be significantly reduced.
It is possible to achieve high integration of M. Furthermore, the area of the source/drain diffusion layer of the MOS transistor connected to the bit line can be significantly reduced, making it possible to reduce junction leakage current, and also reducing the collection area of noise charges generated by alpha rays, etc. Reliability such as soft errors can be improved. Furthermore, in the structure according to the present invention, even if a lightly doped drain structure is used in the switching MoS transistor of the memory cell, contacts and holes can be prevented from coming into direct contact with the lightly doped drain part, so the MOS transistor can be connected without increasing the area of the memory cell. It is possible to achieve high voltage resistance and high reliability.

In addition, since the contacts for the bit lines are formed on flattened polycrystalline silicon, it is easy to process fine contact holes, and the coverage of the metal bit lines in the contact holes is improved. Significant improvement in reliability as electrode wiring.

〔Example〕

The present invention will be explained in detail below.

FIG. 1 is a cross-sectional structural diagram of a memory cell showing a first embodiment of the present invention. 10 to 5 Qnm on p-type silicon substrate 1
A gate electrode 3 serving as a word line of a memory cell is formed by a first layer of polycrystalline silicon or silicide, a high melting point metal, or a composite film thereof, with a gate insulating film 12 having a relatively thin thickness interposed therebetween. This gate electrode 3 is covered with an insulating film 14 such as SiO2 formed in a self-aligned manner, and polycrystalline silicon 6 is formed in the storage capacitor part so as to overlap with this insulating film 14, and is connected to the bit line. A flattened polycrystalline silicon 6 is formed in the contact portion. This polycrystalline silicon 6.61 has a high concentration of n-type dopant added, and these polycrystalline silicon
It is in contact with the source/drain diffusion layer of the OS transistor. The polycrystalline silicon 6 on the right and left sides of FIG. 1 serve as the lower electrodes of the memory cell storage capacitor, and the polycrystalline silicon 61 in the center serves as an underlying layer for the bit line contact portion.

In the storage capacitor section, a layer with a thickness of 5 to 2
An extremely thin insulating film 7 of about 0 nm is formed, and polycrystalline silicon 8 is further formed as an upper electrode on top of the insulating film 7.

In the contact portion of the bit line, a contact hole on the polycrystalline silicon 6] is formed so as to overlap the gate electrode 3, which is the word line. The MOS transistor has a low concentration drain structure, and the source/drain regions 4 and 5 in contact with the polycrystalline silicon 6 and 61 are high concentration n-bulk head regions.

FIG. 4 is a plan layout diagram of a memory cell according to the prior art for comparison, and FIG. 5 is a plan layout diagram of a memory cell according to the present invention. In these two plan layout diagrams, the layout margin between the bit line contact hole 11 and the word line 3 is assumed to be d. In the conventional technology, the layout margin d is set large as shown in FIG. 4 in consideration of the mask misalignment between the contact hole 11 and the word line 3, but in the present invention, as shown in FIG. Since the layout margin between the contact hole 11 and the word line 3 is almost zero, the memory cell area can be reduced by 30 to 50% compared to a conventional memory cell.

A second implementation of the invention is shown in FIG. In this embodiment, an insulating film 15 of SiOx or the like is formed to a thickness of about 50 to 500 nm on the polycrystalline silicon 61 formed in the bit line contact portion, and the insulating film 15 covers the polycrystalline silicon 8 of the storage capacitor upper electrode. When etching polycrystalline silicon 6
1 is protected.

In contrast, in the first embodiment, when polycrystalline silicon 8 is etched, only extremely thin insulating film 7 for forming storage capacitance is placed on polycrystalline silicon 61. For this reason, when over-etching the polycrystalline silicon 8 to avoid etching residue in the stepped portion, etching with a high etching selectivity is necessary to prevent the ultra-thin insulating film 7 on the polycrystalline silicon 61 from being completely etched. It is necessary to use advanced dry etching techniques. In contrast, the present embodiment described above has the advantage that memory cells can be manufactured without using the sophisticated etching technology required in the first embodiment. Note that the manufacturing process of this example will be described later.

A third embodiment of the invention is shown in FIG. In this embodiment, a second layer of polycrystalline silicon 6 is provided in the bit line contact portion 11.
At the same time, a third layer of polycrystalline silicon 8 is formed. With this structure, the bit line contact hole 11 is filled with the third layer of polycrystalline silicon 8, so the depth of the contact hole can be made equal to that of the first embodiment. Therefore, the coverage of the bit line 10 with metal or silicide in the contact hole portion is improved, and reliability and production yield are increased.

A fourth embodiment of the invention is shown in FIG. In this embodiment, the surfaces of polycrystalline silicon 16 and 161 are both flattened as shown.

Such a structure has the advantage that fine processing by lithography or dry etching is facilitated because the base is flattened when the third layer of polycrystalline silicon 8 is processed. Furthermore, since the bit line contact hole 11 is formed on the flattened second layer polycrystalline silicon 161, microfabrication of the contact hole is facilitated, and at the same time, coverage of the bit line electrode in the contact hole is improved. , contributes to improving manufacturing yield. Note that the manufacturing process of this example will also be described later.

A fifth embodiment of the invention is shown in FIG. This embodiment is not a stacked capacitor type memory cell, but a planar type memory cell in which an extremely thin oxide film 7 is formed on the surface of a silicon substrate. In this memory cell, the first layer of polycrystalline silicon 8 serves as a storage capacitor plate electrode, and the second layer of polycrystalline silicon or a composite film 3 of a silicide layer and polycrystalline silicon serves as a word line. ing. In this memory cell as well, in order to shorten the distance between the bit line contact hole 11 and the gate electrode 3 and reduce the area of the memory cell, a third layer of polycrystalline silicon is added to the bit line contact portion as in the previous embodiment. It is preferable to form a contact hole 18 and provide a contact hole 11 thereon.

The manufacturing process of this example will also be described later.

Next, each method of manufacturing a memory cell according to the present invention will be described. FIG. 10 is a manufacturing process diagram showing the manufacturing method of the first embodiment. First, a thick field oxide film 12 with a thickness of about 0.1 to 1.0 μm, a thin gate oxide film 12 with a thickness of 2.5 to 50 nm, and a first layer gate electrode 3 made of polycrystalline silicon, silicide, high melting point metal, etc. are formed. After that, add n-type inert substances such as phosphorus and arsenic to 1012-1014(1)-
2 ions are implanted to form an n-shaded region 13. Thereafter, the gate electrode 3 is covered with an Si02 film 14 having a thickness of 0.2 to 0.4 μm using a chemical vapor deposition method (CVD method) or a thermal oxidation method. The Si○2 film 14 covers the gate electrode in a self-aligned manner without using a mask alignment process, and thus contributes to reducing the memory cell area. After that, after forming a thin oxide film 22 of about 10 to 20 nm on the surface of the silicon substrate, using the SiO2 film 14 covering the gate electrode as a mask, 1015 to 1016 an inch of n-type inert material such as phosphorus or arsenic is implanted. Form n shadow area 4.5.

Next, the thin insulating film 22 is removed only on the sources and drains where the bit line contact holes will be formed, and then polycrystalline silicon is grown by chemical vapor deposition so that the surface is flattened, or A polycrystalline silicon electrode 6] is etched back by dry etching so that it is flattened. Note that this polycrystalline silicon 61 is doped with n-type inert substances such as phosphorus and arsenic at a high concentration (FIG. 10A).

Next, a polycrystalline silicon layer 6 with a thickness of 0.1 to 0.5 μm containing a high concentration of n-type inert material is formed (FIG. 10B). Polycrystalline silicon 61 and silicon substrate n in the bit line contact area
The contact area with the 10 region 4 is the hatched area in FIG. 5, and since this area is determined by the 5iOz film 14 and the field oxide film 2 that cover the gate electrode formed in a self-aligned manner, the mask alignment process is necessary. Regardless of the size, the area can be reduced to 1 μm or less, contributing to a reduction in the memory cell area.

Next, an extremely thin insulating film 7 with a thickness of 5 to 20 nm is formed over the entire surface of the wafer. This insulating film 7 is composed of a 5iOz film, a 5isNt film, or a 5isN4 film deposited by chemical vapor deposition.
A composite film of an iOx film, a composite film of a Ta205 film and a 5iOz film, a composite film of a TazOs film and a SigNt film, etc. can be used. Next, polycrystalline silicon 8 is formed as the upper plate electrode of the storage capacitor so as to cover the ultra-thin insulating film 7. After forming the polycrystalline silicon 8, by oxidizing the surface of the polycrystalline silicon, it is possible to improve the interlayer breakdown voltage between the polycrystalline silicon and other layers, or to reduce the leakage current caused by the etching of the polycrystalline silicon at the stepped portion. It is also possible to prevent the occurrence of (Fig. 10C). Next, a surface protection film 9 made of a PSG film or the like is formed, contact holes 11 are opened, and electrodes 10 are formed (FIG. 10D).

Next, FIG. 11 shows a manufacturing process of a third embodiment of the present invention. The manufacturing process up to the step of forming polycrystalline silicon 6.61 is the same as that shown in FIG. 10 (FIG. 11A). Next, a thin 5iaNa film 23 with a thickness of about 10 to 20 nm is deposited on the wafer surface by chemical vapor deposition, and a SiOx film 23 with a thickness of about 50 to 500 nm is deposited on top of the 5iaNa film 23.
is deposited by chemical vapor deposition to form a pattern. In order to leave this SiO2 film 21 only on the polycrystalline silicon 61 in the bit line contact area, the 5ift film 21 in other areas
must be removed by etching. Hydrofluoric acid-based wet etching is preferable for etching the SiO2 film 21 even at step portions; In order to prevent the Ox film from being scratched, a 5isNt film 23 is formed under the 5iOz film 21, which is resistant to hydrofluoric acid etching solution (FIG. 11B). Next, Si○2 film 21 film island 1
After etching the 8N4 film 23, an extremely thin insulating film 7 of about 5 to 20 nm for a capacitor is formed on the wafer surface. After that, polycrystalline silicon 8 is deposited to a thickness of 100 to 500 nm.
(Fig. 11C). In the dry etching of polycrystalline silicon, since the Si○2 film 21 film island 1 is used as the base of the area where polycrystalline silicon is removed, the polycrystalline silicon 61 in the bit line contact area is not etched away, and the fine details of the polycrystalline silicon 8 are removed. Makes processing easier. Next, P.S.G.
A surface protection film 9 made of a film or the like is formed, a contact hole 11 is opened, and an electrode 10 is formed (FIG. 11D).

Next, we will discuss the manufacturing process of the fourth embodiment of the present invention.
This will be explained using Figure 2. MOS transistor source
The steps up to the formation of drain diffusion layers 4 and 5 are the same as in FIG. 10A. After that, a relatively thick polycrystalline silicon 24 with a thickness of about 0.5 to 2 μm is deposited by chemical vapor deposition, and a photoresist film 25 is further applied on top of the polycrystalline silicon 24 with a thickness of 1 to 2 μm.
It is formed to a thickness of about μm (FIG. 12A). Next, the photoresist film is etched back from the surface to expose the surface 26 of the second layer of polycrystalline silicon (FIG. 12B). Next, the second layer polycrystalline silicon is etched back to remove the photoresist film, thereby flattening the second layer polycrystalline silicon surface 24' (FIG. 12C). Note that if the surface is flat when the second layer of polycrystalline silicon 24 is deposited, it is not necessary to form the photoresist film 25, and it is sufficient to etch back only the polycrystalline silicon layer. Next, the second layer of polycrystalline silicon 24 is patterned to realize the shape shown in Figure 12.

The subsequent steps are the same as the manufacturing process shown in FIG.

Next, the manufacturing process of the fifth embodiment of the present invention will be explained using FIG. 13. 1018~ on the surface of P type silicon substrate
n shadow areas 5 and 101 with a density of 10"an-"
6-10 A p shadow region 17 having a concentration of am-2 and an ultra-thin oxide film 7 of 4 to 20 nm for a capacitor are formed on the surface of the silicon substrate, and a plate electrode is formed on the top by the first layer of polycrystalline silicon. 8 (Fig. 13A).

Next, a gate insulating film 12 having a thickness of approximately 10 to 50 nm is formed, and then word lines 3 are formed using polycrystalline silicon or a composite film of polycrystalline silicon and silicide.

Furthermore, 200-500 nm was deposited by chemical vapor deposition method.
The SiOx film is etched back to form an insulating film 14 surrounding the gate electrode 12. In order to form a low concentration drain structure, the low concentration n shadow region 13 is doped using the gate electrode as a mask, and the high concentration n shadow region 4 is doped using the insulating film 14 as a mask (FIG. 13B). Next, the surface of the Si substrate in the bit line contact area is exposed, and a conductive layer 18 in the bit line contact area is formed using a third layer of polycrystalline silicon, silicide, high melting point metal, or a composite film thereof (see FIG. 13). C). Next, a surface protection film 9 is formed using a PSG film, a contact hole 11 is opened, and a bit line electrode 10 is formed (FIG. 13D).

FIG. 14 shows a sixth embodiment. In this embodiment, the bit line 101 is formed of polycrystalline silicon or a composite film of polycrystalline silicon and a silicide layer, and this bit line itself flattens the bit line contact portion 11. This structure is simpler than the structure of the embodiment described above, and contributes to an improvement in manufacturing yield.

〔Effect of the invention〕

As described above, according to the present invention, the stacked capacitance type DRAM
In memory cells, it is no longer necessary to provide a margin for mask alignment between bit line contact holes and gate electrodes, and the memory cell area can be reduced to 50 to 70% of the area of conventional memory cells with the same microfabrication dimensions, allowing for higher DRAMs. It is possible to achieve higher integration density and larger capacity. Furthermore, since the contact 1- for the bit line is formed in a flattened area, fine machining of the contact hole is facilitated, and the coverage of the metal pin 1- line at the contact hole is greatly improved. This improves manufacturing yield and reliability. Also,
Since the self-aligned structure reduces the noise charge collection area to a fraction of that of a conventional memory cell, refresh characteristics determined by soft errors caused by alpha rays and junction leakage current can also be improved by an order of magnitude over the conventional structure. moreover,
It is possible to improve the breakdown voltage and reliability of a MOS transistor without increasing the memory cell area.

[Brief explanation of the drawing]

FIG. 1 is a vertical sectional view of the first embodiment of the present invention, FIG.
The figure is a vertical cross-sectional view of the conventional structure, and Figure 4 is a plan view of the conventional structure.
FIG. 5 is a plan view of one embodiment of the present invention, FIG. 6 is a longitudinal sectional view of a second embodiment of the invention, FIG. 7 is a longitudinal sectional view of a third embodiment of the invention, and FIG. 8 is a longitudinal sectional view of a third embodiment of the invention. FIG. 9 is a vertical cross-sectional view of the fourth embodiment of the present invention, FIG. 10 is a vertical cross-sectional view of the fifth embodiment of the present invention, and FIG.
Figure 1. FIG. 12 and FIG. 13 are process diagrams showing the manufacturing process of the first, second, third, fourth, and fifth embodiments of the present invention, respectively, and FIG. 14 is a longitudinal cross-section of still another embodiment of the present invention. It is a front view. 1.17...p shadow area, 4,5.13...n shadow area,
2.7, 9, 12, 14, 15, 22.23...Insulating film, 3...Word line, 6,61,8,16,161°18.24.24', 26...Multiple crystalline silicon, 1
0...Data line, 11...Contact hole, 25゜2
5'...Photoresist.

Claims (1)

[Claims] 1. A plurality of semiconductor substrates having a second conductivity type formed at desired intervals in a surface region of a semiconductor substrate having a first conductivity type divided by a thick insulating film for element isolation. An insulated gate field effect transistor comprising a gate electrode made of an impurity doped region and a first conductive film formed on the semiconductor substrate between the desired impurity doped regions via a first insulating film; and the gate electrode. a second insulating film formed on the top and sides of the gate electrode; a second conductive film extending from the second insulating film on the gate electrode to the thick insulating film through the surface of the impurity doped region; a storage capacitor composed of a third insulating film and a third conductive film stacked on the second conductive film; the impurity doped region formed between two adjacent memory cells; The second insulating film and the thick insulating film are electrically connected to each other through an opening defined by the thick insulating film, and a portion of the second insulating film overlaps with the second insulating film, and the surface thereof is planarized. and a fifth conductive film electrically connected to the fourth conductive film and extending over a fourth insulating film formed on the third conductive film. A semiconductor memory characterized by 2. A semiconductor memory characterized in that, in a stacked capacitive DRAM memory cell, the contact hole is configured in a self-aligned manner with respect to the word line by forming flattened polysilicon in the bit line contact hole portion.