JPH03268462A - Formation of memory cell - Google Patents

Abstract

PURPOSE: To increase integration density of cells by minimizing a cell area on a substrate by a method, wherein cell transistors are formed in a sidewall of a trench provided in the substrate forming a cell capacitor, and a word line and a bit line are mutually intersected in an upper part of the trench. CONSTITUTION: Transistors 18 of each memory cell 30 are of a bulk silicon structure having a polysilicon gate, and a channel 44 is a part of a P-epitaxial layer 34, and a source region 48 (a part of one pole plate of a capacitor 12) and a drain region 20 (a bit line 20) are N<+> -diffused substrates in the P-epitaxial layer 34, and a gate oxide layer 46 grows on a trench face of the P-epitaxial layer 34. Further, gates are a part of a word line 14 layer of polysilicon. An insulated oxide layer 42 has considerable thickness, and even so, the word line 14 gated is of a structure which overlaps the source and drain regions of transistors 18. Thereby, an electric charge storing area per unit area of the substrate is increased, and memory density can be maximized.

Description

[Detailed description of the invention]

[0001]

[Industrial application field]

The present invention relates to semiconductor devices, and particularly to dynamic random access memories, or dynamic RAMs (hereinafter referred to as dRAMs). [0002]

[Conventional technology]

The development of large-scale monolithic dRAM poses a number of issues, one of the most important of which is the need to shrink the dimensions of individual cells in order to increase the number of memory cells that can be integrated onto a single chip. The question is what can be done to prevent the incidence of soft errors from increasing. Large-scale dRAM uses silicon as the primary construction material, and each memory cell typically has a single MOS field effect transistor whose source is connected to the capacitor, drain to the bit line, and gate to the word line. It is. Such a memory cell operates such that when a charge is added to the capacitor, it becomes a logic 1, and when no charge is added, it becomes a logic 0. Conventionally, the cell capacitor in this case is formed by an inversion layer separated from the upper electrode layer by a thin oxide layer and separated from the substrate by a force depletion layer. However, in order to maintain stable circuit operation, it is necessary to set the capacitance of the capacitor to a large value that provides a sufficient S/N ratio. It has to be thick. Furthermore, such MOS capacitors are susceptible to charges generated in the substrate by alpha particles (a 5 MeV alpha particle can generate more than 200 hemtoclones (fC) of harmful electrons) and noise intruding from the substrate. It is susceptible to the effects of PN junction leakage over the entire area of the capacitor, subthreshold leakage (leakage below the threshold voltage) of the MOS FET in the cell, and the like. The charge stored in one dRAM is usually 250 fC, so if the power supply voltage is 5 V, the capacitance of the capacitor needs to be 50 fF, and if the thickness of the physical dioxide for charge storage is 150 A, then Approximately 20 square microns of capacitor area was required. In a memory cell using a conventional two-dimensional structure dRAM, this defines the minimum size of the cell. [0003] One attempt to solve these problems was made by Joly et al.
Dynamic RAM Ce1l in
Recrystallized Polysili
c. nJ (4IEEE Elec, Dev,
Lett, 8.1983), which attempts to form all of the basic elements of the cell, including the access transistor and charge storage capacitor, in a layer of beam-recrystallized polysilicon deposited on an oxide layer on a silicon substrate. . In this case, the bit line is included in the recrystallized polysilicon layer, and turning on the transistor causes charge to flow into the charge storage region. Highly doped recrystallized polysilicon surrounded by thermally grown oxide on the top, bottom and three sides is used as the charge storage region. The charge storage capacity obtained in this way is approximately the same as that of a normal capacitor with an equivalent storage area, because the electrodes above and below the region are separated from the charge storage region in the recrystallized polysilicon by a thin oxide layer. It will be doubled. Moreover, this charge storage region is isolated by the underlying oxide from charges injected into the substrate from circuits around the region, and from charges penetrating into the substrate due to alpha particles and other radiation that causes soft errors. Become. Additionally, the presence of a thick oxide layer below the bit line and complete sidewall oxide isolation may reduce the capacitance of the bit line. However, even if the capacity is twice the normal capacity, it is impossible to make the area occupied by the cell capacitor sufficiently small. [0004] Another attempt to miniaturize dRAM is to extend the capacitor plates into the interior of the substrate. Such a capacitor is called a corrugated capacitor, and is described in “A Corrugated Capacitor” by H. Sunami et al.
Capacitor Ce1l (CCC)f
or Megabit Dynamic MO3
MemoriesJ (IEEE IEDM T
ech, Digest 8061982) and “A Corrugated
Capacitor Ce1l (CCC) for
Megabit Dynamic MOS
MemoriesJ (4IEEE Elec,
Dev, Lett. 90.1983), and ■, Ito et al.'s “An
Expert mental 1Mb DRAM
with 0n-Chip Voltage
LimterJ (1984 IEEE l5S
CCDigest of Tech. Paper 282) etc. have a description thereof. This corrugated capacitor has 2.5
It extends to a depth of microns, and to manufacture it, a trench is formed by an etching method, and then wet etching is performed to remove scratches and dirt caused by dry etching. After forming the trench in this way,
A triple charge storage layer of silicon dioxide/silicon nitride/silicon dioxide is formed on the trench walls, and the trench is then finished by filling with LPGVD polysilicon. This is because such a corrugated capacitor, in the case of a three-layer, 7-micron cell with a capacitance of 60 fF, has a capacitance more than seven times that of a normal cell.

A third attempt to reduce the area occupied by cell capacitors is similar to the method of forming trenches as described above, for example, the "Submic" method by E.
ron MOS VLSI Process
TechnologiesJ (IEEE IED
M Tech, Digest 19, 1983
) "A Submicron" by Yani Minegishi et al.
CMO3Megabit Dynamic RA
M Technology Using Dop
ed Face Trench Capacit
or Ce1lJ (IEEE IEDMTec
h, Digest 319.1983) and T.
“Depletion Trench” by Morie et al.
h Capacitor Technology
or Megabit Level MOS
dRAMJ (4IEEE Elec, Dev
, Lett, 411.1983), etc. In all of these, the capacitor plate is formed on the trench wall of the substrate instead of being parallel to the substrate, but is similar to a normal cell. A memory cell having a similar configuration is described. Such a trench capacitor can have a large capacitance per unit area of the substrate simply by using a deep trench, and according to the three papers mentioned above, it is manufactured as follows. That is, first, crystal orientation (100) P type, resistivity 4
-5o-ACm(7) Radiation 0,4-1.0 on silicon substrate
A micron trench is formed using an electron beam direct writing method. Then, reactive ion etching with CB r F 3 (
After etching a trench to a depth of 1-3 microns by RIE), scratches caused by the RIE process are removed from the trench surface by etching in a mixture of nitric acid, acetic acid, and hydrofluoric acid. Next, PSG (phosphorus silicate glass) is deposited by CVD using a PH/5iH4102 gas system to diffuse phosphorus into the trench surface layer, and the PSG is etched away with hydrofluoric acid. Next, 150-500A of 3102 is grown on the trench surface in dry oxygen or by CVD to form Si3N4.
is deposited to a thickness of 500A, and finally the trench is filled with LPGVD polysilicon. In this way, the capacitance per unit area of the trench sidewall is comparable to the capacitance per unit area of a normal capacitor, and therefore a capacitor with a large trench depth increases the charge storage area per unit area of the substrate. By this, it is possible to reduce the substrate area of the cell. [0006] On the other hand, isolation using trenches is also a well-known technique, and its research has been widely conducted.
For example, “Deep Trench” by R. Lang
l5olated CMO3DevicesJ
(IEEE IEDM Tech, Dige
st 237.1982) and K. Cham et al.
A 5tudy of the trench
Inversion Problem in
the Trench CMO3Technol
ogyJ (4IEEE Elec, Dev,
Lett, 303.1983) and A. “U-Groove l5olat” by Hayasaka et al.
ion Technique for High
5peed Bipolar VLSI'
sJ (IEEE IEDM Tech, D
62.1982) and “An l5olation Technolo” by H. Goto et al.
gy for High Performance
Bipolar Memories--IOP-I
IJ (IEEE IEDM Tech, D
igest 58.1982) and “High-5peed Latchup-Fr” by T. Yamaguchi et al.
ee 05-μm-Channel CMO5Us
ing Self-Aligned TiSi2
and Deep Trench l5olat
ion Technologies (IEEE
IEDM Tech, Digest 52
2.1983) and “Direc” by S. Koyama et al.
tions in Cst 151.1983)
“Characterlzat” by K., K., and Cham et al.
ion and Modeling of
the Trench 5 surface Pro
blem for the trench I
solatedCMO3TechnologyJ (
IEEE IEDM Tech, Digest
23.1983) and others. The isolation trenches described therein are formed in a manner similar to that previously described for the fabrication of trenched corrugated capacitors. That is, patterning (typically done using an oxide mask), CBr
RIE treatment with F3, CCl4, Cl2H2, CClO3, etc., engraving treatment, thermal oxidation of the side wall (LPCV)
This method uses processing procedures such as forming a nitride layer by forming a nitride layer using D (D), or even embedding with polysilicon. [0007]

[Problems to be solved by the invention]

However, using a trench capacitor reduces the dR
This does not completely solve the problem of making AM cells smaller, and in any case, such as a vertically arranged FET or a substantially vertically arranged trench capacitor,
At present, the area occupied by the cell on the substrate is still large. [0008]

[Means for Solving the Problems] The present invention forms a cell transistor on the side wall of a trench provided in a substrate in which a cell capacitor is formed, and a word line and a bit line intersect with each other above the trench. The present invention provides a one-transistor dRAM cell structure and an array of such cells, which stack the transistors on top of the capacitors to minimize the cell area on the substrate, thereby increasing the This is to increase the density of cell integration. In one embodiment of the invention, one plate of the capacitor and the channel region of the transistor are formed in the bulk sidewall of the trench, and the other plate of the capacitor and the gate region of the transistor are formed in the trench. Formed by filling polysilicon and separated by an oxide layer inside the trench. Note that the signal charge is accumulated in the capacitor plate formed of the polysilicon. [0009]

【Example】

FIG. 1A shows a one-transistor, one-capacitor cell connected to a bit line and a word line as an embodiment of the present invention, and its operation mode is as follows. That is, the capacitor 12 stores a charge representing one bit of information (for example, a state in which no charge is stored represents a logic O, and a state in which a charge corresponding to a potential of 5 volts between the plates of the capacitor is stored represents a logic 1). ). This one bit of information is accessed (read or write a new bit) each time a voltage is applied to word line 14 connected to gate 16, thereby turning on transistor 18. This transistor 18
When the bit line 20 is turned on, the capacitor 12 is brought into conduction with the bit line 20, and reading or writing is performed. At this time, it is necessary to periodically refresh the charge in order to compensate for the loss of charge stored in the capacitor 12 due to leakage current or other causes, and this is the origin of the name dynamic RAM (dRAM). [0010] FIG. IB is a plan view showing a part of the array in which the memory cells 30 of the above embodiment are arranged at the intersection of each line in a dRAM array consisting of a word line 14 and a bit line 20, and the bit line 20 is a word line. It is formed to pass below the line 14. The memory cells 30 extend below these lines in the substrate to maximize memory density. Now, as shown in the diagram,
\If the figure size is f and the minimum layer alignment tolerance (minimum printing error tolerance) is R, the area of each cell is (2(f
+R)). Therefore, for example, the minimum figure size is 1.0
If the rJz layer spacing tolerance is 0.25 microns, the area of each cell will be approximately 6.25 square microns. [0011] FIG. 2 is a cross-sectional view of the memory cell 30 as an embodiment of the present invention. This memory cell 30 is formed on a P-type silicon substrate 32 having a P-type epitaxial layer 34, and includes a bit line 20 made of an N" type buried layer, an oxide layer 42 for bit line insulation, and an N" polysilicon layer. word line 14
, the channel 44 of the transistor 18 , the gate oxide layer 46 of the transistor 18 , the N diffusion region 48 forming the source region of the transistor 18 , and the P type substrate 32 connected to one side of the capacitor 12 , that is, the ground side terminal. It has an N 2 polysilicon region 50 that forms the other plate of the capacitor 12, and an oxide/nitride/oxide stack 52 that forms an insulating layer between the plates of the capacitor 12. The cross-section of memory cell 30 in FIG. 2 corresponds to arrow line 2--2 in FIG. IB, and therefore the cross-sectional structure of trench-formed capacitor 12 and transistor 18 will be clear from FIG. IB. [0012] In the memory cell 30 having the above-described configuration, one plate of the capacitor 12 has an N region 48.50.
The other plate is formed by a substrate 32 and a shrimp layer 34, respectively. However, in this case, by making the impurity concentration of the shrimp layer 34 much lower than that of the P type substrate 32, the capacitance of the N/P junction between the diffusion region 48 and the shrimp layer 34 and the N type polysilicon region 50/stack are reduced. The capacitance of the 52/P type epi layer 34 is much smaller than the capacitance of the N polysilicon region 50/stack 52/P substrate 32 and can be ignored. Further, as explained next, the plate area of the shrimp layer 34 is the same as that of the substrate 3.
For this reason, the capacity of the shrimp layer 34 itself is not a very important factor. In addition, when the cross section of the trench to be formed is 1×1 micron and the depth is 5 microns, this 1 micron depth shall be obtained by the shrimp layer 34 and the bit line 20 layer, and in this case, the pole of the capacitor 12 The plate area will be approximately 17 square microns. Also, the illustrated P substrate 32 is a ground layer common to all memory cells 30 in the array shown in FIG. IB. [0013] Transistor 18 of each memory cell 30 is of bulk silicon configuration with a polysilicon gate, channel 44 is part of P epi layer 34, and source region 48
The drain region 20 (which is also part of one plate of capacitor 12) and the drain region 20 (which is also bit line 20) is N diffused in the P epi layer 34 and is part of the word line 14 layer of galley silicon. . Although the insulating oxide layer 42 is fairly thick, the gate word line 14 is still configured to overlap the source and drain regions of the transistor 18. [0014] Next, an embodiment of a method for manufacturing the memory cell 30 having the above configuration will be described, and through this description, the dimensional and material characteristics of the memory cell 30 will also be clarified. FIGS. 3A to 3G show this production procedure. [0015] 1. A P silicon substrate 32 with a crystal orientation of (100) and a resistivity of 1xlO" ohm cm or less is coated with a carrier concentration of 2x1016/Cm3, and the final thickness after all heat treatments are completed. Grow a P epi layer 34 to a thickness of 2.0 microns.Field oxide layer 3
After forming 6 and P-type channel stop 38 by conventional methods, a stress relieving oxide layer is grown and LPVD nitride is deposited on the oxide layer. Next, by patterning and plasma etching the active region (the bit line 20 and the periphery of the cell array), nitride and oxide outside the active region are removed, and boron is implanted using the nitride layer as a mask to remove carriers. After forming a channel stop 38 with a concentration of 1×10 5 /Cm3 to a depth of 40 OA, the field oxide layer 36 is
is grown to a thickness of 800 OA. Then, after removing the nitride layer, a portion of the active region where the bit line 20 will be formed is defined by photolithography, and arsenic is implanted so that the carrier concentration is 1×10 20 /cm 3 . Add these bit lines 20 to a depth of 200
Formed to 0A. After that, the photoresist was removed and a protective film made of oxide was formed. The resulting structure is shown in Figure 3A.
and shown in FIG. 3B. Here, FIG. 3A shows the bit line 20
FIG. 3B is a cross-sectional view along a plane perpendicular to the bit line 20. FIG. Note that the line width of the bit line 20 is approximately 1.5 microns as described with reference to FIG. IB. [0016] 2. To form a trench with a cross section of 1 micron, a trench with a thickness of 1
A micron plasma enhanced CVD oxide layer 64 is deposited and patterned. A trench is etched to a depth of 1.25 microns using HCI RIE using patterned oxide layer 64 as a mask. After removing scratches and dirt caused by the RIE process from the walls of the trench thus formed by wet etching with acid, a protective oxide layer 65 is thermally grown on the walls and bottom of the trench, and LPCV is applied to treat the side walls of the trench.
Deposition of nitride 66 by D is used to protect the oxide layer on the sidewalls to reduce further diffusion during subsequent processing steps. The thickness of the oxide layer 65 is, for example, approximately 200 Å, and the thickness of the nitride layer 66 is, for example, 100 OA. The structure thus obtained is shown in FIG. 3C. Note that this FIG. 30 is similar to the following FIGS. 3D to 3G, but all of them are views showing a cross section along the bit line 20. [0017] 3. Next, the RIE process using HCI is performed again to further dig the trench. In this case, the oxide layer 64 is also slightly eroded, but this layer does not cause any particular problem because the initial deposition thickness of this layer is sufficiently large. When the depth of the trench is finally about 5.0 microns, the trench is cleaned as described above, and
After thermally growing the oxide to form the 100 Å thick insulating layer stack 52 of the capacitor 12, a 75 Å thick nitride is deposited by LPCVD. Thermal oxidation of this nitride layer is carried out to perfect the dielectric properties.
Initial oxide/nitride/oxide layer stack 52
get. The trench thus formed is filled with impurity-implanted polysilicon (region 50) as shown in FIG. 3D. [0018] 4. After planarizing the polysilicon region 50 by, for example, spin coating on photoresist, the surface of the polysilicon region 50 and the inside of the trench 30 are planarized.
Complete plasma etch treatment down to 0OA. In this case, the plasma etch inside the trench is performed from the top of the insulating stack 52 down and over the substrate 32. As will be described later, if the polysilicon region 50 extends slightly below the upper end of the stack 52 and above the potash substrate 32, the upper end position of the polysilicon region 50 does not have to be very precise. See Figure 3E. [0019] 5. Remove exposed portions of stack 52 (in this case, nitride layer 66 is much thicker than stack 52;
In removing exposed portions of stack 52, nitride layer 66 is removed.
are not significantly removed). A diffusion region 48 having a thickness of at least 2000 Å is then formed by vapor phase diffusion of phosphorus (FIG. 3F). In addition, in FIG. 3F, the diffusion region 48 is 2
Although they appear to be formed in places, these regions are part of a single annular region surrounding the trench and forming the source of the transistor 18. However, at this time, the gate oxide layer of this transistor 18 has not yet been formed. [00201 6. After N5 polysilicon is deposited by LPCVD, it is planarized and a plasma etch is performed completely on the plane and immediately below the oxide layer 65 and the oxide layer 66 in the trench. This N polysilicon layer becomes a part of the polysilicon region 50 and increases its thickness.
In the drawing (FIG. 3G), it is indicated by the same reference numeral as the polysilicon region 50. Note that also in this case, the polysilicon region 50
has sufficient overlap with diffusion region 48 to provide good electrical contact therebetween, and oxide layer 66 and nitride layer 65 are fully exposed to ensure that the gate of transistor 18 covers its channel region. If covered,
Although the upper end position of polysilicon region 50 does not have to be very strict, this will also be described later. [0021] 7. Grow a thermal oxide layer 56 on the exposed portions of polysilicon region 50 and diffusion region 48 to a thickness of approximately 1000 Å. In this case, the oxide layer 65 generates a bird's beak at its lower edge, but growth is inhibited by the nitride layer 66 at other locations. This thermal oxide layer 56 is formed to reduce the source/gate parasitic capacitance of the transistor 18, and may be omitted depending on the case. Next, after etching the nitride layer 66, a wet etch is performed to remove the oxide layer 65 (and a portion of the thermal oxide layer 56, which is much thicker than the core layer), thereby removing the channel 44 and diffusion. A portion of region 48 is exposed. This exposed channel 4
4, grow a gate oxide layer 46 to a thickness of 250 nm, (
This increases the thickness of the thermal oxide layer 56) and then N
A polysilicon layer 14 is deposited and patterned to form the word line 14 and to obtain a cell with the cross-sectional structure described in connection with FIG. [0022] Next, a second embodiment of a dRAM according to the present invention (shown as a memory cell 130 in FIG. 4C) and a second embodiment of a fabrication method according to the present invention will be described below with reference to FIGS. 4A to 4D. do. These Figures 4 - Figure 4D are Figures 2 and 3
A-FIG. 3G are also similar cross-sectional views. [0023] 1. After growing a thermal oxide layer 135 with a thickness of 100 OA on a P substrate 132 with a crystal orientation of (100), a thermal oxide layer 135 with a thickness of 1
Micron plasma enhanced CVD oxide layer 137
Deposit. Next, after patterning this oxide layer 137 to form a trench of 1 square micron in cross section,
Using the nuclear layer as a mask, RIE processing using HCI is performed to etch these trenches to a depth of 5 microns. The trench sidewalls are then cleaned, a capacitor oxide layer 152 is thermally grown on the sidewalls and the trench bottom, and a 4 micron arsenic-implanted polysilicon region 150 is then deposited by sputtering (FIG. 4A). [0024] 2. Perform a wet etch process on each of the above oxide layers. This removes the exposed portion of capacitor oxide layer 152 and lifts off the portion of polysilicon region 150 above oxide layer 137. Next, thickness 2
By depositing a 1-2 ohm Cm silicon epitaxial layer 144 of 000A and implanting ions into the core layer,
The N hit line 20, a layer 120 that will become the drain of the transistor 18, and a region 148 that will become the source of the transistor 18 are formed (FIG. 4B). In this case, since the region 148 is formed on the upper surface of the polysilicon region 150, it is naturally expected that the region 148 will have various defects. Since it is an implanted part, such defects do not pose much of a problem. [0025] 3. By performing an annealing treatment, the region 148 is slightly bulged out by promoting diffusion of the implanted impurity. Gate oxide layer 146 is then thermally grown to 250 Å, followed by N 2 polysilicon deposition and patterning to form word line 14 . dRAM that cannot be obtained in this way
The structure of cell 130 is shown in FIG. 4C. [0026] Next, a third embodiment of the dRAM according to the present invention will be described. This third embodiment, designated by the reference numeral 160, is a variant of the dRAM cell 130 described above, and is produced by a third method embodiment, which is a variation of the second embodiment of the method according to the invention, as described above. It is something that will be done. In the following description, the same reference numerals as above indicate corresponding items in the above embodiment. [0027] 1. After performing step (1) of the second embodiment, the oxide layer is etched in step (2). [0028] 2. 2000A thick LPCVD polysilicon layer 144
By implanting impurities into this, N
Form layers 120 and 148. The resulting configuration is equivalent to that of FIG. 4B, except that in this case regions 120, 144, 150 are polysilicon layers rather than shrimp layers as in the second embodiment [0029] 3. The regions 120 and 144 are converted into shrimp layers on the substrate 132 by annealing and solid-phase epitaxy, but as a result, some of the regions 148 and 150 become single crystal. The broken waveform line in FIG. 4D is
This conceptually shows such partial single crystallization. However, among such crystallized regions, only the region 144 () (the channel region of the transistor 18) has an effect on the operating characteristics. Note that the high temperature used in this process causes diffusion of impurity ions, causing the region 148 to bulge as shown in FIG. 4D. [0030] The N-type layer 120 is then patterned and etched to form the bit line 20. [0031] 4. Gate oxide layer 146 is then grown to a thickness of 25 OA, followed by deposition, patterning and etching of N' polysilicon layer 14 to form word line 14.
form. The cross-sectional structure of the dRAM cell 160 thus obtained is shown in FIG. 4E.

[0032] Both of the operations of the dRAM cells 130 and 160 described above are as follows.
The operation is equivalent to that of the cell memory cell 30 described earlier. That is, the drain 20, channel region 144, source 148, and gate 14 of the transistor 18 are all arranged vertically, and one plate of the capacitor 12 is connected to the N region 148/150.
The other plate is each formed by a P 2 substrate 132, and a dielectric layer is formed by an oxide layer 152 and a reverse bias junction between region 148 and substrate 132. [0033] Note that the above step (3) of the method for manufacturing the cell 160 is changed,
The N layer 120 may be patterned and etched after a solid phase epitaxy process is performed to define and implant channel stop regions between the plurality of bit lines 20. The method for forming the channel stop region in this case is the first method according to the present invention.
The method of forming the channel stop 38 between the bit lines 20 in the embodiment shown in FIG. [0034] Various embodiments of the dRAM according to the present invention and embodiments of the manufacturing method thereof have been described above, but these embodiments are based on the above-mentioned dimensions, trench shape, impurity implantation depth, type of substitute material, etc. or using ion diffusion instead of ion implantation, wet etching instead of dry etching, or using a halogen carbon compound instead of HCI in RIE.
Omitting the protective nitride layer 66 and making various other changes will be readily apparent from the foregoing description.

[Brief explanation of drawings]

FIG. 1A and B are a schematic diagram showing an equivalent circuit of a dRAM cell according to the present invention and a plan view showing a cell array using the cell, respectively.

FIG. 2 is a cross-sectional view of a first embodiment of a dRAM cell according to the invention taken along line 2-2 in FIG. IB;

FIGS. 3A to 3G are diagrams showing a series of steps in manufacturing the dRAM cell according to the first example according to the first example of the cell manufacturing method according to the present invention.

4A to 4E are diagrams showing a series of steps when manufacturing dRAM cells according to the second and third embodiments of the cell manufacturing method according to the present invention; be.

[Explanation of symbols]

12 Capacitor 14 Word line 16 Gate 18 Transistor 20 bit line 30.130,160 memory cell 32.132 Board 34.144 Shrimp layer 42 Oxide layer 44 channel 46.146 Gate oxide layer 48 Diffusion area 50.150 Polysilicon area 52.152 Oxide/Nitride/Oxide stack

【Document name】

drawing

[Figure 1]

[Figure 2]

[Figure 3]

[Figure 4] E

Claims (1)

[Claims] 1. A method of forming a memory cell in a semiconductor substrate, comprising: (a) introducing impurities into the surface of the substrate to provide cell address lines and cell transistor drains; (b) in the substrate. (c) forming an insulating layer on the sidewalls; (d) introducing a semiconductor material into the bottom of the trench; and (e) forming a trench in the trench with sidewalls extending through the address line. removing a portion of the insulating layer on the sidewalls overlying the semiconductor material in the trench, and partially insulating an upper portion of the trench adjacent to the semiconductor material in the area where the insulating layer is removed with a conductive material; filling to form the source of the cell transistor, such that the semiconductor material and the conductive material constitute one plate of the cell capacitor and the substrate constitutes the other plate of the cell capacitor, and the address line and forming a conductive gate material over the insulating layer in the trench and beyond the address line to control a transistor channel between the conductive material in the trench, thereby completing a cell capacitor and a transistor; ; A method for producing a memory cell characterized in that it is comprised of;