JP3234010B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a memory cell type dynamic semiconductor memory device in which a plurality of MOS transistors are connected in series.

[0002]

2. Description of the Related Art In recent years, remarkable progress has been made in the integration of DRAM, which is a kind of RAM in LSI memories. DR
As a memory cell structure for further increasing the integration of AM, a so-called stacked capacitor cell in which a capacitor is stacked on a transistor, a so-called trench capacitor cell in which a groove is formed in a silicon substrate and the inner wall thereof is used as a capacitor, and the like. Has been proposed. These stacked and trench capacitor cells are
It has been put to practical use from a 1 Mbit DRAM.

However, the DRAM using the capacitor cell having such a structure has the following problems.

[0004] First, high integration is progressing.
When the degree of integration is about 56 Mbits, in order to increase the storage capacity, in the stacked capacitor cell, it is necessary to take measures such as increasing the height of the storage electrode or making the shape of the storage electrode cylindrical. On the other hand, in the case of a trench capacitor cell, in order to increase the storage capacity, it is necessary to take measures such as reducing the width of the groove and increasing the depth of the groove.
These contrivances for high integration have led to the complication of the manufacturing process, the elongation of the construction period, the reduction of the manufacturing yield, and the occurrence of new problems.

[0005] Second, the DRA in which the degree of integration of the conventional structure is advanced
In the M memory cell, the area of the memory cell is determined by the minimum size of the line and space of the word line and bit line. If it becomes very difficult to reduce the minimum size, further integration becomes difficult. Was.

In order to solve the above-mentioned problem, a new memory cell system, for example, as shown in FIG.
The OS transistor group is connected in series without passing through the element isolation region, and a capacitor C ₁ for storing information is connected to one end of each of the sources or drains of these MOS transistors.
Connect -C _4, by connecting the bit line BL to an output terminal of the MOS transistor connected to said series, a technique for reducing the area of the memory cell has been proposed (JP-A 4-3463). In the drawing, WL1 to WL4 indicate word lines. However, even if such a new memory cell method is adopted, one bit is basically composed of a MOS transistor and a capacitor. However, there remains a problem of how to realize a large storage capacity with a small area memory cell.

In the case of the above-mentioned memory cell system, since the word lines are formed at a pitch close to the minimum line and space dimensions, a stacked capacitor cell is more suitable than a trench capacitor cell. A DRAM cell structure using such a stacked capacitor cell has been proposed. In the figure, 117 indicates a word line (gate electrode), on which a capacitor is projected. The capacitor is formed on the silicon substrate 101 divided by the field insulating film 104, and the plate electrode 123 and the capacitor insulating film 1 are formed.
22 and a capacitor base electrode layer (storage electrode) 121. On the other hand, the MOS transistor includes a gate insulating film 116, a gate electrode 117, and a source / drain diffusion layer 118.
Bit line 1 through a contact hole opened in
25 is connected to the source / drain diffusion layer 118.

However, the DR constructed as described above
In AM, if an attempt is made to realize a sufficient storage capacity with a memory cell having a small area, the structure of the storage electrode 121 becomes complicated, the height of the storage electrode 121 becomes, for example, about 1 μm, and after the entire surface is flattened. There is a problem that the contact hole becomes too deep and the manufacturing process becomes very difficult.

[0009]

As described above, the conventional D
The RAM cell has a problem that the manufacturing process becomes complicated at the time of high integration and the manufacturing yield is significantly reduced. Further, the area of the memory cell is determined by the minimum dimensions of the lines and spaces of word lines and bit lines, and there is a problem that further integration is difficult unless the minimum dimensions are reduced. In order to solve such a problem, a new type of memory cell has been proposed. In this case, however, since one bit is basically composed of a MOS transistor and a capacitor, However, there remains a problem as to whether a large storage capacity can be realized with the memory cell.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device capable of obtaining a large storage capacity with a small area memory cell.

A dynamic semiconductor memory device according to the present invention.
The device comprises a semiconductor substrate and a plurality of substrates formed on the semiconductor substrate.
And a dynamic cell composed of memory cells
A dynamic semiconductor memory device comprising:
The memory cell has a gate connected to the word line and one source
MOS transistor with drain and drain connected to bit line
And the other source drain of this MOS transistor
Embedded storage electrode electrically connected to
And a capacitor on the storage electrode.
The gate of each of the two MOS transistors adjacent to
The electrode is characterized in that a part of the electrode extends insulated .

[0012]

[0013]

[0014]

According to the semiconductor memory device of the present invention,
The gate electrode of at least one MOS transistor is
It extends over the storage electrodes of two adjacent trench capacitors.

That is, the capacitor and the MOS transistor are not completely formed in different regions, but the peripheral portion of the groove of the capacitor extends to the region where the MOS transistor is formed. Becomes larger.

Therefore, since the storage capacity can be increased without increasing the depth of the trench or increasing the area of the memory cell, the step between the memory cell section and the peripheral circuit section, which is a problem in the stack type memory cell, the so-called element step. Can be reduced, noise-resistant, and stable operation can be ensured.

Further, since the source / drain region and the storage electrode are directly connected, miniaturization is easier than in the conventional case where the source / drain region and the storage electrode are connected via a connection portion. And MO connected in series
The series resistance of the source and drain of the S transistor can be reduced.

[0018]

[0019]

Embodiments will be described below with reference to the drawings.

FIG. 1 is a plan view of a DRAM cell using a trench type memory cell according to a first embodiment of the present invention. FIGS. 2 (a), 2 (b), and 2 (c) are plan views. FIG. 2 is a sectional view taken along the lines AA ′, BB ′, and CC ′ of the DRAM cell of FIG. 1, respectively.

The DRAM cell of this embodiment employs the series connection type memory cell system shown in FIG. An N-well layer 2 and a P-well layer 3 are sequentially provided on a silicon substrate 1. A stripe-shaped element region is formed of the insulating film 4 in the three P-well layers in the memory cell region, and deep trenches 9 ₁ and 9 are formed in the capacitor formation region of the element region.
₂ , 9, ₃ and 9 ₄ (hereinafter, the reference number may be simply referred to as 9) are formed. Each trench 9 is formed so as to divide the element region, and an oxide film 8 having a thickness of about 50 nm is formed on the inner wall surface above the trench 9 (about 2 μm). Generation is suppressed.

The P well layer 3 is formed at a depth not exceeding the region of the oxide film 8. Two of the four side surfaces of the trench 9 are separated from other layers by the shallow trench isolation insulating film 4 having a depth of about 500 nm, for example, and the remaining two
The side surface is separated from other layers by the oxide film layer 8 on the upper inner wall of the trench 9. Further, a capacitor insulating film 10 made of an NO film or the like is formed on the inner wall of the trench 9, and polysilicon containing impurities as the lower storage electrode 11 is buried in the trench 9 via the capacitor insulating film 10. ing.

An upper storage electrode 13 made of polysilicon electrically connected to the lower storage electrode 11 is provided above the trench 9 and in the vicinity thereof.
A source / drain diffused layer 15 is provided on the side of 3. This source / drain diffusion layer 15 is formed in a self-aligned manner by introducing impurities such as arsenic in the upper storage electrode 13 into the P well layer 3 by thermal diffusion, as described later.

The gate electrode 17 of the MOS transistor is
A word line (not shown), at least one side of which extends above the trench 9 via the oxide film 14. Also,
The source / drain layer 18 on the bit line 20 side is formed in a self-aligned manner using the gate electrode 17 as a mask.

That is, the MOS transistor group of the DRAM cell of this embodiment includes a MOS transistor whose channel length is determined by the distance between two source / drain diffusion layers 15 formed by thermal diffusion of impurities from the upper storage electrode 13. ,
Source / drain diffusion layer 15 having a channel length formed by thermal diffusion of impurities from upper storage electrode 13 and source / drain formed in a self-aligned manner using gate electrode 17 as a mask.
The MOS transistor has an asymmetrical source / drain structure determined by the distance between the drain diffusion layer 18 and the MOS transistor.

The capacitor of the DRAM cell according to the present invention comprises storage electrodes 11 and 13 made of polysilicon buried in trench 9, capacitor insulating film 10, and N well layer 2 as a plate electrode. This is a so-called substrate plate electrode system.

According to the DRAM cell configured as described above, first, since a part of the gate electrode 17 extends above the trench 9, a trench capacitor can be formed in a part of the gate electrode region. Therefore, the opening diameter of the trench 9 can be increased without increasing the depth of the trench 9 for the storage capacitor. In other words, the storage capacity can be increased without increasing the step of the element or the area of the memory cell.

Second, the source / drain diffusion layers 15
Since it is formed in a self-aligned manner with the upper storage electrode 13 due to thermal diffusion of impurities, a region for connecting a capacitor and a transistor is not required unlike the related art. For this reason, it becomes possible to arrange the trench region and the transistor region sufficiently close to each other.

According to the first and second features described above, a large storage capacitance can be obtained with a small cell area without increasing a device step. In particular, as in this embodiment,
In the case of a new series-connected memory cell system, the upper storage electrode 13 also serves as a charge transfer region to the source / drain diffusion layer of the next-stage MOS transistor, so that a very large effect in reducing the series resistance of the source and drain. There is.

Next, a description will be given of a manufacturing process of the DRAM cell constructed as described above. FIG. 3, FIG. 5, FIG. 7, FIG.
FIG. 4 is a plan view showing a manufacturing process of the DRAM cell of the present embodiment. FIGS. 4, 6, 8, and 10 show FIGS.
AA ′ cross-sectional view, BB ′ cross-sectional view and CC ′ cross-sectional view of FIGS. 5, 7, and 9 are shown.

First, as shown in FIGS. 3 and 4, a P-type silicon substrate 1 having an impurity concentration of about 5 × 10 ¹⁵ cm ^-3 and a main surface of (100) is prepared. For example, 5 × 10 ¹⁷ cm ^{−3 in} a region having a depth of about 2 to 8 μm.
N-well layer 2 having an impurity concentration of about
It is formed using a class ion implantation apparatus or the like. This N
Since the well layer 2 serves as a plate electrode, the well layer 2 is extracted from a desired location at the end of the memory cell array as an electrode.

Since the impurity concentration is slightly too low, arsenic or the like is diffused from, for example, an AsSG film or the like into only the region in contact with the N-well layer 2 on the side wall surface of the trench 9 to obtain, for example, 1 × 10 ¹⁹ cm ^−3. A high concentration layer (not shown) may be formed. Alternatively, the same high-concentration layer and a P-well layer 3 described later may be formed using an N-well layer and a P-type epitaxial Si layer.

Next, a P-well layer 3 is formed on a desired surface of the cell array of the silicon substrate 1, for example, at a depth of about 1.5 μm. Next, after a shallow trench (for example, about 0.4 μm in depth) is dug in a desired element isolation region by using, for example, RIE, the insulating film 4 such as a SiO ₂ film is subjected to a flattening method such as an etch-back method or a polishing method. And buried. This is an example of a so-called trench isolation method. Alternatively, the field oxide film 4 having a thickness of about 400 nm may be formed by a so-called LOCOS method using a Si ₃ N ₄ film. Although not shown here, an impurity layer for preventing field inversion may be formed at the bottom of the shallow trench.

Thereafter, the surface of the silicon substrate 1 in the element region is exposed, and subsequently, the buffer SiO ₂ film 5 and the Si
_{A 3} N ₄ film 6 and a mask SiO ₂ film 7 are sequentially formed. Each film thickness is, for example, 10 nm, 100 nm, 50
It is about 0 nm.

Next, after forming a trench opening pattern / resist mask (not shown) by a usual lithography process, the mask SiO ₂ film 7, Si ₃ N ₄ film 6, and buffer SiO ₂ film 5 are sequentially formed by RIE or the like. To form a hole having a trench diameter of, for example, 0.4 μm. Next, after removing the trench opening pattern / resist mask, the silicon substrate 1 is etched by RIE using the mask SiO ₂ film 7 as a mask to form a shallow trench deeper than the P well layer 3, for example, having a depth of about 2 μm. .

Next, after cleaning the inner wall of the shallow trench, the inner wall of the shallow trench is coated with a film having a thickness of, for example, 50 nm.
An SiO ₂ film 8 of about nm is formed. Then after selectively removing the SiO ₂ film 8 of a shallow trench bottom by RIE, the mask SiO ₂ film 7 and the SiO inner walls of the trenches ₂
Using the film 8 as a mask, the deep trenches 9 ₁ , 9 ₂ , 9 ₃ , 9
₄ is formed, for example, by further RIE of the silicon substrate 1 by about 4 μm. As the cleaning treatment of the inner wall of the trench 9 after the RIE, the silicon surface is slightly etched with a wet liquid containing an alkaline liquid or the like, the silicon surface is thermally oxidized to remove the oxide film, or the silicon film is removed in an N ₂ atmosphere. Although there are methods such as high-temperature annealing, they may be performed in an appropriate combination.

Next, as shown in FIGS. 5 and 6, a capacitor insulating film 10 is formed on the inner wall surface of the trench 9 having been subjected to the cleaning process.
, A polysilicon layer 11 doped with an impurity such as arsenic to be the lower storage electrode 11 is deposited on the entire surface. As a material of the lower storage electrode 11, amorphous silicon may be used instead of polysilicon.

Hereinafter, as the capacitor insulating film 10, NO
The case where a film is used will be described, but another insulating film, for example, a high dielectric film such as a Ta ₂ O ₅ film may be used.

First, the natural oxide film on the surface of the silicon substrate in the region in contact with the N-well layer 2 in the trench 9 is removed with silane gas or the like. Then, for example, at a high temperature (8
After an Si ₃ N ₄ film of the ammonia gas (e.g. a thickness of about 1nm to the silicon surface by flowing NH ₃₎ remains about 50 ° C.), the entire surface of about good coverage thickness 5 nm the Si ₃ N ₄ film Then, the surface of the Si ₃ N ₄ film is deposited at a temperature of, for example, 800 ° C. and about 10% HCl for about 60 hours.
The NO film is formed by oxidizing the surface of the Si ₃ N ₄ film for about a minute to form a SiO ₂ film having a thickness of about 2 nm.

Thereafter, using a so-called chemical mechanical polishing (hereinafter, referred to as polishing) method for chemically and mechanically polishing the entire surface of the wafer, polysilicon or amorphous silicon to be the lower storage electrode 11 is used.
The capacitor insulating film 10 and the mask SiO ₂ film 7 are continuously polished, and the polishing is stopped by the Si ₃ N ₄ film 6. For this, a polishing condition (adjusting a polishing agent, a load, and the like) is selected so that the etching speeds of the Si ₃ N ₄ film and the SiO ₂ film are different.

Next, only the polysilicon layer 11 is etched by RIE, and the polysilicon layer 11 is
The polysilicon layer 11 is completely buried in the trench 9 by etching about 0 nm. At this time, it is important that the depth of the SiO ₂ film 8 on the upper side surface of the trench 9 can be etched in a later step.

Next, as shown in FIGS. 7 and 8, after forming a side wall contact pattern for etching a part of the SiO ₂ film 8 on the upper side wall of the trench 9 using a photoresist, the resist film 12 is used. This resist film 12, S
Using the i ₃ N ₄ film 6 and the polysilicon layer 11 as an etching mask, the NO film 10 and the Si
A part of the O ₂ film 8 is etched to expose a part of the upper part of the P well layer 3. At this time, since the oxide film 8 is also etched, the etching amount is controlled so that the oxide film 8 is not much etched.

Next, as shown in FIGS. 9 and 10, after removing the resist film 12, the exposed natural oxide film on the surface of the silicon substrate 1 is removed. Next, the arsenic-doped polysilicon layer 13 serving as the upper storage electrode 13 is formed with a
A polysilicon layer 13 is buried in the upper portion of the trench 9 and in the periphery of the trench 9 by depositing over the entire surface of about 0 nm and polishing the entire surface again. Again, S
The i ₃ N ₄ film 6 is used as a stopper layer. Also, instead of polysilicon, as a material of the upper storage electrode 13,
Amorphous silicon may be used.

Next, heat is applied to the exposed surface of the polysilicon layer 13 (here, only the surface of the polysilicon layer 13 in the region of the trench 9 is exposed, and the others are covered with the Si ₃ N ₄ film 6). After forming an oxide film (not shown) of, for example, about 30 nm, the thermal oxide film is used as a mask to form a surface layer of Si ₃ N _4.
The film 6 is selectively removed using, for example, a so-called hot phosphoric acid solution obtained by heating a phosphoric acid solution. Arsenic thermally diffuses from the polysilicon layer 13 in contact with the Si surface exposed by the heat step during this time or the subsequent high-temperature heat step to the silicon substrate side,
An N-type diffusion layer 15 is formed. The diffusion length of the diffusion layer 15 toward the silicon substrate can be controlled by the temperature and time of the thermal process.

Next, after removing the buffer SiO ₂ film 5 on the surface of the silicon substrate 1 in the element region to expose the surface of the silicon substrate 1, the exposed portion is oxidized to, for example, a thickness of 10 n.
A gate insulating film (SiO ₂ film) 16 of about m is formed.
At this time, the surface of the polysilicon layer 13, made of a SiO ₂ film formed with the residual film and formation of the gate insulating film 16 of the previous thermal oxide film, for example 30nm about SiO ₂
A film 14 will be formed. The gate insulating film 1
Before film formation 6, so-called channel ion implantation is performed for adjusting the threshold voltages of the n-channel transistor in the memory cell portion and the n-channel and p-channel transistors in the peripheral circuit portion.

Next, a polysilicon layer 17 having a thickness of, for example, about 200 nm doped with an impurity such as phosphorus, which becomes the gate electrode 17, is deposited on the entire surface, and a desired photolithography method and an RIE method are used. The polysilicon layer 17 is processed into a gate electrode shape.

At this time, the gate electrode 17 is formed so as to partially cover the trench 9. That is, when the trenches 9 are provided on both sides of the region to be the gate electrode 17, a part of the gate electrode 17 is formed on the trenches 9 on both sides and formed on one side of the region to be the gate electrode 17. When there is only the trench 9, the gate electrode 17 is formed so that a part of the gate electrode 17 runs only on the trench 9 on one side.

Next, ion implantation of impurities such as arsenic is performed by using the gate electrode 17 as a mask to form source / drain diffusion layers 18. MOS transistors having the source / drain diffusion layers 18 formed in this manner can be classified into those having two types of source / drain structures in the memory cell portion.

In other words, one is that the two source / drain diffusion layers 18 are both the polysilicon i layer 1 above the trench 9.
MOS transistor formed by thermal diffusion of impurities from the third, and one of the two source / drain diffusion layers is one in which the source / drain diffusion layer 13 is the thermal diffusion of the impurity from the polysilicon layer 13 above the trench. And the other source / drain diffusion layer 18 is a MOS transistor formed by an ion implantation method using a normal gate electrode as a mask.

In particular, the polysilicon layer 1 above the trench 9
In the MOS transistor in which the source / drain diffusion layer 15 is formed by thermal diffusion from 3, the depth of the source / drain diffusion layer 15 can be reduced, and the actual channel length is not determined by the gate length. And the diffusion length from the polysilicon 13, so that the effective channel length can be increased.

The reason why such a feature is obtained is that, unlike the conventional DRAM cell, the connection part for electrically connecting the capacitor part and the transistor part is unnecessary in the embodiment. That is, since the DRAM cell of the present embodiment has a structure in which the trench capacitor portion enters into a part below the gate electrode 17, the trench opening diameter can be made larger than that of the conventional DRAM cell.
This means that the memory cell area can be reduced to achieve the same storage capacity, and conversely, the trench depth can be reduced if the memory cell area is the same.

Next, B, for example, having a thickness of about 500 nm is formed on the entire surface.
After depositing an interlayer insulating film 19 such as a PSG film, for example,
Melting is performed at about 850 ° C., and the surface is gently flattened.
0 is arranged. As a material of the bit line 20, a silicide laminated film such as silicon and WSi ₂ is used.
In addition to a so-called polysilicide film, a metal material such as W may be used.

Finally, after an interlayer insulating film 21 such as a BPSG film is deposited on the entire surface to flatten the surface, contact holes are opened in each electrode, and a metal wiring (not shown) such as aluminum is formed. The DRAM shown in FIGS. 1 and 2 is completed.

Thus, according to the present embodiment, since a part of the gate electrode 17 of the MOS transistor extends above the trench 9, the opening diameter of the trench 9 can be increased without increasing the depth of the trench 9. . Therefore, a large storage capacitance can be obtained without increasing the element step and the area of the memory cell.

Further, according to the present embodiment, the upper storage electrode 1
Since the source / drain diffusion layers 15 are formed in a self-aligned manner by introducing the impurities in 1 into the P well layer 3 by thermal diffusion, unlike the conventional DRAM cell,
A special connecting portion for connecting the capacitor portion and the transistor portion is not required, and the trench region and the transistor region can be arranged closer to each other. Therefore, a large storage capacity can be obtained in a small-sized memory cell without increasing the device step. In particular, in the case of a new series-connected memory cell system, the storage electrode is connected to the next stage (the next MOS
Transistor), and if the storage electrode is directly connected to the source / drain diffusion layer without passing through the connection portion as in the present embodiment, the series resistance of the source / drain diffusion layer can be sufficiently increased. Can be smaller.

Further, in this embodiment, since the N-well layer 2 formed on the silicon substrate 1 is used as the plate electrode, the plate electrode does not protrude onto the silicon substrate 1,
A DRAM excellent in the flatness of the element surface can be obtained.

Further, the channel length of the MOS transistor is not determined by the processing size of the gate electrode 17 and is not determined by the trench 9.
The distance between the source / drain diffusion layers 15 formed by the thermal diffusion of the impurities from the upper side wall of the source and the source / drain diffusion layers 15 and the gate electrode 17 formed by the thermal diffusion of the impurities from the upper side wall of the torrent 9 Since it is determined by the distance between the source and drain diffusion layers 18 formed in a self-aligned manner by masking, it is possible to prevent variations in threshold voltage due to dimensional variations when processing the gate electrode.

By the effects of the present embodiment described above, it is possible to greatly increase the degree of integration, simplify the process, and improve the performance.

Next, a DRAM according to a second embodiment of the present invention.
The cell will be described. FIG. 11 shows a DRAM of this embodiment.
11A is a diagram showing a configuration of a cell, FIG. 11A is a plan view, and FIG. 11A is a cross-sectional view taken along line AA ′ of the DRAM cell in FIG.

The DR referred to in the following description of the embodiment will be described.
In the figure of the AM cell, portions corresponding to those of the DRAM cell of FIGS. 1 and 2 are denoted by the same reference numerals as in FIGS. 1 and 2, and detailed description is omitted.

The DRAM cell of this embodiment is an example in which the present invention is applied not to a direct connection type DRAM but to a conventional DRAM (for 2 bits).

Each bit memory cell is composed of a MOS transistor and a trench capacitor, and is provided with a passing word line (gate electrode 17 ₂ ).

[0063] That is, in the gate electrode of the MOS transistor of each memory cell, the gate electrode 17 _1, 7 ₃ has one end extending so as to partially overlap on the trench 9, the other end (the bit line contact side) Has the same structure as a normal planar gate electrode. Gate electrodes 17 _1, 7 channel length of MOS transistors having _3, the source-drain diffusion layer formed by diffusion of impurities from the top of the polysilicon layer 13 of the trench 9 15 and the gate electrode 1
7 _1, 17 ₃ determined by the distance between the source and drain diffusion layer 18 formed in the mask, not determined by the gate length of the gate electrodes 17 _1, 17 _3.

Therefore, the trench 9 and the gate electrode 1
7 _1, 17 is ₃ by misalignment between seem channel length varies, such a problem does not occur because the alignment accuracy of recent exposure apparatus is remarkably improved.
Rather, a connecting portion for connecting the storage electrode 13 in the trench 9 and the source / drain diffusion layer 15 becomes unnecessary,
It is important to reduce the cell area in order to realize a high-density DRAM.

Since the memory cell of this embodiment has a structure in which a part of the region below the gate electrode is used as a region for forming a trench capacitor, as in the first embodiment, And the storage capacity can be increased without increasing the element step and the area of the memory cell.

Next, a DRAM according to a third embodiment of the present invention
The cell will be described with reference to FIG.

The difference between the DRAM cell of the present embodiment and that of the first embodiment is that the opening diameter of the trench 9 is larger.

In the case of the first embodiment, as described above, the oxide film (SiO 2) formed on the upper side wall of the shallow trench is used.
_{The two} films ₂ ) 8 have two roles. One is to suppress the generation of leakage current on the side wall of the shallow trench, and the other is
One is a role as a mask when the deep trench 9 is formed. For this reason, the opening diameter of the deep trench 9 is reduced by the thickness of the oxide film 8, which is not desirable for increasing the storage capacity.

In this embodiment, in order to improve such a defect, first, the trench 9 is formed, and then the trench 9 is formed.
(SiO ₂ film) 31 having a thickness of, for example, 5
The thickness is about 0 nm. Next, after the polysilicon layer 32 is buried as the lower storage electrode 32 in the trench 9,
Similarly to the first embodiment, the polysilicon layer 33 serving as the upper storage electrode 33 (this is the polysilicon layer 1 of the first embodiment)
3), and impurities are diffused from the polysilicon layer 33 to the silicon substrate side to form the source / drain diffusion layers 15. This embodiment is an application of that spirit in which a portion under the gate electrode 17 _1, 17 ₃ to form a trench capacitor to increase the trench opening diameter of the present invention.

By the above-described process, the opening diameter of the trench 9 can be made larger than that of the first embodiment, and a trench capacitor having a larger storage capacity can be obtained.

Next, a DRAM according to a fourth embodiment of the present invention.
The cell will be described. FIG. 13 shows a DRAM of this embodiment.
FIG. 14A, FIG. 14B, and FIG. 14C are plan views of the cell, respectively, taken along line AA of the DRAM cell of FIG.
'A sectional view, a BB' sectional view, and a CC 'sectional view are shown.

The DRAM cell of this embodiment differs from that of the first embodiment in that, instead of forming a trench capacitor after performing element isolation, a device molecule is formed after forming a trench capacitor. .

That is, after the trench 9 is formed, the polysilicon layers 11 and 13 to be the storage electrodes 11 and 13 are sequentially deposited on the entire surface, and then the polysilicon layer 11 and
A shallow trench is formed by an etching step of embedding 13, and an insulating film 41 for element isolation is embedded in the shallow trench. The storage capacity of the trench capacitor is the same as in the first embodiment and does not increase.

The first process can be performed by such a process change.
In this embodiment, the element isolation is performed after the formation of the trench capacitor, so that the insulating film 41 does not decrease due to the etching during the formation of the trench capacitor. , MO in FIG.
As compared to the S transistor, the corner (corner) 51 at the element isolation end of the MOS transistor is less exposed, and a parasitic channel is less likely to occur.

The present invention is not limited to the embodiment described above. For example, in the above embodiment, the case where all the memory cell array units are n-channel MOS transistors has been described.
Even when an OS transistor is used, a memory cell having the same effect can be obtained by changing the conductivity type of the impurity, the well layer, and the substrate.

In the above embodiment, the mutual relationship between a plurality of memory cells adjacent in the word line direction has not been mentioned. However, in the case of the folded bit line system, the passing word line passes over the trench. Will be. Also,
The present invention can be applied to an open bit line type DRAM.

Further, in the form of electrical connection between the polysilicon layers or between the polysilicon layer and the silicon substrate, not only the natural oxide film at the interface is removed with a hydrofluoric acid (HF) -based solution, but also, for example, Silane (SiH ₄ ) gas is heated to a high temperature (8
After flowing at about 50 ° C. to remove the natural oxide film by silane reduction, normal polysilicon deposition conditions (vacuum degree of 0.1 mm).
Polysilicon may be deposited under higher vacuum deposition conditions (for example, about 0.02 Torr). By doing so, the polysilicon layer at the interface with the silicon substrate becomes a layer close to the epitaxial silicon layer,
The uniformity of the interface is significantly improved, the uniformity of the diffusion length of the impurity diffusion from the polysilicon layer is stabilized, and the product yield is significantly improved.

Further, a silicide layer (Ti
Si ₂ , PtSi ₂ , WSi _2, etc.) may be formed to reduce the resistance. Further, in the present embodiment, the gate electrode extending to above the upper storage electrode is formed. However, similar effects can be expected by forming a gate electrode extending only to above the source / drain diffusion layers. .

In addition, various modifications can be made without departing from the spirit of the present invention.

[0080]

As described in detail above, according to the present invention, the storage capacitance can be increased without increasing the depth of the trench or the memory cell, so that the element step is small, noise-resistant, and stable. DRAM that can ensure optimized operation
Is obtained. In addition, since the source / drain region and the storage electrode are directly connected, miniaturization becomes easy, and
The series resistance of the source / drain of a plurality of MOS transistors connected in series can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view of a DRAM cell according to a first embodiment of the present invention.

FIG. 2 is a sectional view of the DRAM cell of FIG. 1;

FIG. 3 is a plan view showing the first half of the manufacturing process of the DRAM cell according to the first embodiment of the present invention.

FIG. 4 is a sectional view of the DRAM cell of FIG. 3;

FIG. 5 is a plan view showing the first half of the manufacturing process of the DRAM cell according to the first embodiment of the present invention.

FIG. 6 is a sectional view of the DRAM cell of FIG. 5;

FIG. 7 is a plan view showing the latter half of the manufacturing process of the DRAM cell according to the first embodiment of the present invention.

FIG. 8 is a sectional view of the DRAM cell of FIG. 7;

FIG. 9 is a plan view showing the latter half of the manufacturing process of the DRAM cell according to the first embodiment of the present invention.

FIG. 10 is a sectional view of the DRAM cell of FIG. 9;

FIG. 11 is a diagram showing a configuration of a DRAM cell according to a second embodiment of the present invention.

FIG. 12 is a diagram showing a configuration of a DRAM cell according to a third embodiment of the present invention.

FIG. 13 is a plan view of a DRAM cell according to a fourth embodiment of the present invention.

FIG. 14 is a sectional view of the DRAM cell of FIG. 13;

FIG. 15 is a diagram showing a configuration of a memory cell system proposed to reduce the area of a memory cell.

FIG. 16 shows a DRA using a conventional stacked memory cell.
FIG. 4 is a sectional view of an element of an M cell.

[Explanation of symbols]

1. Silicon substrate, 2. N-well layer (plate electrode),
3 ... P well layer, 4,41 ... insulating film (for element isolation)
8, 14 ... oxide film (SiO _2), 9 ... trench, 10 ...
Capacitor insulating film, 11: lower storage electrode, 13: upper storage electrode, 15: source / drain diffusion layer (on the upper wall of the trench), 16: gate insulating film, 17: gate electrode, 18
... source / drain diffusion layers (on the bit line contact side), 19, 21 ... interlayer insulating films, 20 ... bit lines.

Continuation of front page (56) References JP-A-4-212451 (JP, A) JP-A-4-252071 (JP, A) JP-A-2-62073 (JP, A) JP-A-2-172219 (JP) JP-A-3-102869 (JP, A) JP-A-63-258060 (JP, A) JP-A-3-36762 (JP, A) JP-A-3-227563 (JP, A) 4-3463 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8242 H01L 21/822 H01L 27/04 H01L 27/108

Claims (5)

(57) [Claims] A semiconductor substrate formed on the semiconductor substrate;
Dynamic cells composed of multiple memory cells
Dynamic semiconductor memory device comprising
The memory cell has a gate connected to a word line,
MOS transistors whose source and drain are connected to bit lines
The source of the transistor and the other source of this MOS transistor
Embedded storage electrode electrically connected to the rain
Consisting of a wrench capacitor and on the storage electrode
Each of the two MOS transistors adjacent to it
Characterized in that part of the gate electrode extends insulated
Dynamic type semiconductor memory device. 2. The storage electrode according to claim 1, wherein the storage electrode has an upper side wall.
It is characterized by being in direct contact with the other source / drain
2. The dynamic semiconductor memory device according to claim 1, wherein: 3. The one source / drain and the other
Arranged on the semiconductor substrate so as to include the source and drain of
And a half having a depth smaller than the depth of the trench.
A conductor well region, and the train in the semiconductor substrate.
And surrounding the trench, the trench being deeper than the semiconductor well.
A further insulating film shallower than
The dynamic semiconductor memory device according to claim 1. 4. The storage electrode has an upper side below the storage electrode.
In the channel length direction of the MOS transistor
2. The dyna according to claim 1, wherein the dimensions are large.
Mick type semiconductor storage device. 5. The dynamic type cell according to claim 1, wherein the dynamic type cell is of a series connection type.
5. The method according to claim 1, wherein
2. The dynamic semiconductor memory device according to claim 1.