[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPS6232631A - Integrated circuit package - Google Patents

Integrated circuit package

Info

Publication number
JPS6232631A
JPS6232631A JP60171068A JP17106885A JPS6232631A JP S6232631 A JPS6232631 A JP S6232631A JP 60171068 A JP60171068 A JP 60171068A JP 17106885 A JP17106885 A JP 17106885A JP S6232631 A JPS6232631 A JP S6232631A
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit package
glass
thermal expansion
silicon carbide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60171068A
Other languages
Japanese (ja)
Other versions
JPH0431187B2 (en
Inventor
Masatoshi Tsuchiya
土屋 正利
Satoru Ogiwara
荻原 覚
Hiromi Kozobara
楮原 広美
Kanji Otsuka
寛治 大塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60171068A priority Critical patent/JPS6232631A/en
Priority to US06/890,533 priority patent/US4729010A/en
Priority to EP86305894A priority patent/EP0211618B1/en
Priority to DE8686305894T priority patent/DE3672709D1/en
Publication of JPS6232631A publication Critical patent/JPS6232631A/en
Publication of JPH0431187B2 publication Critical patent/JPH0431187B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Heat Treatment Of Steel (AREA)

Abstract

PURPOSE:To enhance reliability in preventing cracks in a glass layer, by forming a lead piece with an iron alloy, which includes nickel and cobalt and has martensite transformation temperature of less than -55 deg.C. CONSTITUTION:A chamber is formed by a ceramic insulating substrate 4 including silicon carbide, a cap 5 and a sealing glass 6 in an airtight manner. A semiconductor element 1 is mounted on the substrate. The end parts of lead pieces 3 are introduced from the outside. Wires 2 electrically connect the lead pieces and the element 1. Those parts are contained in an integrated circuit package. The lead piece 3 comprises an iron alloy, which includes nickel and cobalt and has martensite transformation temperature of less than -55 deg.C. Out of the iron alloys, the alloy, in which the amount of Ni is 29-31wt% and the amount of Co is 12.5-15wt%, especially has the thermal expansion coefficient that is approximate to the thermal expansion coefficient of glass, therefore said ally is most suitable for the material of the lead piece 3.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、炭化けい素質セラミックスよりなる絶縁基板
上に半導体素子を有し1周囲をキャップで気密に覆って
いる構造の集積回路パッケージに係り、特に基板とキャ
ップをガラス封止する構造の集積回路パッケージに関す
る。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an integrated circuit package having a structure in which a semiconductor element is mounted on an insulating substrate made of silicon carbide ceramic and one periphery is hermetically covered with a cap. In particular, the present invention relates to an integrated circuit package having a structure in which a substrate and a cap are sealed with glass.

本発明は、電子計算機に使用するのに好適である。The present invention is suitable for use in electronic computers.

〔発明の背景〕[Background of the invention]

セラミックス絶縁基板、キャップおよび封止用ガラスに
よって気密に囲われた小室内に、半導体素子と、室外か
ら導入されたリード片の端部、および半導体素子とリー
ド片とを電気的に接続したワイヤを収容してなる集積回
路パッケージが知られている。たとえば特開昭5!ll
−134852号公報には。
The semiconductor element, the end of the lead piece introduced from outside, and the wire electrically connecting the semiconductor element and the lead piece are placed in a small chamber airtightly surrounded by a ceramic insulating substrate, a cap, and a sealing glass. Integrated circuit packages are known. For example, Tokukai Showa 5! ll
-134852 publication.

絶縁基板として従前のアルミナ焼結体に代えて炭化けい
素質セラミックスを使用した例が示されている。
An example is shown in which silicon carbide ceramics are used as the insulating substrate in place of the conventional alumina sintered body.

かかる集積回路パッケージにおいては、該公報にも記載
(第2頁右下$117行〜第3頁左上欄第2行)されて
いるように、基板とキャップとを封止するガラス層に亀
裂が生じやすい。
In such an integrated circuit package, as described in the publication (page 2, lower right, line 117 to page 3, upper left column, line 2), cracks occur in the glass layer that seals the substrate and the cap. Easy to occur.

ガラス層の亀裂を防止するために、該公報では炭化けい
素質セラミックス絶縁基板に近似した熱膨張係数を有す
るセラミックスによりキャップを構成することが記載さ
れている。
In order to prevent cracks in the glass layer, the publication describes that the cap is made of ceramic having a coefficient of thermal expansion similar to that of the silicon carbide ceramic insulating substrate.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、ガラス層の亀裂防止に対する信頼性が
より高い集積回路パッケージを提供することにある。
An object of the present invention is to provide an integrated circuit package that is more reliable in preventing cracks in the glass layer.

〔発明の概要〕[Summary of the invention]

本発明は、炭化けい素質セラミックス絶縁基板を有する
集積回路パッケージにおいて、リード片を、ニッケルと
コバルトを含み且つマルテンサイト変態温度が一55℃
以下の鉄合金により構成することにある。
The present invention provides an integrated circuit package having a silicon carbide-based ceramic insulating substrate, in which lead pieces contain nickel and cobalt and have a martensitic transformation temperature of 155°C.
It is composed of the following iron alloys.

本発明者らは、炭化けい素質セラミックス絶縁基板を有
する集積回路パッケージにおけるガラス層の亀裂の一原
因が、ガラス封止処理後の冷却過程、或はパッケージ製
作後に冷熱サイクルを与えて行う寿命試験によりガラス
層が熱応力を受けることにあることを究明した。
The present inventors have determined that one of the causes of cracks in the glass layer in integrated circuit packages having silicon carbide-based ceramic insulating substrates is due to the cooling process after glass sealing treatment or the life test performed by applying a cooling/heating cycle after package fabrication. It was determined that the glass layer was subjected to thermal stress.

そして、ガラス層に熱応力を与えないためには、リード
片の材料の熱膨張、収縮をガラスの熱膨張、収縮とほぼ
同じにすればよいとの結論に達し1本+S 発明の到達した。
Then, in order to avoid applying thermal stress to the glass layer, it was concluded that the thermal expansion and contraction of the material of the lead piece should be approximately the same as the thermal expansion and contraction of the glass, leading to the invention of 1+S.

本発明の効果は、冷熱サイクルによる寿命試験によって
十分に実証され、ガラス層の亀裂のない信頼性の高い集
積回路パッケージを得ることができた。
The effects of the present invention were fully demonstrated by a life test using thermal cycles, and it was possible to obtain a highly reliable integrated circuit package with no cracks in the glass layer.

本発明は、特開昭59−134852号公報に記載の発
明に対して適用するとより一層効果的である。
The present invention is even more effective when applied to the invention described in JP-A-59-134852.

(イ) リード片の構成; 本発明におけるリード片は、相転移温度具体的にはマル
テンサイト変態温度が一55℃以下をもつ材料で構成さ
れる。集積回路パッケージの冷熱サイクル寿命試験は、
一般に一55℃と+150℃の間でくり返されるので、
−55℃以下の相転移温度を有することが必要である。
(a) Structure of lead piece; The lead piece in the present invention is made of a material having a phase transition temperature, specifically, a martensitic transformation temperature of 155°C or less. The thermal cycle life test of integrated circuit packages is
Generally, it is repeated between -55℃ and +150℃,
It is necessary to have a phase transition temperature of -55°C or lower.

このように極めて低い相転位温度を有し且つ低熱膨張の
材料として、ニッケル(Ni)とコバルト(Co )を
含む鉄合金がある。この鉄合金のなかで特にNi量が2
9〜31重量%、Go量が12.5〜15重量%の範囲
にある合金は、ガラスの熱膨張係数に近似した熱膨張係
数を有し、リード片の材料として最適である。かかる成
分組成のF e −N i −C6f合金溶製材を、1
0〜60%の冷間加工後に100〜600℃間の温度で
応力除去焼鈍を行なうと、その熱膨張係数が40 X 
10−7/℃以下となることが判明した。なお実用上は
上記組成に、炭素(C)を0.1 重量%以下、けい素
(Si)を0.5重量%以下、マンガン(Mn)を0.
5 重量%以下の範囲で含有することができる。その他
の成分として溶解時に混入するリン(P)、硫黄(S)
等を不可避の不純物として、通常の溶製合金に含まれる
程度の量含んでもかまわない。
Iron alloys containing nickel (Ni) and cobalt (Co2) are examples of materials that have extremely low phase transition temperatures and low thermal expansion. Among this iron alloy, especially the Ni content is 2.
An alloy in which the amount of Go is in the range of 9 to 31% by weight and 12.5 to 15% by weight has a coefficient of thermal expansion close to that of glass, and is optimal as a material for the lead piece. F e -N i -C6f alloy ingot material having such a composition is 1
When stress relief annealing is performed at a temperature between 100 and 600℃ after 0 to 60% cold working, the thermal expansion coefficient is 40
It was found that the temperature was 10-7/°C or less. Practically speaking, the above composition includes carbon (C) of 0.1% by weight or less, silicon (Si) of 0.5% by weight or less, and manganese (Mn) of 0.1% by weight or less.
It can be contained in a range of 5% by weight or less. Other components include phosphorus (P) and sulfur (S) that are mixed in during dissolution.
etc. may be included as unavoidable impurities in amounts that are included in ordinary melted alloys.

Ni及びCO含有量が上記組成範囲より少ないと、完全
焼鈍状態からの冷却でマルテンサイト変態が生じ熱膨張
係数が増大する。また、上記組成範囲よりNi及びCo
量が多いと、オーステナイトが化学的に安定化しマルテ
ンサイト変態点は下がるが、熱膨張係数が増し40 X
 10−7/℃が得られにくくなる。冷間加工度につい
ては、10%以下では加工によるオーステナイトの安定
化が得べ られない。また組成によっては冷間加工度160%をこ
えると熱膨張係数が増加し90%以上になると加エマル
テンサイドが生成し熱膨張係数が著しく増大する。好ま
しくは12〜50%の冷間加工度を与えるのがよく、こ
の加工を与えることによりオーステナイトの安定化が得
られる。応力除去焼鈍は、材料の再結晶温度以下で行な
うべきで100〜600℃が適当である。100℃以下
テは十分な歪除去が達成できず、ガラス封止でリードが
変形するおそれがある。600℃以上の温度で焼鈍する
と加工によるオーステナイトの安定化効果が失なわれマ
ルテンサイト変態を生じやすくなる。
If the Ni and CO contents are less than the above composition range, martensitic transformation occurs upon cooling from the completely annealed state, resulting in an increase in the coefficient of thermal expansion. Also, from the above composition range, Ni and Co
If the amount is large, austenite becomes chemically stable and the martensitic transformation point decreases, but the coefficient of thermal expansion increases and 40
10-7/°C becomes difficult to obtain. Regarding the degree of cold working, if the degree of cold working is less than 10%, stabilization of austenite cannot be obtained by working. Also, depending on the composition, when the degree of cold working exceeds 160%, the coefficient of thermal expansion increases, and when the degree of cold working exceeds 90%, emulsion martenside is generated, and the coefficient of thermal expansion increases significantly. It is preferable to apply a cold working degree of 12 to 50%, and stabilization of austenite can be obtained by applying this working. Stress relief annealing should be performed at a temperature below the recrystallization temperature of the material, and is suitably 100 to 600°C. At temperatures below 100°C, sufficient strain removal cannot be achieved, and there is a risk that the leads may be deformed due to glass sealing. When annealing is performed at a temperature of 600° C. or higher, the stabilizing effect of austenite due to processing is lost and martensitic transformation is likely to occur.

次に脱酸、脱硫剤として添加する元素及び製造中に不可
避に混入する元素の許容量について説明する。Cは強力
な脱酸剤として材料の清浄度を向上させるために必要で
あるが、その含有量が増加すると熱膨張係数が増加する
のでCは0.1 重量%以下にすべきである。Siも脱
酸剤として用いられるが含有量が増加すると靭性が低下
しリード折れの原因となるので0.5重量%以下が適当
である。Mnは脱硫剤として用いられるが、含有量が増
加すると熱膨張係数が増加するので0.5 重量%以下
に限定する。p、sは材料の靭性を劣下させるのでP+
S量で0.01 重量%以下にするのが望ましい。
Next, the allowable amount of elements added as deoxidizing and desulfurizing agents and elements unavoidably mixed during production will be explained. C is necessary as a strong deoxidizing agent to improve the cleanliness of the material, but as its content increases, the coefficient of thermal expansion increases, so C should be kept at 0.1% by weight or less. Si is also used as a deoxidizing agent, but as the content increases, the toughness decreases and lead breakage is caused, so the content is preferably 0.5% by weight or less. Mn is used as a desulfurizing agent, but as the content increases, the coefficient of thermal expansion increases, so it is limited to 0.5% by weight or less. Since p and s deteriorate the toughness of the material, P+
It is desirable that the amount of S be 0.01% by weight or less.

第1表に、Ni−Fe合金、N i −G o −F 
e合金の熱膨張係数、電気抵抗の変化より求めた相変態
温度を示す。
Table 1 shows Ni-Fe alloy, Ni-Go-F
The phase transformation temperature determined from the change in thermal expansion coefficient and electrical resistance of the e-alloy is shown.

第1表 第2図に1本発明によるリードの材料すなわち29.5
重量%N i −14、5重量%Co −F s合金、
比較のために示した42重量%N i −F e合金お
よびガラスの熱膨張特性を示す、 Ni −Co−Fe
合金の熱膨張はガラスよりも少ない。
Table 1, Figure 2 shows the material of the lead according to the present invention, i.e. 29.5
wt% Ni-14, 5 wt% Co-Fs alloy,
Ni-Co-Fe, showing the thermal expansion properties of the 42 wt% Ni-Fe alloy and glass shown for comparison.
Alloys have less thermal expansion than glass.

(ロ)絶縁基板の構成: 絶縁基板は、炭化けい素質セラミックスによって構成さ
れる。従前のアルミナ焼結体基板に代えて炭化けい素質
セラミックスを用いることにより、半導体素子に生じた
熱の放散性をよくすることができる。
(b) Composition of the insulating substrate: The insulating substrate is composed of silicon carbide ceramics. By using silicon carbide ceramics in place of the conventional alumina sintered substrate, it is possible to improve the dissipation of heat generated in the semiconductor element.

炭化けい素質セラミックス基板は、セラミックス成型品
の製造手段として通常実施されている焼結法によって製
造することができる。
The silicon carbide ceramic substrate can be manufactured by a sintering method that is commonly used as a means for manufacturing ceramic molded products.

好適な絶縁基板は、ベリリウム(Be)およびベリリウ
ム化合物から選ばれた少なくとも1種をベリリウム量に
して、0.05〜5重量%含み、炭化けい素を主成分と
する炭化けい素質セラミックスであって、かつ、理論密
度の90%以上の相対密度を有する焼結体である。かか
る焼結体の熱膨張係数は35〜40 X 10−’/”
Cであって、けい素の熱膨張係数値に近く、また、その
熱伝導率は0.2caΩ/ am−s・℃以上である。
A preferred insulating substrate is a silicon carbide ceramic containing 0.05 to 5% by weight of at least one selected from beryllium (Be) and beryllium compounds, and containing silicon carbide as a main component. and a sintered body having a relative density of 90% or more of the theoretical density. The coefficient of thermal expansion of such a sintered body is 35 to 40 x 10-'/''
C, which has a thermal expansion coefficient close to that of silicon, and its thermal conductivity is 0.2 caΩ/am-s·°C or more.

この熱伝導率味0.2 caQ/cx−s・℃という値
は、炭化けい素質セラミックスが焼結によって作られる
場合に、電気絶縁性(抵抗率107Ω−1以上)と熱膨
張係数とに悪影響を与えることなく、良好な再現性をも
って得られる熱伝導率の下限を意味し、しかもそれは従
来のアルミナセラミック基板の熱伝導率の約4倍の値で
ある。また、熱膨張係数は半導体素子に使われるシリコ
ンのそれに近いものであリ、半導体素子が基板に接合さ
れた場合に、両者の熱膨張の差によって生ずる熱応力は
小さい。
This thermal conductivity value of 0.2 caQ/cx-s・℃ has a negative effect on electrical insulation (resistivity of 107 Ω-1 or more) and thermal expansion coefficient when silicon carbide ceramics are made by sintering. This means the lower limit of the thermal conductivity that can be obtained with good reproducibility without giving rise to a loss of heat, and moreover, it is about four times the thermal conductivity of conventional alumina ceramic substrates. Furthermore, the coefficient of thermal expansion is close to that of silicon used in semiconductor devices, and when a semiconductor device is bonded to a substrate, the thermal stress caused by the difference in thermal expansion between the two is small.

(ハ) キャップの構成; 基板上の半導体素子、配線等を覆い封入するためのキャ
ップは、熱膨張係数が20〜55 Xl0−7/℃をも
つ材料で構成されることが望ましい、このような材料と
して、炭化けい素質セラミックス。
(c) Structure of the cap; It is desirable that the cap for covering and enclosing the semiconductor elements, wiring, etc. on the substrate be made of a material having a coefficient of thermal expansion of 20 to 55 Xl0-7/°C. The material is silicon carbide ceramics.

°ムライト質セラミックス、ジルコン質セラミックス、
窒化けい素質セラミックスなどが使用できる。
°Mullite ceramics, zircon ceramics,
Silicon nitride ceramics and the like can be used.

前記熱膨張係数値をもつキャップ材を使用すると、従来
のアルミナセラミックス(熱膨張係数値65X 10−
7/℃)使用に比較して、炭化けい素質絶縁基板との間
の膨張差は少なくとも173以上軽減され、従ってそれ
だけ基板とキャップ間に起り得る熱応力は軽減される。
When a cap material with the above thermal expansion coefficient value is used, conventional alumina ceramics (thermal expansion coefficient value 65X 10-
7/° C.), the expansion differential between the silicon carbide insulating substrate and the silicon carbide insulating substrate is reduced by at least 173, and therefore the thermal stresses that may occur between the substrate and the cap are reduced accordingly.

(ニ)封止用ガラスの構成; 封止用ガラス材については、理想的には基板に使われた
炭化けい素質セラミックスの熱膨張係数に近い材料が望
ましく、その値として30〜55X10−7/”C特に
40〜55X10−フ/℃が適当である。ガラス封止が
、絶縁基板上に半導体素子を接着したのちに行なわれる
ため、高融点のガラスは使用に適さない、最高でも50
0℃以下の温度で封止可能なガラスを選定することが望
ましい。
(d) Composition of the sealing glass; Ideally, the sealing glass material should be a material with a coefficient of thermal expansion close to that of the silicon carbide ceramic used for the substrate, with a value of 30 to 55 x 10-7/ In particular, a temperature of 40 to 55 x 10-f/°C is appropriate. Glass sealing is performed after bonding the semiconductor element onto an insulating substrate, so glass with a high melting point is not suitable for use.
It is desirable to select glass that can be sealed at temperatures below 0°C.

このような条件を満足させるために、βユークリブタイ
ト、チタン酸鉛、これらを含むほう酸鉛系のガラスを使
用することが望ましい。
In order to satisfy these conditions, it is desirable to use β-eucribtite, lead titanate, or lead borate glass containing these.

以上のように構成することにより、封止温度から室温ま
での冷却においても、また、−55〜+150℃の間の
冷熱サイクルを反復した際にも。
By configuring as above, even when cooling from the sealing temperature to room temperature, and when repeating the cooling/heating cycle between -55 and +150°C.

封止部に亀裂を生じたり、電気特性に異常を生ずること
のない安定性と、高い信頼性をもち、熱放散特性にすぐ
れた集積回路パッケージが得られる。
It is possible to obtain an integrated circuit package that has stability, high reliability, and excellent heat dissipation characteristics without causing cracks in the sealing portion or abnormalities in electrical characteristics.

〔発明の実施例〕[Embodiments of the invention]

次に、本発明を実施例によって説明する。 Next, the present invention will be explained by examples.

実施例1 第1図に本発明の集積回路パッケージの断面を例示する
。同図において、炭化けい素質セラミックスからなる絶
縁基板4の一方の面上の中央部に半導体素子1が金属ソ
ルダ層7によって接着され。
Embodiment 1 FIG. 1 illustrates a cross section of an integrated circuit package of the present invention. In the figure, a semiconductor element 1 is bonded to the center of one surface of an insulating substrate 4 made of silicon carbide ceramics through a metal solder layer 7.

同面上に封止ガラス層6によって複数個のリード片3が
接着され、リード片の一端と半導体素子1との間は、ボ
ンディングワイヤ2によって電気的に接続されている。
A plurality of lead pieces 3 are bonded on the same surface through a sealing glass layer 6, and one end of the lead piece and the semiconductor element 1 are electrically connected by a bonding wire 2.

リード片3の他端は絶縁基板4の周縁から外方に延びて
いる。半導体素子1゜ボンディングワイヤ2およびリー
ド片3の端部は絶縁基板とキャップ5によって囲まれ、
該キャップ5と絶縁基板4およびリード片3との間隙は
封止ガラス層6を介して気密に封着されている。
The other end of the lead piece 3 extends outward from the periphery of the insulating substrate 4. The ends of the semiconductor element 1° bonding wire 2 and lead piece 3 are surrounded by an insulating substrate and a cap 5,
The gaps between the cap 5, the insulating substrate 4, and the lead pieces 3 are hermetically sealed via a sealing glass layer 6.

絶縁基板に用いる炭化けい素質セラミックスは、理論密
度の90%以上の密度をもつ焼結体である。
The silicon carbide ceramic used for the insulating substrate is a sintered body having a density of 90% or more of the theoretical density.

この焼結体は抵抗率(室温)10aΩ−1以上の電気絶
縁性と、熱伝導率0.2〜0.7caΩ/a1・S・℃
以上1曲げ強さ30kgf/ma”以上、熱膨張係数a
 5 x 10−7/℃の特性をもっている。
This sintered body has electrical insulation with a resistivity (room temperature) of 10 aΩ-1 or more and a thermal conductivity of 0.2 to 0.7 caΩ/a1・S・℃
1 Bending strength 30 kgf/ma” or more, thermal expansion coefficient a
It has a characteristic of 5 x 10-7/°C.

キャップ材には炭化けい素質セラミックスに近い熱膨張
係数をもつムライト質セラミックス(40〜55X10
−)7℃)、炭化けい素質セラミックス(25〜35 
X 10−7/”C)などが用いられる。封着用ガラス
には、熱膨張係数が絶縁基板の炭化けい素質セラミック
ス及びキャップ材料の熱膨張係数に近い40〜55X1
07/℃をも必要である。封止温度が低く、且つ、熱膨
張係数が低いガラスとしては、βユークリブタイト、チ
タン酸鉛、またはその両者を含むほう酸鉛系のガラスが
あり、本発明における封止用ガラス材として使用可能で
ある。
The cap material is made of mullite ceramic (40 to 55 x 10
-7℃), silicon carbide ceramics (25~35
X 10-7/"C) etc. are used for the sealing glass. The sealing glass has a thermal expansion coefficient of 40 to 55X1 close to that of the silicon carbide ceramic of the insulating substrate and the cap material
07/°C is also required. Examples of glasses with a low sealing temperature and a low coefficient of thermal expansion include β-eucribtite, lead titanate, or lead borate glass containing both, which can be used as the sealing glass material in the present invention. It is.

リード片の材料は、室温〜400℃の熱膨張係数が40
 X 10−’/℃以下の特性を有するNi−Co−F
e合金で、マルテンサイト変態が一55℃以下をもつ、
リード片はFa、Ni及びGoを所要量配合し真空溶解
後、熱間圧延してから冷間圧延と焼鈍をくり返し行ない
板厚0.18mにしてから、焼鈍し再び0.15■の厚
さまで冷間圧延を行ない仕上げた。その後約400〜5
00℃で歪取り焼鈍を行なった板よりリードフレームを
製作し、第1図に示す集積回路パッケージを製作した。
The material of the lead piece has a thermal expansion coefficient of 40 from room temperature to 400°C.
Ni-Co-F with characteristics of X 10-'/℃ or less
e alloy with martensitic transformation below 155°C.
The lead pieces are made by blending the required amounts of Fa, Ni and Go, melting them in vacuum, hot rolling them, repeating cold rolling and annealing until the plate thickness is 0.18m, and then annealing them again to a thickness of 0.15mm. Finished by cold rolling. After that, about 400-5
A lead frame was fabricated from a plate that had been annealed to remove strain at 00°C, and an integrated circuit package as shown in FIG. 1 was fabricated.

−55〜+150℃の信頼性試験の結果、ガラス封止部
のリーク不良は全くないことが確認された。
As a result of the reliability test at -55 to +150°C, it was confirmed that there was no leakage failure at the glass sealing part.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、ガラス封着処理の加熱か
ら室温迄冷却した時、及び−55〜+150℃の冷熱サ
イクルの寿命試験をかけた時に、ガラス封止部に亀裂を
生ずることのない、信頼性の高い集積回路パッケージが
得られる。
As described above, according to the present invention, cracks do not occur in the glass sealing part when the glass sealing process is heated and then cooled to room temperature, and when a life test is performed in a cooling/heating cycle from -55 to +150°C. The result is a highly reliable integrated circuit package.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の集積回路パッケージの断面図である。 第2図はリード片材料およびガラスの熱膨張特性図であ
る。 1・・・半導体素子、2・・・ボンディングワイヤ、3
・・・リード片、4・・・絶縁基板、5・・・キャップ
、6・・・封止ガラス層、7・・・金属ソルダ層。
FIG. 1 is a cross-sectional view of an integrated circuit package of the present invention. FIG. 2 is a diagram showing the thermal expansion characteristics of the lead piece material and glass. 1... Semiconductor element, 2... Bonding wire, 3
...Lead piece, 4...Insulating substrate, 5...Cap, 6...Sealing glass layer, 7...Metal solder layer.

Claims (1)

【特許請求の範囲】 1、炭化けい素質セラミックス絶縁基板、キャップおよ
び封止用ガラスによつて気密に囲まれた室内に、前記基
板上に載置された半導体素子と、前記室外から導入され
たリード片の端部、およびそれらを電気的に接続したワ
イヤを収容してなる集積回路パッケージにおいて、前記
リード片がニッケルとコバルトを含み、且つマルテンサ
イト変態温度が−55℃以下の鉄合金よりなることを特
徴とする集積回路パッケージ。 2、特許請求の範囲第1項において、前記鉄合金の成分
組成が、ニッケル29〜31重量%、コバルト12.5
〜15.5重量%および残部実質的に鉄よりなることを
特徴とする集積回路パッケージ。 3、特許請求の範囲第2項において、前記鉄合金が10
0〜600℃の温度範囲で応力除去焼鈍されていること
を特徴とする集積回路パッケージ。 4、特許請求の範囲第1項において、前記基板が炭化け
い素質焼結体よりなることを特徴とする集積回路パッケ
ージ。 5、特許請求の範囲第4項において、前記焼結体の成分
組成がベリリウムとベリリウム化分物の少なくとも1つ
をベリリウム量にして0.05〜5重量%、残部実質的
に炭化けい素よりなることを特徴とする集積回路パッケ
ージ。 6、特許請求の範囲第1項において、前記キャップが熱
膨張係数20〜55×10^−^7/℃を有するセラミ
ックスよりなることを特徴とする集積回路パッケージ。 7、特許請求の範囲第6項において、前記キャップがム
ライト質セラミックス、炭化けい素質セラミックス、ジ
ルコン質セラミックス、窒化けい素質セラミックスのい
ずれか1つよりなることを特徴とする集積回路パッケー
ジ。 8、特許請求の範囲第1項において、前記ガラスが熱膨
張係数30〜55×10^−^7/℃を有することを特
徴とする集積回路パッケージ。 9、特許請求の範囲第8項において、前記ガラスがβユ
ークリブタイト、チタン酸鉛系ガラス、ほウ酸鉛系ガラ
スのいずれか1つよりなることを特徴とする集積回路パ
ッケージ。
[Claims] 1. In a chamber airtightly surrounded by a silicon carbide ceramic insulating substrate, a cap, and a sealing glass, a semiconductor element mounted on the substrate and a semiconductor device introduced from the outside An integrated circuit package that accommodates the ends of lead pieces and the wires that electrically connect them, wherein the lead pieces are made of an iron alloy containing nickel and cobalt and having a martensitic transformation temperature of -55°C or less. An integrated circuit package characterized by: 2. In claim 1, the composition of the iron alloy is 29 to 31% by weight of nickel and 12.5% by weight of cobalt.
An integrated circuit package comprising ~15.5% by weight and the remainder consisting essentially of iron. 3. In claim 2, the iron alloy is 10
An integrated circuit package characterized in that it is stress-relieving annealed in a temperature range of 0 to 600°C. 4. An integrated circuit package according to claim 1, wherein the substrate is made of a sintered body of silicon carbide. 5. Claim 4, wherein the composition of the sintered body is such that at least one of beryllium and beryllium compound is 0.05 to 5% by weight of beryllium, and the remainder is substantially silicon carbide. An integrated circuit package characterized by: 6. The integrated circuit package according to claim 1, wherein the cap is made of ceramic having a coefficient of thermal expansion of 20 to 55 x 10^-^7/°C. 7. The integrated circuit package according to claim 6, wherein the cap is made of any one of mullite ceramics, silicon carbide ceramics, zircon ceramics, and silicon nitride ceramics. 8. The integrated circuit package according to claim 1, wherein the glass has a coefficient of thermal expansion of 30 to 55 x 10^-^7/°C. 9. An integrated circuit package according to claim 8, wherein the glass is made of one of β-eucribtite, lead titanate glass, and lead borate glass.
JP60171068A 1985-08-05 1985-08-05 Integrated circuit package Granted JPS6232631A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP60171068A JPS6232631A (en) 1985-08-05 1985-08-05 Integrated circuit package
US06/890,533 US4729010A (en) 1985-08-05 1986-07-30 Integrated circuit package with low-thermal expansion lead pieces
EP86305894A EP0211618B1 (en) 1985-08-05 1986-07-31 Integrated circuit package
DE8686305894T DE3672709D1 (en) 1985-08-05 1986-07-31 INTEGRATED CIRCUIT PACK.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60171068A JPS6232631A (en) 1985-08-05 1985-08-05 Integrated circuit package

Publications (2)

Publication Number Publication Date
JPS6232631A true JPS6232631A (en) 1987-02-12
JPH0431187B2 JPH0431187B2 (en) 1992-05-25

Family

ID=15916442

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60171068A Granted JPS6232631A (en) 1985-08-05 1985-08-05 Integrated circuit package

Country Status (1)

Country Link
JP (1) JPS6232631A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03167853A (en) * 1989-11-27 1991-07-19 Kyocera Corp Package for semiconductor-element
JPH03173154A (en) * 1989-11-30 1991-07-26 Kyocera Corp Package for housing semiconductor element
JPH0456343A (en) * 1990-06-26 1992-02-24 Kyocera Corp Package for accommodating semiconductor element

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54124972A (en) * 1978-03-23 1979-09-28 Tamagawa Kikai Kinzoku Kk Semiconductor lead material
JPS5596664A (en) * 1979-01-16 1980-07-23 Furukawa Electric Co Ltd:The Copper alloy for lead frame of semiconductor element
JPS563653A (en) * 1979-06-23 1981-01-14 Nippon Gakki Seizo Kk Manufacture of seal bonding material
JPS5933857A (en) * 1982-08-19 1984-02-23 Hitachi Metals Ltd Ic lead frame material and manufacture thereof
JPS5996245A (en) * 1982-11-22 1984-06-02 Daido Steel Co Ltd Material for lead frame and its manufacture
JPS59198741A (en) * 1983-04-25 1984-11-10 Nippon Gakki Seizo Kk Lead frame member for semiconductor integrated circuit
JPS61235535A (en) * 1985-04-10 1986-10-20 Hitachi Metals Ltd Alloy for lead frame

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54124972A (en) * 1978-03-23 1979-09-28 Tamagawa Kikai Kinzoku Kk Semiconductor lead material
JPS5596664A (en) * 1979-01-16 1980-07-23 Furukawa Electric Co Ltd:The Copper alloy for lead frame of semiconductor element
JPS563653A (en) * 1979-06-23 1981-01-14 Nippon Gakki Seizo Kk Manufacture of seal bonding material
JPS5933857A (en) * 1982-08-19 1984-02-23 Hitachi Metals Ltd Ic lead frame material and manufacture thereof
JPS5996245A (en) * 1982-11-22 1984-06-02 Daido Steel Co Ltd Material for lead frame and its manufacture
JPS59198741A (en) * 1983-04-25 1984-11-10 Nippon Gakki Seizo Kk Lead frame member for semiconductor integrated circuit
JPS61235535A (en) * 1985-04-10 1986-10-20 Hitachi Metals Ltd Alloy for lead frame

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03167853A (en) * 1989-11-27 1991-07-19 Kyocera Corp Package for semiconductor-element
JPH03173154A (en) * 1989-11-30 1991-07-26 Kyocera Corp Package for housing semiconductor element
JPH0456343A (en) * 1990-06-26 1992-02-24 Kyocera Corp Package for accommodating semiconductor element

Also Published As

Publication number Publication date
JPH0431187B2 (en) 1992-05-25

Similar Documents

Publication Publication Date Title
US4729010A (en) Integrated circuit package with low-thermal expansion lead pieces
US4352120A (en) Semiconductor device using SiC as supporter of a semiconductor element
JPS5896757A (en) Semiconductor device
JPS5921032A (en) Substrate for semiconductor device
JPS61176142A (en) Substrate structure
KR102252979B1 (en) Terminal connecting method of ceramic heater for semiconductor
JPS6232631A (en) Integrated circuit package
JP2544031B2 (en) How to eliminate cracks in alumina substrates
JP2004253736A (en) Heat spreader module
US4711826A (en) Iron-nickel alloys having improved glass sealing properties
JPS63235440A (en) Fine copper wire and its production
JPH0412623B2 (en)
JPH0337308B2 (en)
JP2523677B2 (en) Low thermal expansion lead frame material
JPS6245298B2 (en)
JPH01273690A (en) Material for brazing
KR102575288B1 (en) Semiconductor package and manufacturing method thereof
JPH06183852A (en) Bonding of beryllium oxide ceramic to metal
JPH0353780B2 (en)
JPH04329845A (en) Passive electronic part material
JPS63247325A (en) Fine copper wire and its production
US3465421A (en) High temperature bonding to germanium
JPS61259555A (en) Cu alloy bonding wire for semiconductor device
JPS62142720A (en) Manufacture of iron alloy having satisfactory resistance to stress corrosion cracking
CN112750550A (en) Bonding wire and semiconductor device