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JPS62232934A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62232934A
JPS62232934A JP61076978A JP7697886A JPS62232934A JP S62232934 A JPS62232934 A JP S62232934A JP 61076978 A JP61076978 A JP 61076978A JP 7697886 A JP7697886 A JP 7697886A JP S62232934 A JPS62232934 A JP S62232934A
Authority
JP
Japan
Prior art keywords
pellet
sheet
pellets
electrode pads
heat
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61076978A
Other languages
Japanese (ja)
Other versions
JPH0518461B2 (en
Inventor
Shinji Kobayashi
伸次 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61076978A priority Critical patent/JPS62232934A/en
Publication of JPS62232934A publication Critical patent/JPS62232934A/en
Publication of JPH0518461B2 publication Critical patent/JPH0518461B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To prevent contamination of elements, by adhering a heat-resistant sheet on the surface portion of a pellet other than electrode pads after dividing a semiconductor wafer into seperate pellets and before performing the die bonding or wire bonding operation. CONSTITUTION:A wafer is divided into seperate semiconductor pellets 1 which are spaced appropriate]y from each other on an electron sheet 3. A heat- resistant sheet of a polyimide film 4 for example is cut into an appropriate size in accordance with each pellet 1 and adhered on the surface portion of the pellet other than electrode pads 2 by means of an adhering jig 6 on a sheet pressing stage 5. The pellet is then secured on a die stage 8 of a led frame. The electrode pads are connected to the inner leads 9 of the lead frame by bonding metal wires l0 thereto. The sheet is then peeled off and the device is sealed with resin.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に半導体ペレ
ット分離後の組立工程中におけるペレットの表面保護方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for protecting the surface of a semiconductor pellet during an assembly process after separation of the semiconductor pellet.

〔従来の技術〕[Conventional technology]

一般に半導体装置の製造は、ウェーハをダイシングして
ペレットに分離後、ペレット表面の外観チェックを行な
い、不良ペレットを除去し、良品ペレットをリードフレ
ームのダイスステージにダイホントし、電極部とリード
フレームのインナーリードの間を金属細線で接続したの
ち、樹脂あるいはガラス等で封止している。Generally, in the manufacturing of semiconductor devices, after dicing a wafer and separating it into pellets, the appearance of the pellet surface is checked, defective pellets are removed, and the good pellets are die-bonded on the die stage of the lead frame. The leads are connected with thin metal wires and then sealed with resin or glass.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、上記工程中、ペレット表面は作業環境中
のごみや汚れ、あるいは機械からのごみ。However, during the above process, the pellet surface is exposed to dirt and grime in the working environment or debris from the machinery.

汚れ、人間からのごみ、汚れのために、素子に不具合が
生じ、歩留の低下が恒常的に発生している。Dirt, human debris, and contamination cause device failures and constant yield losses.

〔問題点を解決するための手段〕[Means for solving problems]

本発明はこのような問題点を解決するためになされたも
ので、半導体ウェーハからペレットに分離後、ペレット
の電極パッド以外の表面に耐熱性シートを貼シ付け、ダ
イボンディング及びワイヤボンディングを行なう。The present invention was made to solve these problems, and after separating a semiconductor wafer into pellets, a heat-resistant sheet is pasted on the surface of the pellets other than the electrode pads, and die bonding and wire bonding are performed.

〔実凡例〕[Actual legend]

次に本発明の実施例を図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.

第１図ないし第４図は、本発明の一実施例を説明するた
めの工程順の側面図（第１図と第２図に部分拡大平面図
を含む）である。まず、第１図のように、ウェーハから
個々の半導体ペレットに分離されたペレット１は、エレ
クトロンシート３上に適当な間隔で並べられている。各
ペレット１には、同図１１＞）の部分拡大平面図に示す
ように、ポンディングパッド２を有する。次に第２図（
ａ）　、　（ｂ）で示すように、ペレットサイズに応じ
て個片に切断された耐熱性シート、例えばポリイミドフ
ィルム４を、シート押さえステージ５にて貼シ付は治具
６に、より、ペレット上の電極パッド部２を除く表面に
貼り付ける。次に第３図に示すように、ペレットをリー
ドフレームのダイメスデージ８上に固着する。さらに、
第４図に示すように、電極パッド部とリードフレームの
インナーリード部９を金属ｌａ！１０でボンディングす
る。その後適当なシート剥離機にてシートを剥離し、樹
脂封止全行う。1 to 4 are side views (partially enlarged plan views are included in FIGS. 1 and 2) of steps for explaining an embodiment of the present invention. First, as shown in FIG. 1, pellets 1 separated from a wafer into individual semiconductor pellets are arranged on an electron sheet 3 at appropriate intervals. Each pellet 1 has a bonding pad 2, as shown in the partially enlarged plan view of FIG. 11>). Next, Figure 2 (
As shown in a) and (b), a heat-resistant sheet such as a polyimide film 4 cut into individual pieces according to the pellet size is pasted on a sheet holding stage 5 using a jig 6 to form pellets. Paste it on the surface except for the upper electrode pad part 2. Next, as shown in FIG. 3, the pellet is fixed onto the die size 8 of the lead frame. moreover,
As shown in FIG. 4, the electrode pad portion and the inner lead portion 9 of the lead frame are connected to metal la! Bond with 10. Thereafter, the sheet is peeled off using a suitable sheet peeling machine, and the entire resin sealing process is performed.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、ペレットは組立工程中、表面の主要部
分が保護されているため、作業環境中のごみや汚れの付
着がなく１作業者による汚染もなくなるため、素子の不
具合は極端に減少する。又シートとしてダイン５ンデイ
ングやボンディング温度に耐え得る耐熱性シートを使用
するので、シートによる不具合は生じない。なお、本発
明の実施例としてリードフレームを使用する場合を説明
したが、ガラスケースあるいはセラミックケースを使用
する場合も同様である。According to the present invention, the main part of the surface of the pellet is protected during the assembly process, so there is no adhesion of dust or dirt in the working environment, and there is no contamination by a single worker, resulting in an extreme reduction in device defects. do. In addition, since a heat-resistant sheet that can withstand the dynamizing and bonding temperatures is used as the sheet, problems caused by the sheet will not occur. Although the case where a lead frame is used has been described as an example of the present invention, the same applies when a glass case or a ceramic case is used.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）、第２図（ａ）、第３図および第４図は本
発明の一実施例を説明するための工程順の側面図、第１
図ｔｂ）および第２図（ｂ）はそれぞれ、第１図（ａ）
。 第２図ｔａ＞に示す半纏体ペレットの部分拡大平面図で
ある。 ■・・・・・・生得体ペレット、２・・・・・・ホンデ
ィングパッド、３・・・・−・エレクトロンシート、４
・・・・・・表面保護シート、５・・・・・・押さえス
テージ、６・・・・・・押さえ治具、８・・・・・・ダ
イステージ、９・・・・・・インナーリード、１０・・
・・・・金属細編。 代理人　弁理士　　内　原　　　晋 第ｌFIG. 1(a), FIG. 2(a), FIG. 3, and FIG. 4 are side views of the process order for explaining one embodiment of the present invention.
Figure tb) and Figure 2(b) are respectively similar to Figure 1(a).
. FIG. 2 is a partially enlarged plan view of the semi-integrated pellet shown in FIG. ■・・・Innate body pellet, 2・・・Honding pad, 3・・・・Electron sheet, 4
...Surface protection sheet, 5 ... Holding stage, 6 ... Holding jig, 8 ... Die stage, 9 ... Inner lead , 10...
...Metal details. Agent: Patent Attorney Shindai Uchihara

Claims (1)

【特許請求の範囲】[Claims] 半導体ウェーハをペレットに分離後、個々のペレットの
電極パッド以外の表面に耐熱性シートを貼り付けた後、
ダイボンディング及びワイヤボンディングを行なうこと
を特徴とする半導体装置の製造方法。After separating the semiconductor wafer into pellets and pasting a heat-resistant sheet on the surface of each pellet other than the electrode pads,
A method for manufacturing a semiconductor device, characterized by performing die bonding and wire bonding.
JP61076978A 1986-04-02 1986-04-02 Manufacture of semiconductor device Granted JPS62232934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61076978A JPS62232934A (en) 1986-04-02 1986-04-02 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61076978A JPS62232934A (en) 1986-04-02 1986-04-02 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS62232934A true JPS62232934A (en) 1987-10-13
JPH0518461B2 JPH0518461B2 (en) 1993-03-12

Family

ID=13620870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61076978A Granted JPS62232934A (en) 1986-04-02 1986-04-02 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62232934A (en)

Also Published As

Publication number Publication date
JPH0518461B2 (en) 1993-03-12

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