JPH03105950A - Package of semiconductor integrated circuit - Google Patents
Package of semiconductor integrated circuitInfo
- Publication number
- JPH03105950A JPH03105950A JP1244240A JP24424089A JPH03105950A JP H03105950 A JPH03105950 A JP H03105950A JP 1244240 A JP1244240 A JP 1244240A JP 24424089 A JP24424089 A JP 24424089A JP H03105950 A JPH03105950 A JP H03105950A
- Authority
- JP
- Japan
- Prior art keywords
- sealing glass
- cap
- package
- chip
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 239000005394 sealing glass Substances 0.000 claims abstract description 19
- 238000007789 sealing Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 3
- 239000000470 constituent Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路(以下、チップという)を密
閉するパッケージに関し、特にパッケージを構成するキ
ャップに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for sealing a semiconductor integrated circuit (hereinafter referred to as a chip), and particularly to a cap constituting the package.
従来、チップを密閉するパッケージは、ベースとキャッ
プと封止ガラスとリードフレームにより構成され、第2
図に示すようにキャップ1と封止ガラス4の界面は平坦
になっていた。Conventionally, a package that seals a chip consists of a base, a cap, a sealing glass, and a lead frame.
As shown in the figure, the interface between the cap 1 and the sealing glass 4 was flat.
上述した従来のパッケージは、封止ガラスを高温で熱処
理することにより軟化させ、ベースとキャップとリード
フレームを接合させるようになっているが、近来のパッ
ケージの小型化,薄型化に伴ない、接合面積が小さくな
り、密着性が悪化するという欠点がある。In the conventional package described above, the sealing glass is heat-treated at high temperature to soften it, and the base, cap, and lead frame are bonded together. However, as packages have become smaller and thinner in recent years, The disadvantage is that the area becomes smaller and the adhesion deteriorates.
本発明は、チップを密閉するパッケージにおいて、キャ
ップと封止ガラスの界面のキャップに溝を設け封止ガラ
スとの密着性を良くしたことを特徴とする。The present invention is characterized in that, in a package for sealing a chip, a groove is provided in the cap at the interface between the cap and the sealing glass to improve adhesion to the sealing glass.
次に、本発明について図面を参照して説明する。第1図
は、本発明の一実施例の縦断面図である。そして第3図
は第1図のキャップのみの縦断面図である。リードフレ
ーム3は、封止ガラス4によりベース2に圧着されてい
る。キャップ1には溝8が設けられており、封止ガラス
4が印刷されている。また、チップ5は、ダイボンディ
ング材6によりベース2にダイボンディングされている
。チップ5とリードフレーム3は、ボンディングワイヤ
ー7によって接続されている。以上の構或要素を高温で
熱処理することにより、封止ガラスが軟化し接合される
。Next, the present invention will be explained with reference to the drawings. FIG. 1 is a longitudinal sectional view of an embodiment of the present invention. FIG. 3 is a longitudinal sectional view of only the cap shown in FIG. 1. The lead frame 3 is pressure-bonded to the base 2 with a sealing glass 4. A groove 8 is provided in the cap 1, and a sealing glass 4 is printed on it. Further, the chip 5 is die-bonded to the base 2 using a die-bonding material 6. Chip 5 and lead frame 3 are connected by bonding wire 7. By heat-treating the above structural elements at high temperatures, the sealing glass is softened and bonded.
本実施例では、キャップ1に溝8が設けられているので
封止ガラス4との接合面積を大きくでき密着性が増大す
る。In this embodiment, since the groove 8 is provided in the cap 1, the bonding area with the sealing glass 4 can be increased and the adhesion can be increased.
以上説明したように本発明は、キャップに溝を設けるこ
とにより、小型のパッケージでもキャップと封止ガラス
の接合面積を大きくすることができ、密着性を向上でき
るという効果がある。As explained above, the present invention has the effect that by providing a groove in the cap, the bonding area between the cap and the sealing glass can be increased even in a small package, and the adhesion can be improved.
ム、4・・・封止ガラス、5・・・チップ、6・・・ダ
イボンディング材、7・・・ボンディングワイヤー 8
・・・清。4... Sealing glass, 5... Chip, 6... Die bonding material, 7... Bonding wire 8
...Kiyoshi.
Claims (1)
プと封止ガラスの界面のキャップに溝を設け封止ガラス
との密着性を良くしたことを特徴とする半導体集積回路
のパッケージ。1. A semiconductor integrated circuit package for sealing a semiconductor integrated circuit, characterized in that a groove is provided in the cap at the interface between the cap and the sealing glass to improve adhesion to the sealing glass.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1244240A JPH03105950A (en) | 1989-09-19 | 1989-09-19 | Package of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1244240A JPH03105950A (en) | 1989-09-19 | 1989-09-19 | Package of semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03105950A true JPH03105950A (en) | 1991-05-02 |
Family
ID=17115823
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1244240A Pending JPH03105950A (en) | 1989-09-19 | 1989-09-19 | Package of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03105950A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05235185A (en) * | 1992-02-25 | 1993-09-10 | Nec Corp | Ic package |
US5889323A (en) * | 1996-08-19 | 1999-03-30 | Nec Corporation | Semiconductor package and method of manufacturing the same |
US6856015B1 (en) * | 2003-08-21 | 2005-02-15 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with heat sink |
US7504670B2 (en) * | 2005-06-09 | 2009-03-17 | Shinko Electric Industries Co., Ltd. | Sealing structure for mounting a semiconductor device to a substrate |
JP2014165305A (en) * | 2013-02-25 | 2014-09-08 | Kyocera Crystal Device Corp | Electronic device, glass sealing method of the same, and lid member for the same |
-
1989
- 1989-09-19 JP JP1244240A patent/JPH03105950A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05235185A (en) * | 1992-02-25 | 1993-09-10 | Nec Corp | Ic package |
US5889323A (en) * | 1996-08-19 | 1999-03-30 | Nec Corporation | Semiconductor package and method of manufacturing the same |
US6856015B1 (en) * | 2003-08-21 | 2005-02-15 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with heat sink |
US7504670B2 (en) * | 2005-06-09 | 2009-03-17 | Shinko Electric Industries Co., Ltd. | Sealing structure for mounting a semiconductor device to a substrate |
JP2014165305A (en) * | 2013-02-25 | 2014-09-08 | Kyocera Crystal Device Corp | Electronic device, glass sealing method of the same, and lid member for the same |
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