JPS62174934A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS62174934A JPS62174934A JP61018469A JP1846986A JPS62174934A JP S62174934 A JPS62174934 A JP S62174934A JP 61018469 A JP61018469 A JP 61018469A JP 1846986 A JP1846986 A JP 1846986A JP S62174934 A JPS62174934 A JP S62174934A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pad
- semiconductor device
- small regions
- width
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 10
- 230000001681 protective effect Effects 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims 1
- 229910000838 Al alloy Inorganic materials 0.000 abstract description 10
- 229910052782 aluminium Inorganic materials 0.000 abstract description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 10
- 230000008646 thermal stress Effects 0.000 abstract description 6
- 238000001816 cooling Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 230000035882 stress Effects 0.000 abstract description 3
- 230000002950 deficient Effects 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000007123 defense Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 235000016623 Fragaria vesca Nutrition 0.000 description 1
- 240000009088 Fragaria x ananassa Species 0.000 description 1
- 235000011363 Fragaria x ananassa Nutrition 0.000 description 1
- 241000283973 Oryctolagus cuniculus Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は半導体装置およびその製造方法に関し、特に
、アルミニウムまたはアルミニウム合金からなる配線層
を有する半導体装置およびその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a wiring layer made of aluminum or an aluminum alloy and a method of manufacturing the same.
［従来の技術］
第２八図ないし第２Ｆ図は従来の半導体装置の一例の製
造工程を示す断面図および平面図である。[Prior Art] FIGS. 28 to 2F are a cross-sectional view and a plan view showing the manufacturing process of an example of a conventional semiconductor device.
以下、第２八図ないし第２Ｅ図を参照して従来の半導体
装置の製造方法について説明する。Hereinafter, a conventional method of manufacturing a semiconductor device will be described with reference to FIGS. 28 to 2E.
第２Δ図において、たとえばシリコンである半導体基板
１の所定領域にトランジスタ等からなる回路素子（図示
せず）が形成された後、絶縁膜であるＰＳＧ （燐ガラ
ス）膜２が所定領域に形成される。次に、ＰＳＧＩ２上
にアルミニウムまたはアルミニウム合金からなる配線層
３がｎ出した表面上全面に形成され、さらに配線層３上
にフォトレジスト膜４が塗布される。In FIG. 2Δ, after a circuit element (not shown) consisting of a transistor or the like is formed in a predetermined region of a semiconductor substrate 1 made of silicon, for example, a PSG (phosphor glass) film 2, which is an insulating film, is formed in a predetermined region. Ru. Next, a wiring layer 3 made of aluminum or an aluminum alloy is formed on the entire surface of the PSGI 2, and a photoresist film 4 is further applied on the wiring layer 3.
第２Ｂ図において、露光装置（図示せず）を用いた写真
製版およびエツチング法によりフォト−ジス１−膜４が
所定の形状にパターニングされる。In FIG. 2B, the photolithographic film 4 is patterned into a predetermined shape by photolithography and etching using an exposure device (not shown).
第２Ｃ図において、パターニングされたフＡトレジスＩ
−１１４をマスクとして配線層３をエツチングして内部
配線１３ａおよびボンディングパッド３′が所定の領域
に形成され１次にマスクとして用いたフォトレジスト膜
４が除去される。In FIG. 2C, the patterned photoresist I
-114 as a mask, the wiring layer 3 is etched to form internal wiring 13a and bonding pads 3' in predetermined areas, and then the photoresist film 4 used as the mask is removed.
第２Ｄ図において、露出した表面上全面にわたってＪｌ
終保ｒ！１！ＩＩ５が形成される。In Figure 2D, Jl is shown over the entire exposed surface.
End of life! 1! II5 is formed.
第２Ｅ図において、ボンディングパッド３−上の最終保
護ｍ５に写Ｗ製版およびエツチング法を用いて開口部を
設け、これによりボンディングパッド領域が完成する。In FIG. 2E, an opening is provided in the final protection m5 on the bonding pad 3- by using photolithography and etching, thereby completing the bonding pad area.
第２Ｆ図は、第２Ｅ図に示されるボンディングパッド３
−の平面構造を示す図である。このボンディングパッド
３′は、たとえばリード端子と半導体基板１上に形成さ
れた半導体回路装置との電気的接続点となるという重要
な役割を有している。FIG. 2F shows the bonding pad 3 shown in FIG. 2E.
It is a figure showing the planar structure of -. This bonding pad 3' has an important role of serving as an electrical connection point between a lead terminal and a semiconductor circuit device formed on the semiconductor substrate 1, for example.
［発明が解決しようとする問題点］
上ｊホの工程を経て形成された半導体装置を加熱（１５
０℃）および冷ｍ（−６５℃）の熱サイクルを繰返しく
１００ないし１０００サイクル）行ない、形成された半
導体装置の信頼性試験を行なった後、半導体装置を切断
し、その断面を観察すると、第３図に示されるように、
ボンディングパッド３′が横方向にスライドしているが
、一方、比較的線幅の狭い配線層３はほとんどスライド
していない（正常状Ｂ）という現象が見られる。この現
象は、加熱および冷却の熱サイクルを印加したときに最
終保ｒ！ｉ膜５に生じる熱ストレスにより引き起こされ
、アルミニウムまたはアルミニウム合金膜の線幅の広い
ところ、特にボンディングパッド３′にストレスが大き
くかかるためと考えられている。[Problems to be solved by the invention] The semiconductor device formed through the steps in j-e above is heated (15
After conducting a reliability test on the formed semiconductor device by repeating 100 to 1000 thermal cycles of 0°C) and cold (-65°C), the semiconductor device was cut and its cross section was observed. As shown in Figure 3,
A phenomenon is observed in which the bonding pad 3' slides laterally, but the wiring layer 3, which has a relatively narrow line width, hardly slides (normal state B). This phenomenon occurs when applying thermal cycles of heating and cooling. It is believed that this is caused by thermal stress generated in the i-film 5, and a large stress is applied to the areas where the line width of the aluminum or aluminum alloy film is wide, especially the bonding pads 3'.
このように熱ストレスによりボンディングパッド３′が
横方向にスライドすると、半導体装置を外部に電気的に
接続するための接触点位置が移動することになり、たと
えばボンディングワイヤとボンディングバンド３′との
接触不良が生じるなどの問題点があった。When the bonding pad 3' slides laterally due to thermal stress, the position of the contact point for electrically connecting the semiconductor device to the outside moves, for example, the contact between the bonding wire and the bonding band 3'. There were problems such as defects occurring.
それゆえ、この発明の目的は上述のような欠点を除去し
、ボンディングパッド３−の移動をなくすことにより、
たとえばボンディングワイヤとボンディングパッドとの
接触不良発生を除去し、これにより半導体装置の不良発
生率を低減することである。Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks and eliminate movement of the bonding pad 3-.
For example, the purpose is to eliminate the occurrence of poor contact between bonding wires and bonding pads, thereby reducing the failure rate of semiconductor devices.
［問題点を解決するための手段１
この発明に係る半導体装置は、１１１装置のボンディン
グパッドにおいて、その幅が所定幅、好ましくは５ｆ１
ｍ以下の小領域に分割された領域を有するようにボンデ
ィングパッドを構成したちのである。[Means for Solving the Problems 1] In the semiconductor device according to the present invention, the width of the bonding pad of the 111 device is a predetermined width, preferably 5f1.
The bonding pad is configured to have an area divided into small areas of m or less.
［作用１
線幅か狭い（約１０ｕｍ以下）領域では、熱ストレスに
よるスライド現象は発生しない。したがって、１個のボ
ンディングパッドを構成するＷＩ数国の小領域の各々は
、その幅が所定幅、好ましくは５μｍ以下にされている
ので、最終保護膜の熱ストレスによる影野を見掛は上緩
和することができ、個々の幅の狭い小領域が移動するこ
とがなく、ボンディングパッドのたとえばボンディング
用ワイヤとの接触点の移動を防止することができる。[Effect 1: In a region where the line width is narrow (approximately 10 um or less), the sliding phenomenon due to thermal stress does not occur. Therefore, each of the small regions of several WI countries constituting one bonding pad has a predetermined width, preferably 5 μm or less, so that the appearance of the shadow caused by thermal stress on the final protective film is reduced. It is possible to relax the individual narrow regions without movement and to prevent movement of the contact point of the bonding pad, for example with the bonding wire.
［弁明の実施例１
第１Δ図および第１Ｂ図はこの発明の一実施例である半
導体装置の概略構造を示す図であり、第１Ａ図はその断
面構造を示し、第１Ｂ図はボンディングパッド領域の平
面構造の一例を示す図である。以下、第１Ａ図および第
１Ｂ図を参照してこの弁明の一実施例による半導体８ｉ
蓑の構成について説明する。[Embodiment 1 of Defense] Fig. 1Δ and Fig. 1B are diagrams showing a schematic structure of a semiconductor device which is an embodiment of the present invention, Fig. 1A shows its cross-sectional structure, and Fig. 1B shows a bonding pad area. FIG. 2 is a diagram showing an example of a planar structure of FIG. Hereinafter, with reference to FIGS. 1A and 1B, a semiconductor 8i according to an embodiment of this defense will be described.
The structure of the strawberry will be explained.
たとえばシリコンである半導体基板１上に、絶縁喚であ
るＰＳＧ模（燐ガラス膜）２が予め定められた形１ツク
に形成される。このＰ Ｓ Ｇ ｇＲ２上に１よ、アル
ミニウムまｌ；はアルミニウム合金力日らなる内部量ｌ
１１１１Ｊ３ａと、ボンディングパッド３０がそれぞれ
所定の＃４域に形成される。この発明の特ｉ′ｉとして
、ボンディングバンド３０は、少数個の小頭域に分割さ
れた領域を有するように形１吸されている。このボンデ
ィングパッドに含まれる小ｆＪ（Ｉｆｆの幅は所定幅、
好ましくは５μｍ以下にされている。For example, on a semiconductor substrate 1 made of silicon, a PSG pattern (phosphor glass film) 2 serving as an insulator is formed in a predetermined shape. On this P S G gR2, 1, aluminum is the internal amount of aluminum alloy.
1111J3a and bonding pad 30 are respectively formed in a predetermined #4 area. As a feature of the invention, the bonding band 30 is shaped so as to have a region divided into a small number of subregions. The small fJ included in this bonding pad (the width of Iff is a predetermined width,
The thickness is preferably 5 μm or less.
ＰＳＧＩ１ｍ２上および配置１３ａ上ならびにボンディ
ングパッド３０周辺部は最終保護膜５で覆われる。ボン
ディングパッド３０上には、ワイヤボンディング用の開
口部が設けられている。The final protective film 5 covers the PSGI 1m2, the arrangement 13a, and the periphery of the bonding pad 30. An opening for wire bonding is provided on the bonding pad 30.
第１Ｂ図においては、この発明の一実施例である半導体
装置において形成されたボンディングパッド３ｏがくし
形の形状に構成された場合が一例として示される。FIG. 1B shows, as an example, a case where bonding pads 3o formed in a semiconductor device according to an embodiment of the present invention are configured in a comb shape.
次にこの発明の一実施例である半導体装置の製造方法に
ついて説明する。Next, a method for manufacturing a semiconductor device, which is an embodiment of the present invention, will be described.
不純物拡散層、すなわちトランジスタ領域（図示せず）
が形成されたシリコン半ｓ体譜板１上にＰＳＧ膜２が塗
布される。このＰＳＧ膜２上にスパック法、真空蒸着法
およびＣＶＤ法等を用いてアルミニウムまたはアルミニ
ウム合金からなる金属膜が仝而に形成される。この工程
は第２Ａ図に示される工程と同一である。Impurity diffusion layer, i.e. transistor region (not shown)
A PSG film 2 is applied onto the silicon half-score board 1 on which the PSG film 2 is formed. A metal film made of aluminum or an aluminum alloy is then formed on this PSG film 2 by using a spuck method, a vacuum evaporation method, a CVD method, or the like. This step is identical to the step shown in FIG. 2A.
次に形成したアルミニウムまたはアルミニウム合金から
なる金属膜上にフォトレジスト唄を露出した表面上全面
に塗布し、写真狛版およびエツチング工程で予め定めら
れた形状にパターニングする。このとき、ボンディング
パッド部分は、少なくともその幅が５μｍ以下である小
領域に分ｔＪされた領ｊ戊を有するようにパターニング
される。この工程は第２Ｂ図に示される工程に対応する
ものである。Next, a photoresist is applied to the entire exposed surface of the formed metal film made of aluminum or aluminum alloy, and patterned into a predetermined shape using a photolithography and etching process. At this time, the bonding pad portion is patterned to have a region divided into small regions each having a width of at least 5 μm or less. This step corresponds to the step shown in FIG. 2B.
次に、パターニングされたフォトレジスト膜をマスクと
して下地のアルミニウムまたはアルミニウム合金金属膜
をエツチングする。次にマスクとして用いたフォトレジ
スト川を陥入し、パターニングされたアルミニウムまた
はアルミニウム合金膜の焼き締めのため４００〜５００
℃で熱処理を行なう。この工程は第２Ｃ［ｉ４に示され
る工程に対応する。Next, the underlying aluminum or aluminum alloy metal film is etched using the patterned photoresist film as a mask. Next, the photoresist layer used as a mask is invaginated, and the patterned aluminum or aluminum alloy film is baked at a temperature of 400 to 500 μm.
Heat treatment is carried out at ℃. This step corresponds to the step shown in 2nd C[i4.
次に露出した表面上全面にわたって最終保謂摸５を形成
しく第２Ｄ図の工程に対応）、写１１製版６よびエツチ
ング法を用いてボンディングパッド３０上に開口部を形
成づる。これは第２Ｅ図および第２Ｆ図に示される工程
に対応する。Next, a final sealing plate 5 is formed over the entire exposed surface (corresponding to the process shown in FIG. 2D), and an opening is formed on the bonding pad 30 using a copying plate 6 and an etching method. This corresponds to the steps shown in FIGS. 2E and 2F.
以上の工程によりボンディングパッド３０を第１Ａ図、
第１Ｂ図に示されるような小領域に分割することが７斤
しい工程な付カロすることなくσ易ｉ二実現することが
できる。各小頭域の幅は狭くされているので、加熱−冷
却の熱サイクル時にｉ者主する最終保護膜からの応力に
対しても強くなってスライド現象が生じることはない。Through the above steps, the bonding pad 30 is formed as shown in FIG. 1A.
Dividing into small regions as shown in FIG. 1B can be achieved without requiring a large process and expense. Since the width of each capitellar region is narrow, it becomes strong against stress from the final protective film during heating-cooling thermal cycles, and no sliding phenomenon occurs.
なＪ３、上記″Ｘ施例においては、ボンディングバツド
の形状として第１Ｂ図に示されるようにくし形彫状の場
合を一例として示しているが、この形状に限定されるこ
となく、たとえば短冊状に形成する場合、また網目状に
構成した場合においても、その幅が所定幅、好ましくは
５μｍ以下であるならば同様の効果を）りることができ
る。J3, In the above-mentioned "X Example," the shape of the bonding butt is shown as an example of a comb-shaped shape as shown in FIG. 1B. Even when formed in a mesh shape, the same effect can be obtained as long as the width is a predetermined width, preferably 5 μm or less.
［発明の効果１
以上のように、この発明によれば、１個のボンディング
パッドに関して、その幅が所定幅く５μｍ＞以下である
櫂数個の小領域に分割して構成するようにしたので、加
熱−冷却の熱サイクル条件下でも、最終保護膜からの熱
応力によるスライド現象が生ぜず、ボンディングワイヤ
等とボンディングパッドとの接触不良が生じることもな
く半導体装置の信頼性を向上することができるとともに
不良発生率を低減することができる。[Effect of the Invention 1 As described above, according to the present invention, one bonding pad is divided into several small regions each having a predetermined width of 5 μm or less. Even under thermal cycle conditions of heating and cooling, the sliding phenomenon due to thermal stress from the final protective film does not occur, and poor contact between bonding wires and bonding pads does not occur, improving the reliability of semiconductor devices. At the same time, the defect rate can be reduced.
第１Ａ図および第１Ｂ図はこの発明の一実施例である半
導体装置の概略構成を示す図であり、第１Ａ図はその断
面構造を示す図であり、第１Ｂ図はボンディングパッド
の平面形状の一例を示す図である。
第２八図ないし第２Ｆ図は従来の半導体装置の一例の製
造工程を示す断面図および平面図である。
第３図は、従来の半導体装ハのボンディングバンド′ｆ
４ＴＴｌｉに発生するスライド状態を示す断面図である
。
図において、１は半導体島板、２はＰＳＧ摸、３はアル
ミニウムまたはアルミニウム合金膜、３ａは内部１１１
層、５はＲ終保護膜、３−．３０はボンディングパッド
である。
なお、図中、同一符号は同一または相当部分を示す。
代 理 人 大 岩 増 雄第１Ａ
図
］）：１１Ｂｌｌｌ
１ ： 千 リ午 イ＊＠”４Ｌ
２： ＰＳＧ繰
３０： ホ゛ンす゛イレク″ノ＼？５．７Ｆ第２ＡＩ
兎２Ｂ図第２Ｃ図 第
２Ｄ図
ｊ
第２Ｅ図 第２Ｆ図
冷1A and 1B are diagrams showing a schematic configuration of a semiconductor device which is an embodiment of the present invention, FIG. 1A is a diagram showing its cross-sectional structure, and FIG. 1B is a diagram showing a planar shape of a bonding pad. It is a figure showing an example. FIGS. 28 to 2F are a cross-sectional view and a plan view showing the manufacturing process of an example of a conventional semiconductor device. Figure 3 shows the bonding band 'f of a conventional semiconductor device.
FIG. 4 is a cross-sectional view showing a sliding state that occurs in 4TTli. In the figure, 1 is a semiconductor island board, 2 is a PSG model, 3 is an aluminum or aluminum alloy film, and 3a is an internal 111
layer, 5 is R final protective film, 3-. 30 is a bonding pad. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa 1st A
Figure]):11Bllll 1: Thousand Rigoi*@"4L 2: PSG Re30: Honsu゛Ireku"ノ＼? 5.7F 2nd AI
Rabbit 2B Figure 2C Figure 2D Figure j Figure 2E Figure 2F Cold
Claims (8)
素子を前記半導体基板の外部領域に電気的に接続するた
めに前記半導体基板上に形成された少なくとも１個のボ
ンディングパッドとを含む半導体装置であって、 前記少なくとも１個のボンディングパッドは、複数個の
小領域に分割された領域を有し、かつ前記複数個の小領
域の各々は少なくともその幅が所定幅以下にされてるこ
とを特徴とする半導体装置。(1) A semiconductor including a circuit element formed on a semiconductor substrate and at least one bonding pad formed on the semiconductor substrate for electrically connecting the circuit element to an external region of the semiconductor substrate. The at least one bonding pad has a region divided into a plurality of small regions, and each of the plurality of small regions has at least a width equal to or less than a predetermined width. Characteristic semiconductor devices.
項記載の半導体装置。(2) Claim 1, wherein the predetermined width is 5 μm.
1. Semiconductor device described in Section 1.
島領域を形成する、特許請求の範囲第１項または第２項
記載の半導体装置。(3) The semiconductor device according to claim 1 or 2, wherein each of the plurality of small regions forms an island region separated from each other.
し形状に形成されている、特許請求の範囲第１項または
第２項に記載の半導体装置。(4) The semiconductor device according to claim 1 or 2, wherein the at least one bonding pad is formed in a comb shape.
素子を前記半導体基板の外部領域に電気的に接続するた
めの少なくとも１個のボンディングパッドとを含む半導
体装置の製造方法であって、前記回路素子が形成された
前記半導体基板上に予め定められた形状にパターニング
された絶縁膜を形成するステップと、 前記パターニングされた絶縁膜上全面にわたって金属導
電膜を形成するステップと、 前記金属導電膜を予め定められた形状にパターニングし
、前記回路素子を相互接続するための内部配線を形成す
るとともに、少なくとも各々の幅が所定幅以下の複数個
の小領域を有するボンディングパッドを形成するステッ
プと、 露出した表面上にわたって保護膜を形成するステップと
、 前記ボンディングパッド上に形成された保護膜に開口部
を設けるステップとを含む、半導体装置の製造方法。(5) A method for manufacturing a semiconductor device including a circuit element formed on a semiconductor substrate and at least one bonding pad for electrically connecting the circuit element to an external region of the semiconductor substrate, forming an insulating film patterned in a predetermined shape on the semiconductor substrate on which the circuit element is formed; forming a metal conductive film over the entire surface of the patterned insulating film; patterning the film into a predetermined shape to form internal wiring for interconnecting the circuit elements, and forming a bonding pad having at least a plurality of small regions each having a width equal to or less than a predetermined width; A method for manufacturing a semiconductor device, comprising: forming a protective film over the exposed surface; and providing an opening in the protective film formed over the bonding pad.
幅は５μｍ以下である、特許請求の範囲第５項記載の半
導体装置の製造方法。(6) The method of manufacturing a semiconductor device according to claim 5, wherein each of the small regions of the bonding pad has a width of 5 μm or less.
の各々は、互いに分離された島領域を形成する、特許請
求の範囲第５項または６項に記載の半導体装置の製造方
法。(7) The method of manufacturing a semiconductor device according to claim 5 or 6, wherein each of the plurality of small regions of the bonding pad forms an island region separated from each other.
である、特許請求の範囲第５項または第６項に記載の半
導体装置の製造方法。(8) The method for manufacturing a semiconductor device according to claim 5 or 6, wherein the bonding pad has a comb shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61018469A JPS62174934A (en) | 1986-01-28 | 1986-01-28 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61018469A JPS62174934A (en) | 1986-01-28 | 1986-01-28 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62174934A true JPS62174934A (en) | 1987-07-31 |
| JPH0482054B2 JPH0482054B2 (en) | 1992-12-25 |
Family
ID=11972496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61018469A Granted JPS62174934A (en) | 1986-01-28 | 1986-01-28 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62174934A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5309025A (en) * | 1992-07-27 | 1994-05-03 | Sgs-Thomson Microelectronics, Inc. | Semiconductor bond pad structure and method |
| US6087756A (en) * | 1997-08-11 | 2000-07-11 | Murata Manufacturing Co., Ltd. | Surface acoustic wave |
| US6414415B1 (en) | 1999-02-18 | 2002-07-02 | Murata Manufacturing Co., Ltd. | Surface acoustic wave device and method for manufacturing the same |
| US8896397B2 (en) * | 2003-04-16 | 2014-11-25 | Intellectual Ventures Fund 77 Llc | Surface acoustic wave device and method of adjusting LC component of surface acoustic wave device |
| USRE47410E1 (en) * | 2003-04-16 | 2019-05-28 | Intellectual Ventures Holding 81 Llc | Surface acoustic wave device and method of adjusting LC component of surface acoustic wave device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS558044A (en) * | 1978-06-30 | 1980-01-21 | Sumitomo Electric Ind Ltd | Semiconductor element |
| JPS55135459U (en) * | 1979-03-19 | 1980-09-26 | ||
| JPS5929430A (en) * | 1982-08-11 | 1984-02-16 | Matsushita Electronics Corp | Semiconductor device |
| JPS61220364A (en) * | 1985-03-26 | 1986-09-30 | Fujitsu Ltd | Pectinate type bonding pad |
-
1986
- 1986-01-28 JP JP61018469A patent/JPS62174934A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS558044A (en) * | 1978-06-30 | 1980-01-21 | Sumitomo Electric Ind Ltd | Semiconductor element |
| JPS55135459U (en) * | 1979-03-19 | 1980-09-26 | ||
| JPS5929430A (en) * | 1982-08-11 | 1984-02-16 | Matsushita Electronics Corp | Semiconductor device |
| JPS61220364A (en) * | 1985-03-26 | 1986-09-30 | Fujitsu Ltd | Pectinate type bonding pad |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5309025A (en) * | 1992-07-27 | 1994-05-03 | Sgs-Thomson Microelectronics, Inc. | Semiconductor bond pad structure and method |
| US6087756A (en) * | 1997-08-11 | 2000-07-11 | Murata Manufacturing Co., Ltd. | Surface acoustic wave |
| US6414415B1 (en) | 1999-02-18 | 2002-07-02 | Murata Manufacturing Co., Ltd. | Surface acoustic wave device and method for manufacturing the same |
| US8896397B2 (en) * | 2003-04-16 | 2014-11-25 | Intellectual Ventures Fund 77 Llc | Surface acoustic wave device and method of adjusting LC component of surface acoustic wave device |
| USRE47410E1 (en) * | 2003-04-16 | 2019-05-28 | Intellectual Ventures Holding 81 Llc | Surface acoustic wave device and method of adjusting LC component of surface acoustic wave device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0482054B2 (en) | 1992-12-25 |
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