JPS6367753A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6367753A JPS6367753A JP21312286A JP21312286A JPS6367753A JP S6367753 A JPS6367753 A JP S6367753A JP 21312286 A JP21312286 A JP 21312286A JP 21312286 A JP21312286 A JP 21312286A JP S6367753 A JPS6367753 A JP S6367753A
- Authority
- JP
- Japan
- Prior art keywords
- film
- bonding pad
- psg
- polysilicon
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 14
- 239000011574 phosphorus Substances 0.000 claims abstract description 14
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 13
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 8
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 abstract description 6
- 230000007423 decrease Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910000714 At alloy Inorganic materials 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 210000001015 abdomen Anatomy 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000003017 phosphorus Chemical class 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係）、特に半導体素子上のボンデ
ィングパッドの構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a bonding pad on a semiconductor element.
従来、この種の半導体装置は、そのボンディングパッド
部分の断面および平面図をそれぞれ第３図、第４図に示
すように、回路素子が組み込まれたシリコン基板１の上
にフィールド酸化膜（Ｓｉ（ｈ ） ２およびリンを含
有する二酸化硅素ｇＸ（以下、ＰＳＧ膜と称す）４を順
次形成したうえ、このＰＳＧ膜４上に蒸着などによシア
ルミニウム（以下、Ａｔと記す）膜５を形成する。そし
て、これをバターニングした後、絶縁保護膜６を被着し
てそのＡｔ膜膜上上ボンディング部のみを開孔させるこ
とによ）、この開孔されたＡｔ膜５をボンディングパッ
ドとして金（Ａｕ）などのリード線（図示せず）にてボ
ンディングするものとなっている。なお、同図中、６ａ
は絶縁保護膜６に設けられた開孔部である。Conventionally, this type of semiconductor device has a field oxide film (Si( h) After sequentially forming silicon dioxide gX (hereinafter referred to as PSG film) 4 containing 2 and phosphorus, a sialumium (hereinafter referred to as At) film 5 is formed on this PSG film 4 by vapor deposition or the like. Then, after patterning this, an insulating protective film 6 is deposited and holes are formed only on the bonding portion on the At film.) Then, the opened At film 5 is used as a bonding pad and a gold layer is formed. Bonding is performed using a lead wire (not shown) made of (Au) or the like. In addition, in the same figure, 6a
is an opening provided in the insulating protective film 6.
しかし、従来の半導体装置は以上のような構造を有して
いるので、ＰＳＧ膜４中の不純物特にリンのＡｔ膜膜中
中の拡散カニ起こシ易く、このリンの影響による初期ボ
ンディング性の低下、あるいは金−Ａｔ合金層の高温時
の早期劣化、水分の侵入によシリン酸が発生してｈｔ
ｔＱ食させる耐温性不良現象などを引き起こすという問
題点がちつた。However, since the conventional semiconductor device has the above-mentioned structure, impurities in the PSG film 4, especially phosphorus, are likely to diffuse into the At film, and the initial bonding performance is deteriorated due to the influence of this phosphorus. , or early deterioration of the gold-At alloy layer at high temperatures, or the generation of silicic acid due to moisture intrusion.
Problems have arisen, such as poor temperature resistance due to tQ corrosion.
本発明は上記のような問題点を解消するためＫなされた
もので、その目的は、ボンディングパッドにＡｔを用い
る際にその人ｔＨへのリンの拡散を抑制することによ）
、信頼性を向上させた半導体装置全提供することにある
。The present invention was made to solve the above-mentioned problems, and its purpose is to suppress the diffusion of phosphorus into the bonding pad when At is used for the bonding pad.
Our goal is to provide all semiconductor devices with improved reliability.
本発明に係る半導体装置は、シリコン基板上に形成され
たフィールド酸化膜の表面に内部配線のゲートと同時に
ポリシリコン膜を設置し、このポリシリコン膜の上にリ
ンを含有する二酸化硅素膜を形成したうえ、該二酸化硅
素膜のボンディングパッドの箇所だけエッチングにより
除去してその’？ＭＰＡＩｔＣＡｔ膜をボンディングパ
ッドとして設けたものである。In the semiconductor device according to the present invention, a polysilicon film is placed on the surface of a field oxide film formed on a silicon substrate at the same time as the gate of the internal wiring, and a silicon dioxide film containing phosphorus is formed on the polysilicon film. Then, only the bonding pad portion of the silicon dioxide film is removed by etching. A MPAItCAt film is provided as a bonding pad.
本発明においては、ボンディングパッド部のＡｔ膜の下
にポリシリコン膜を設け、その人を膜とリンを含有する
二酸化硅素膜つまｆｉＰｓＧ膜とが接触する部分を少な
くすることによυ、Ａｔ膜中へのリンの拡散を抑制する
ことカニできる。In the present invention, a polysilicon film is provided under the At film in the bonding pad portion, and by reducing the contact area between the film and the phosphorous-containing silicon dioxide film or fiPsG film, the At film It can suppress the diffusion of phosphorus into the crab.
以下、本発ＢＪＪを図面に示す実施例に基づいて詳細に
説明する。Hereinafter, the present BJJ will be explained in detail based on an embodiment shown in the drawings.
第１図は本発明の一実施例による半導体装置のボンディ
ングパッド部分の概略断面図で、第２図はその平面図で
ある。この実施例では、シリコン基板１上に形成された
フィールド酸化膜２０表面に、半導体素子を構成する内
部配線のゲートと同時にポリシリコン膜３を形成し、こ
のポリシリコン膜３の上にＰＳＧＳ導膜形成する。そし
て、とのＰＳＧＳ導膜ボンディングパッド部分のみをエ
ツチングによ）除去して開孔部４ａを施したうえ、この
開孔部４轟を含むＰＳＧＳ導膜上にＡｔ膜５を被着する
。次いでとのＡｔ膜５を所定形状にパターニングした後
、その上に絶縁保護膜６を被着して、この膜６のボンデ
ィングパッドとなる部分を開孔させることによ）、第１
図に示す：うに、Ａｔ膜５の周囲部を絶縁保護膜６にて
被覆セーしめて該ＡｔＰｊＪ５にボンディングパッドと
して構成したものである。なお、図中、同一符号は同一
または相当部分を示している。FIG. 1 is a schematic sectional view of a bonding pad portion of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view thereof. In this embodiment, a polysilicon film 3 is formed on the surface of a field oxide film 20 formed on a silicon substrate 1 at the same time as the gate of an internal wiring constituting a semiconductor element, and a PSGS conductive film is formed on this polysilicon film 3. Form. Then, only the bonding pad portion of the PSGS conductive film is removed (by etching) to form an opening 4a, and an At film 5 is deposited on the PSGS conductive film including the opening 4. Next, after patterning the At film 5 into a predetermined shape, an insulating protective film 6 is deposited thereon, and a hole is opened in a portion of this film 6 that will become a bonding pad).
As shown in the figure, the periphery of the At film 5 is covered with an insulating protective film 6 to form a bonding pad on the AtPjJ5. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
このように上記実施例によると、フィールド酸化膜２と
Ａｔ、［５の間に内部配線のゲートと同時にポリシリコ
ン膜３を形成し、ボンディングパッドとしてのＡｔ膜５
の下にはＰＳＧｉ４が存在しないようＫしたので、Ａｔ
膜５とＰＳＧＳ導膜が接触する部分が少なくな９、その
Ａｔ膜５中へのリンの拡散を抑制できる。これによって
、ＰＳＧ腹４中のリンの影響による初期ボンディング性
の低下を防止できるとともに、膜の界面を通じて侵入し
た水とＰＳＧＭＪ中のリンとの反応を抑制することがで
きる。さらに、ボンディング部の金−Ａｔ合金層に悪影
響企及はすリンの拡散を抑えることができるなど、長期
的信頼性の向上がはかれる。しかも、Ａｔ膜５の下地と
なるポリシリコン膜３は、内部配線のゲートと同時に形
成できるので、プロセス的には工程が増えることはなく
、半導体製造上有利となる利点を奏する。According to the above embodiment, the polysilicon film 3 is formed between the field oxide film 2 and the At film 5 at the same time as the gate of the internal wiring, and the At film 5 is formed as a bonding pad.
Since I made sure that PSGi4 does not exist under the At
Since the contact area between the film 5 and the PSGS conductive film is reduced 9, diffusion of phosphorus into the At film 5 can be suppressed. This makes it possible to prevent a decrease in initial bonding properties due to the influence of phosphorus in the PSG belly 4, and to suppress the reaction between water that has entered through the membrane interface and phosphorus in the PSGMJ. Furthermore, long-term reliability can be improved by suppressing the diffusion of phosphorus, which has an adverse effect on the gold-At alloy layer at the bonding part. Moreover, since the polysilicon film 3 underlying the At film 5 can be formed at the same time as the gate of the internal wiring, there is no increase in the number of steps in the process, which is advantageous in terms of semiconductor manufacturing.
以上のように本発明によれば、ボンディングパッドの構
造を、Ａｔ膜の下にポリシリコン膜を設けて、このＡｔ
膜およびポリシリコン膜の下にはＰＳＧ膜が存在しない
ように構成したので、ボンディング性の向上が計れると
ともに、金−Ａｔ接合部の早期劣化を防ぐことができ、
これによって半導体素子の長期信頼性を確保することが
可能となる。As described above, according to the present invention, the structure of the bonding pad is such that a polysilicon film is provided under the At film.
Since the PSG film is not present under the film and the polysilicon film, bonding performance can be improved and early deterioration of the gold-At junction can be prevented.
This makes it possible to ensure long-term reliability of the semiconductor element.
第１図は本発明の一実施例による半導体装置のボンディ
ングパッド部を示す要部断面図、第２図は第１図の平面
図、第３図は従来の半導体装置のボンディングパッド部
の要部断面図、第４０は第３図の平面図でおる。
１・・・・シリコン基板、２・・・・フィールド酸化膜
、３・・・・ポリシリコン膜、４・・・・ＰＳＧ膜、４
ｍ ・・・・開孔部、５・・・・アルミニウム（ｈｔ
）膜、６・・・・絶縁保護膜、６＆・・・・開孔部。FIG. 1 is a sectional view of a main part showing a bonding pad section of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view of FIG. 1, and FIG. 3 is a main part of a bonding pad section of a conventional semiconductor device. The sectional view No. 40 is the plan view of FIG. 3. 1...Silicon substrate, 2...Field oxide film, 3...Polysilicon film, 4...PSG film, 4
m...Opening part, 5...Aluminum (ht
) membrane, 6...insulating protective film, 6 &... opening portion.
Claims (1)
内部配線のゲートと同時にポリシリコン膜を設置し、こ
のポリシリコン膜の上にリンを含有する二酸化硅素膜を
形成したうえ、該二酸化硅素膜のボンディングパッドの
箇所だけエッチングにより除去してその箇所にアルミニ
ウム膜をボンディングパッドとして設けたことを特徴と
する半導体装置。A polysilicon film is placed on the surface of the field oxide film formed on the silicon substrate at the same time as the gate of the internal wiring, and a silicon dioxide film containing phosphorus is formed on the polysilicon film. A semiconductor device characterized in that only a bonding pad portion is removed by etching and an aluminum film is provided in that portion as a bonding pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21312286A JPS6367753A (en) | 1986-09-09 | 1986-09-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21312286A JPS6367753A (en) | 1986-09-09 | 1986-09-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6367753A true JPS6367753A (en) | 1988-03-26 |
Family
ID=16633938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21312286A Pending JPS6367753A (en) | 1986-09-09 | 1986-09-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6367753A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5316976A (en) * | 1992-07-08 | 1994-05-31 | National Semiconductor Corporation | Crater prevention technique for semiconductor processing |
-
1986
- 1986-09-09 JP JP21312286A patent/JPS6367753A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5316976A (en) * | 1992-07-08 | 1994-05-31 | National Semiconductor Corporation | Crater prevention technique for semiconductor processing |
| US5424581A (en) * | 1992-07-08 | 1995-06-13 | National Semiconductor | Crater prevention technique for semiconductor processing |
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