JPS62144250A - Information processor containing error correcting circuit - Google Patents

Abstract

PURPOSE:To detect a fault through a parity check circuit by invalidating the parity correcting signal by a parity correction inhibiting circuit even though a decoder produces normally the data correcting signal and the parity correcting signal in case an error correcting circuit has a fault. CONSTITUTION:In case a decoder DEC has a fault when the data 1 containing no error and a check bit 2 are supplied to an error correcting circuit, the absence of errors is shown by an error detecting result signal 6 as long as a detecting circuit DET is normal despite the erroneous output of a data correcting signal 5 and a parity correcting signal 4. Then the signal 4 is invalidated by a parity correction inhibiting circuit. Thus the foul relation is defined between the correction data 8 and a parity bit 9 since the error of data is corrected by a data correcting circuit COR. Then an error is detected by a parity check circuit PC.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device having an error correction circuit.

[Conventional technology]

Conventionally, an error correction circuit is often added to information processing apparatuses as one means for achieving high reliability. In particular, for the main memory, an error correction circuit such as an Ebit error correction 2-bit error detection code is generally employed.

In an information processing device having such an error correction circuit, the access time is delayed by the delay time during which the error correction circuit operates. As a method for minimizing this access time delay, there is an information processing apparatus disclosed in Japanese Patent Publication No. 53-39293, for example.

According to this conventional information processing device, when the error correction circuit is able to determine the presence or absence of an error, if there is no error, a synchronization signal for information (data) is generated at that point and the information is set in the information register. On the other hand, when there is an error, a synchronization signal is generated when the error correction of the information is completed, and the information after the error correction is set in the information register.

That is, by controlling the synchronization signal for setting information in the information register to be delayed only when there is an error, the access time when there is no error is shortened.

[Problem that the invention attempts to solve]

Such conventional error correction circuits have the disadvantage that errors cannot be detected even if incorrect information is transferred due to a single failure of the error correction circuit. For example, the aforementioned Special Publication No. 53-3929
As shown in Figure 2 of Publication No. 3, when the information to be inspected includes a 1-bit error and the error signal 5 output from the detection circuit DET is mistaken as having no error, the timing selection circuit TSEL outputs a synchronization signal. T, and information containing an error is set in the information register IR. At this time, since there is no means to detect that incorrect information has been set in the information register R, there is a problem in that the information register R operates as if normal information had been set.

An object of the present invention is to provide an information processing apparatus having an error correction circuit that can detect errors even if a failure occurs in the error correction circuit as described above.

[Means for solving problems]

The information processing device of the present invention includes a syndrome generation circuit that inputs information to be inspected (data and check bits) and generates a syndrome, a data correction signal for correcting error bits from the generated syndrome, and a syndrome generation circuit that generates a syndrome from the data. a decoder that generates a harness correction signal for correcting the parity bits to be detected; a detection circuit that checks whether there is an error in the information under test based on the syndrome; and harness correction when the detection circuit does not detect an error. a crit correction inhibition circuit that invalidates the signal; a data correction circuit that inverts the error billatra in the data by the data correction signal; /? from the IJ tee correction prohibition circuit? an error correction circuit including a parity generation circuit that inverts a parity bit in response to a parity inversion signal; a data register that stores data from the data correction circuit; and a node that stores the parity bit from the parity generation circuit. It has a criticality register, a timing generation circuit that generates a timing signal for storing information in these registers, and a consistency check circuit that performs a FIJ check on the contents of the data register and the parity register.

〔Example〕

Next, embodiments of the invention will be described with reference to the drawings. FIG. 1 is a block diagram of an information processing device showing an embodiment of the present invention, including an error correction circuit and a timing generation circuit T.
G, data register DR, parity register PR, and parity check circuit PC.

Here, the error correction circuit includes a syndrome generation circuit SG, a decoder DEC, a detection circuit DET, a nopity correction inhibition circuit, a data correction circuit COR, and an i4ity generation circuit PC.

When the information to be inspected consisting of data 1 and check bit 2 is input, syndrome 3 is output from syndrome generation circuit SG. In parallel with this, the harity generation circuit PG generates a pulse (I) f (bit 9) for data 1. Using the syndrome 3, the detection circuit DET tests the information under test for errors and outputs an error test result signal 6.

Furthermore, when there is an error in the data 1 of the information to be inspected due to syndrome 3, the decoder DEC first corrects the error bit using the data correction signal 5 for correcting the error bit. A parity correction signal 4 for correcting the parity bit 9 generated by the PG is output. This iR+) tee correction signal 4 is ij
The error detection result signal 6 is input to the parity correction inhibition circuit and is controlled to be valid when an error is detected in the error detection result signal 6, and is output as a parity inversion signal 7. IJ tee generation circuit P
Supplied to G.

When an error bit is pointed out by the data correction signal 5, the data correction circuit COR inverts the error bit and sends corrected data 8 to the data register DR. Further, when the solitary generation circuit PG is instructed to invert by the solitary inversion signal 7, it inverts the parity bit that has already been generated for data 1 and sends the parity bit 9 to the parity register PR.

The timing generation circuit TG is a circuit that generates a timing signal 10 for setting data 8 and nocriticity bit 9 in the data register DR and nocriticity register PR. The information set in the data register DR and parity register PR is checked by the correctness check circuit PC, and if there is an error, a parity error signal 11 is sent.
is output.

Assuming that a failure occurs in the decoder DEC when the information to be inspected that does not contain errors is input to the error correction circuit, even if the data correction signal 5 and the zzIJT correction signal 4 are output in error, it will not be detected. If the circuit DET is normal, the error detection result signal 6 indicates no error, and the data is incorrectly corrected by the data correction circuit COR because the -P IJ tee correction signal 4 is invalidated by the crit correction inhibition circuit. Data 8 and harness bit 9 have an incorrect relationship, and an error is detected by the crit check circuit PC.

Furthermore, when the information to be tested containing an error is input to the error correction circuit, if a failure occurs that makes it impossible for the test circuit DET to detect an error, the decoder DEC outputs the data correction signal 5 and the parity correction signal 4. In order for the parity correction signal 4 to be invalidated by the correction inhibition circuit, t9
In the 1J tee generation circuit PG, /'Pritibi, g is not inverted. Therefore, data register DR and parity register PR
Is there an invalid A in the information set to ? Since the IJ bit is added, parity errors can be detected by the parity check circuit PC.

[Effects of the Invention] As explained above, the present invention is capable of detecting faults in the case where a fault occurs in the error correction circuit, for example, in a state where the information under test contains an error, and the error detection result of the detection circuit shows no error. When this occurs, even if the decoder normally generates the data correction signal and the harrity correction signal, the harrity correction inhibition circuit invalidates the A' IJ ity correction signal, thereby adding an illegal harrity bit to the data. Therefore, it is possible to detect failures using a parity check circuit.

Similarly, even if the detection circuit does not detect an error υ in a state where there is no error in the information under test, but an incorrect data correction signal and parity correction signal are generated due to a decoder failure,... +) By disabling the error correction signal with the tee correction prohibition circuit, it is possible to detect failures with the error tee check circuit.

That is, even if a fault occurs in the error correction circuit, the fault can be detected, and it is possible to prevent erroneous data from being transferred as if it were normal data. Moreover, the total amount of addition needed to realize this is extremely small.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing apparatus showing an embodiment of the present invention. 1.2...M Test information, 3...Syndrome, 4
. . . Nokriti correction signal, 5 . . . Data correction signal,
6...Error detection result signal, 7...Critique inversion signal, 8...Correction data, 9...Parity bit, 1
0...Timing signal, 11...Parity error signal.

Claims (1)

[Claims] (1) A syndrome generation circuit that generates a syndrome by inputting information to be inspected consisting of data and check bits, and a data correction signal for correcting error bits from the generated syndrome and a parity bit generated from the data. a decoder that generates a parity correction signal for correction; a detection circuit that detects the presence or absence of an error in the information under test based on the generated syndrome; and a detection circuit that invalidates the parity correction signal when the detection circuit does not detect an error. a parity correction prohibition circuit that inverts error bits of data in the information under test using the data correction signal; and a parity generation circuit that inverts parity bits using a parity inversion signal from the parity correction prohibition circuit. a data register that stores data from the data correction circuit; a parity register that stores parity bits from the parity generation circuit; and a parity check circuit for these stored data and parity bits. and a timing generation circuit that generates timing signals for storing data and parity bits in the data register and the parity register.