JPH01273450A - Test system for data error detecting circuit - Google Patents

Abstract

PURPOSE:To test detection of a data error in a parity confirming circuit by providing a means able to add a parity causing a simulated error data to a parity addition circuit of a data error detection circuit. CONSTITUTION:The parity addition circuit 1 is a circuit adding a parity bit to the data at the data transmission side and incorporates a circuit able to add the parity causing simulated error data. The parity addition circuit 1 executes whether a correct parity bit is added to a data of a data line 3 or a parity causing an error data by the control of a CPU 4 and a parity confirmation circuit 2 confirms whether or not the parity bit added to the data line 3 is correct. That is, an error data is sent simulatingly by the parity addition means 1 and tests whether or not the error is detectable by the data reception side. Thus, it is tested that the data error is detected by the parity confirmation circuit 2 of the data error detection circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a testing method for electronic circuits, specifically data error detection circuits.

[Conventional technology]

A parity check used to detect data errors in data processing is performed using parity bits added to each predetermined information unit (for example, word, etc.).

The data error detection circuit for parity check has a parity adding circuit on the data sending side and a parity checking circuit on the data receiving side. ,
Using the added parity bit, a parity check circuit checks whether a data error has occurred, thereby detecting an error that may occur during data transmission.

For example, in the case of even parity, "1" or "10" is added as a parity bit for checking so that the number of focus points representing "l" is always an even number, and on the receiving side, including that parity bit, It is determined whether the number of "1"s is an even number, and thereby it is possible to check for data errors that may occur during data transfer.

[Problem to be solved by the invention]

However, if such a data error detection circuit itself functions normally, it is useful for maintaining the quality of data transmission as a means of detecting data errors, but in the unlikely event that the data error detection circuit malfunctions, For example,
Even though a data error has occurred, it may be determined that no error has occurred, so it is important to check whether the data error detection circuit itself is functioning normally, that is, if there is no data error, the data In addition to being able to detect that no errors have occurred, if a data error that was assumed to occur during data transmission actually occurs, can the parity check circuit reliably detect it as a data error? It is extremely important to check whether the information is correct or not in order to ensure credibility.

An object of the present invention is to provide a data error detection circuit test method that can actually test whether a parity check circuit of a data error detection circuit can detect data errors.

[Means to solve the problem]

As a means for detecting data errors on a data line, the present invention uses a parity adding circuit that adds a parity bit to the data on the data sending side, and uses the added parity bit on the data receiving side to detect when a data error occurs. This is a test method for a data error detection circuit that has a parity check circuit to check whether the data is correct or not, and the parity addition circuit has a means for adding parity to pseudo-erroneous data. , the data error detection circuit is tested by sending error data in a pseudo manner using the parity adding means and testing whether the error can be detected on the data receiving side.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

As shown in FIG. 1, the data error detection circuit test method according to the present invention uses parity addition that can add parity to the data sending side to pseudo-error data as a means for detecting data errors in the data line 3. Circuit 1 and...
It has a parity check circuit 2 that checks whether a data error has occurred in the parity added to the data receiving side.

The parity addition circuit 1 is a circuit that adds a parity bit to the data on the data sending side, and in addition to this, it is a parity addition circuit that has a built-in circuit that can add parity to pseudo-error data. be.

The parity adding circuit 1 and the parity checking circuit 2 are connected to the data line 3 and also to the CPU 4.

The parity addition circuit 1, which has a built-in circuit that can add parity to pseudo-error data, adds a correct parity bit to the data on the data line 3, or adds parity to the data to make it error data. The parity checking circuit 2 checks whether the parity bit added to the data line 3 is correct, and the result can be read by the CPU 4.

The above-mentioned addition processing in the parity addition circuit 1 is performed, for example, in the case of even parity as described above, by adding "l" or "0" so that the number of "l" is always an even number, thereby correcting the parity bit. can be added to the data, and on the other hand, when making it erroneous data,
This can be done by adding "1" and "0" so that the number of "1"s is an odd number, and the CPU 4 controls which of these addition processes is performed by the parity addition circuit 1.

In this way, as means for detecting data errors on the data line 3, the parity adding circuit l adds a parity bit to the data on the data sending side, and the parity bit added on the data receiving side is used to detect data errors. In a data error detection circuit having a parity check circuit 2 for checking whether a error has occurred, the parity addition circuit 1 includes a circuit that can add parity to pseudo-erroneous data. send out,
The data error detection circuit is tested by testing whether the error can be detected on the data receiving side.

In the above configuration, the data error detection circuit can be tested as follows.

First, the CPU 4 controls the parity addition circuit 1 to add parity bits that would result in erroneous data, and then reads out the parity confirmation result from the parity confirmation circuit 2.
Confirm that the data is incorrect. Next, after controlling the parity addition circuit 1 to add the correct parity bit, the parity confirmation result of the parity confirmation circuit 2 is read out, and the parity addition circuit and the parity A test of the data error detection circuit including the verification circuit is performed.

In this way, it is possible to easily check whether the data error detection circuit is functioning as expected.

When the parity adding circuit cannot add parity that makes the data pseudo-erroneous as described above, the parity checking circuit can simply check that no data errors are detected.

In other words, in conventional data error detection circuits, the parity addition circuit did not include a circuit that could add parity to pseudo-erroneous data, so this was tested to check the functionality of the data error detection circuit. Even if you try to do so, in that case you could only test that the parity check circuit does not detect data errors;
In other words, in the conventional data error detection circuit testing method, the data error detection circuit is tested because the parity addition circuit does not include a circuit that can add parity that pseudo-errors data. While sometimes it is not possible to test whether the parity check circuit 2 detects data errors, in the case of the above configuration, it is possible to test whether the parity check circuit 2 detects data errors, and this can be done easily and reliably. , can contribute to improving credibility.

〔Effect of the invention〕

As explained above, according to the present invention, by having a means for adding parity to the parity adding circuit of the data error detection circuit to make it pseudo error data, the parity checking circuit can be used when testing the data error detection circuit. This has the effect of making it possible to test whether data errors can be detected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. 1...Parity addition circuit 2...Parity check circuit 3...Data line 4...CPU

Claims (1)

[Claims] (1) As a means of detecting data errors on the data line, a parity adding circuit adds a parity bit to the data on the data sending side, and the added parity bit is used on the data receiving side to detect data errors. A test method for a data error detection circuit having a parity checking circuit for checking whether data has been erroneously detected, the parity adding circuit having means capable of adding parity to pseudo-erroneous data. A data error detection circuit characterized in that the data error detection circuit is tested by sending pseudo error data using the parity addition means and testing whether the error can be detected on the data receiving side. Test method.