JPH04109340A - False fault generating circuit - Google Patents

Abstract

PURPOSE:To surely execute the evaluation of all parity check circuits by inverting a parity bit value outputted from a register corresponding to the parity check circuit concerned out of plural parity check circuits at the time of deciding the generation of a false fault detected by the parity check circuit itself. CONSTITUTION:It is defined that the code numbers of parity error detecting circuits 26, 27 are respectively '1' and '2', the circuit 26 always detect a parity error and the circuit 27 is allowed to detect a parity error only when a specific condition is satisfied. The polarity of the parity bits of parity errors 22, 23 respectively corresponding to the circuits 26, 27 is respectively intermittently or fixedly inverted by exclusive OR circuits 24, 25 in accordance with a code number specified by a diagnostic processor 2. Consequently, the evaluation of all the parity error detecting circuits 26, 27 can surely be executed and time required for the evaluation can be shortened.

Description

TECHNICAL FIELD The present invention relates to a pseudo fault generation circuit, and more particularly to a pseudo fault generation method for generating a pseudo parity error when evaluating a parity error detection function of an information processing device.

Prior Art Conventionally, this type of pseudo failure generation method involves stopping the clock of an information processing device using a diagnostic processor, setting an inverted value for any one bit of a register having a parity check function using a scan operation, etc. There is a method of starting the clock after that and causing a failure due to a parity error.

Another method is to connect the signal line of the logic package to the power supply or ground and force the signal to the "1" or "O" level, thereby causing a failure due to a parity error.

In such a conventional pseudo-failure generation method, if the parity error information is set using a scan operation by a diagnostic processor, if the parity error detection circuit is a circuit that always detects parity errors, the scan operation will detect a parity error. A failure occurs when setting the information.

However, if the parity error detection circuit is a circuit that detects a parity error only when a certain condition is met, and the value set by the scan operation is updated when the parity check condition is met. , there is a problem that it is not possible to cause a failure.

In addition, in the method of generating a fault by clamping the signal line of the logic package to the "1" or "0" level, in the case of a logic package in which a highly integrated LSI is mounted, a pseudo fault is generated inside the LSI. The problem is that I can't.

In the above case, there is a problem in that it is not possible to fully evaluate the parity error detection function in the information processing device, and it is necessary to consider the setting conditions for generating a pseudo failure.

Purpose of the Invention The present invention has been made in order to eliminate the problems of the conventional ones as described above, and it is possible to reliably evaluate a parity error detection circuit and to reduce the time required for evaluation. The purpose is to provide a generation circuit.

Configuration of the Invention A pseudo-failure generating circuit according to the present invention is a pseudo-failure generating circuit for an information processing device including a plurality of parity check circuits each performing a parity check on a value of a corresponding register, wherein each of the plurality of parity check circuits a determining means for determining whether or not a pseudo failure to be detected in the own circuit occurs based on a signal from a host device;
The present invention is characterized by further comprising an inverting means for inverting the value of the parity bit of the register in accordance with a constant result.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a register 10 of a processor holds the execution address of a microprogram when a pseudo fault, parity, or 1 error occurs, or a timer value.

A flip-flop (hereinafter referred to as F/F)]1 holds a selection signal to a selector]7, and a register 12 holds an execution address of a microprogram.

The F/F 14 holds a selection signal output to the selector 29 for selecting whether the parity error, which is a pseudo failure, is an intermittent failure or a fixed failure.

The register 15 holds the code number of the parity error detection circuit 2627, and the F/F 16 holds a pseudo failure occurrence mode indicating whether a pseudo failure is generated.

The selector 17 selects one of the execution address held in the register 12 and the value of the timer 13 according to the selection signal held in F/Fil, and sends it to the comparison circuit 19.

The decoder circuit 18 decodes the code numbers of the parity error detection circuits 26 and 27 held in the register 15,
The decoded signal is output to an AND circuit (AND) 20.21.

The comparison circuit 19 compares the value held in the register 10 and the value selected by the selector 17, and sends the comparison result to the F/F.
28 and selector 29.

The AND circuits 20 and 21 perform an AND operation between the pseudo fault occurrence mode held in the F/F 6, the decoded signal from the decoder circuit 8, and the value selected by the selector 29, and output the result of the operation. It is output to exclusive OR circuits 24 and 25.

Exclusive OR circuits 24.25 perform exclusive OR of the operation results of AND circuits 20.21 and the parity bits of the values held in registers 22.23, and send the operation results to parity error detection circuits 26.25. Output to 27.

Each of the parity error detection circuits 26 and 27 has a code number set, and when the pseudo fault occurrence mode of the F/F 16 indicates that a pseudo fault will occur, the calculation result of the exclusive OR circuits 24 and 25 A parity check is performed on the values of registers 22 and 23 using the value as a parity bit.

When the comparison circuit 19 detects a match, the F/F 28 holds "1" until it is reset by the diagnostic processor 2.

The selector 29 selects one of the comparison result of the comparator circuit 19 and the value of the F/F 28 in response to the selection signal held in the F/F 1.4, and outputs it to the AND circuit 20.21.

The operation of one embodiment of the present invention will be explained using FIG.

In one embodiment of the present invention, the code number of the parity error detection circuit 26 is 1', and the code number of the parity error detection circuit 27 is 2'.

It is also assumed that the parity error detection circuit 26 is a circuit that actually detects parity errors, and the parity error detection circuit 27 is a circuit that detects parity errors only when a certain specific condition is satisfied.

First, when a parity error is generated in the parity error detection circuit 26, when the clock of the processor 2 is stopped, the diagnostic processor 2 sends a “1” signal to the F/F 16.
is set, and the pseudo-failure occurrence mode is held in the F/F 16.

Next, the diagnostic processor 2 sets the code number 1'' of the parity error detection circuit 26 in the register 5, and selects a condition for generating a parity error, which is a pseudo failure.

When a parity error, which is a pseudo failure, is caused by the output value of the register]2 that holds the execution address of the microprogram, the diagnostic processor 2 sets F/F]1 to “0”.
” is set.

F/F], by setting 1 to "0", the selector 17 selects the execution address held in the register 12.

The register 10 from the diagnostic processor 2 holds the large line address of the microprogram in which it is desired to cause a pseudo failure.

Finally, it is selected whether the pseudo fault to be generated is an intermittent fault or a fixed fault, but since the parity error detection circuit 26 always detects parity errors,
F/F from diagnostic processor 2 to select intermittent fault
] Set “0” to 4.

As a result, the two selectors select the comparison result of one comparison circuit and output it to the AND circuits 20 and 21.

If processor 1 is started up in this state, only when the execution address held in register 2 and the execution address held in register 10 match, the output of one comparison circuit becomes ``1'', and the selector The output of 29 becomes "1".

Therefore, all inputs to the AND circuit 20 are "1",
The polarity of the parity bit of the register 22 is inverted by the exclusive OR circuit 24, and the inverted parity bit is input to the parity error detection circuit 26.

At this time, if the parity error detection circuit 26 operates normally, a parity error is detected by the inverted parity bit.

Next, when the parity error detection circuit 27 generates a parity error, the diagnostic processor 2 sets F/F 1.6 to "1" while the clock of the processor 2 is stopped, and the pseudo-failure occurrence mode is activated. is F/F 1
6.

Subsequently, the diagnostic processor 2 sets the code number 2' of the parity error detection H1 circuit 27 in the register 15, and selects a condition for generating a parity error which is a pseudo fault.

Here, when the output value of the timer 13 causes a parity error, which is a pseudo failure, the diagnostic processor 2 sets F/Fll to "1".

By setting "1" in the F/F 11, the selector 17 selects the output value of the timer 13.

The register 10 from the diagnostic processor 2 holds the value of a timer at which a parity error, which is a pseudo failure, is to be generated.

Finally, a selection is made as to whether the pseudo fault to be generated is an intermittent fault or a fixed fault, but the parity error detection circuit 27 only detects parity errors when certain conditions are met; Since no errors are detected,
F/F from diagnostic processor 2 to select fixed fault
] 1'' is set in 4.

As a result, the selector 29 selects the value held in the F/F 28 and outputs it to the AND circuit 20.21.

If processor 1 is started up in this state, timer 13
When the value of the register matches the value of the timer held in register]O, the output of one comparison circuit becomes "]', and F/F2
8 continues to be held as “1”, and selector 2
Since the output of 9 becomes "1", the AND circuit 21 also becomes "1".
continues to be output, and the exclusive OR circuit 25 outputs the register 2.
In this state, the polarity of the parity bit 3 is fixedly inverted, and the inverted parity bits are inputted to the parity error detection circuit 27 at two points.

At this time, if the parity error detection circuit 27 operates as iF-', a parity error is detected by the inverted parity bit when the condition for detecting a parity error is established.

In this way, a code number is set for each parity error detection circuit 2627, and the parity error detection circuits 26 and 27 are set in accordance with the code number instructed by the diagnostic processor 2.
Parity bits of registers 22 and 23 corresponding to each)
The exclusive OR circuit 24 intermittently or fixedly changes the polarity of
．． By inverting at 25, it is possible to reliably evaluate all the parity error detection circuits 26 and 27, and the time required for evaluation ftjf can be shortened.

As described in detail, according to the present invention, when it is determined that a pseudo failure detected in one of a plurality of parity check circuits will occur, the value of the parity bit of the register corresponding to the parity check circuit is By inverting , the tV value of the parity check circuit can be reliably performed and the time required for evaluation can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Explanation of symbols of main parts 1...Processor 2...Diagnostic processor] 2゜15...Register 11, . 14゜1.6.28...Flip-flop 1'B...
... Timer 17.29 ... Selector 18 ... Decoder circuit 19 ... Comparison circuit 21 ... AND circuit 23 ... Register 25.・・・・υ[Ground level OR circuit 27... Parity error detection circuit 20゜24゜26゜Applicant Ibaraki NEC Co., Ltd. 1

Claims (1)

[Claims] (1) A pseudo-failure generating circuit for an information processing device including a plurality of parity check circuits each performing a parity check on the values of corresponding registers, wherein each of the plurality of parity check circuits receives a signal from a host device. A determining means for determining whether or not a pseudo failure to be detected in the own circuit occurs according to the method, and an inverting means for inverting the value of the parity bit of the register according to the determination result of the determining means. A simulated failure circuit.