JPS62119657A - Dma chain control system - Google Patents

Abstract

PURPOSE:To add commands with a single and simple procedure independently of the state of a channel to a chained DMA command by providing a final pointer pointing a final discriptor to the channel. CONSTITUTION:The final pointer pointing final discriptors 4-1, 2 is provided to the channel, a new discriptor to be added is prepared, and when processing commanded by a chained discriptor is executed upon the receipt of a notified chain restart command, the chain restart command is neglected, the new discriptor is processed, and when the processing is waiting for the position of the discriptor pointed by the final point register 5, after chain bits 2-1-3 provided in the final discriptor pointed in the final point register are on '1' level, the processing commanded by the discriptor provided newly is controlled for the execution.

Description

[Detailed Description of the Invention] (Summary) D that performs control by referring to chained descriptors
In the MA chain control method, prepare a new descriptor to be added, and process the new descriptor if processing is currently being executed in response to a chain restart command issued to the channel;
If the machine is on the other hand, after confirming that the chain bit set in the descriptor pointed to by the final point register is "1", execute the process instructed by the newly set descriptor. It is disclosed to do so.

[Industrial application field]

The present invention provides a final pointer that points to the final descriptor in the channel, prepares a new descriptor to be added, and controls execution of the newly chained descriptor in response to a notified chain restart command. This relates to a DMA chain control method.

[Conventional technology]

Conventionally, as shown in FIG. 4, as a control method for a channel, there is a method in which descriptors (descriptors indicating operations to be performed by a channel control section) are configured in a chain shape to perform DMA processing. This type of control method is based on a certain descriptor, for example, DM in descriptor (1) l 4-1.
After transferring the data stored in the buffer (11) pointed to by the A descriptor 13-1 to the 110 device, if the chain bit 12-1 provided in the descriptor (1114-1) is "1", the next It executes the process instructed by the descriptor 14-2 pointed to by the descriptor 11-1.

[Problem that the invention seeks to solve]

At this time, after executing the DMA process instructed by the descriptor (2114-2) shown in FIG. The operating state of the DMAC (DMA control unit) 17 is checked, and if the final descriptor (descriptor (2114-2)) has been processed, a new descriptor 13114 is
There was a problem in that it was necessary to register -3 as the last descriptor in the DMAC 17 and start the DMAC. Furthermore, if the processing for the final descriptor has not yet been completed, the DMAC 17 and the host (C
In order to avoid conflict with the DMACl 7, the host 18 temporarily suspends the operation of the DMACl 7, and replaces the next descriptor 11-2 provided in the descriptor (2114-2) with a new descriptor (pointing at 3114-3). write the address to be used and set chain bit 12-2 to “1”.
”, and the DMAC 17 had to be restarted.

[Means for solving problems]

In order to solve the above problems, the present invention provides a final pointer that points to the final descriptor in the channel, prepares a new descriptor to be added, and uses the notified chain restart command as an opportunity to restart the chain. If the process specified by the descriptor is currently being executed, the chain restart command will be ignored and the new descriptor will be processed, while if the process is currently being executed at the descriptor pointed to by the final point register. After confirming that the chain bit provided in the final descriptor pointed to by the final point register is "1", the chain is controlled to execute the process specified by the newly provided descriptor. This makes it easy to add new descriptors to existing descriptors.

Means for solving the problems will be explained using the configuration of one embodiment of the present invention shown in FIG.

In FIG. 1, a descriptor (
1) 4-1 is composed of a next descriptor 1-1, a chain bit 2-1, and a DMA descriptor 3-1. The same applies to descriptor (2) 4-2. Furthermore, descriptor (3) 4-3 is to be newly added. Each of these descriptors i
ll Data stored in buffers (1), (2), and (3) pointed to by DMA descriptor 3-1.3-2.3-3 provided in 4-1 to 4-3. is transferred by DMA to, for example, the 110 device.

Next descriptors it, 1-2, 1-3 each store an address pointing to what is to be executed next.

Chain bits 2-1.2-2.2-3 each represent the state of whether or not what is pointed to by next descriptors 1-11-2 and -3 should be processed.

The final point register 5 points to the last descriptor to be executed.

The DMAC 7 executes processing related to various DMA controls.

[Effect]

The configuration explained using Fig. 1 is adopted, and the host (CPU
)8 tries to add a new descriptor,
First, for example, the descriptor (314-
3 is prepared in the memory 6.

Second, the address pointing to the newly provided descriptor (314-3) is stored in the next descriptor 1-2 in the final descriptor (214-2) pointed to by the final point register 5.

Third, set the chain bit 2-2 provided in the final descriptor (2+4-2) to 1''.

Fourth, the host 8 issues a chain restart command to the DMAC 7.

Fifth, D receives notification of the chain restart command.
If the MAC 1 is executing the process specified by the final descriptor or a descriptor connected by the chain one sequence before it, the MAC 1 ignores the issued chain restart command. This is still the final descriptor e.g. descriptor f214-2
Since the processing of the final descriptor (214-2) has not been completed, the added descriptor (314-3 is the final descriptor (214-2).
This is because it is processed next to -2. On the other hand, the process specified by final descriptor (2) 4-2 is completed,
When on standby, the final point register 5 holds the address of the final descriptor (2) 4-2, so the chain bit 2 provided in the final descriptor f214-2 pointed to by this final point register 5 is After confirming that -2 is "1", the process specified by the descriptor f314-3 pointed to by the address stored in the next descriptor 1-2 is executed.

The steps described above make it possible to easily add new descriptors.

〔Example〕

FIG. 1 is a block diagram of one embodiment of the present invention, and FIGS. 2 and 3 are operational charts of the present invention.

The operation of the configuration shown in FIG. 1 will be explained in detail using the flowcharts shown in FIGS. 2 and 3.

■ in FIG. 2 indicates a state in which a new descriptor is prepared. This indicates that the new descriptor to be added to the chain in the memory 6 shown in FIG. 1, for example descriptor f314. -3 is prepared as shown in the figure.

In the figure, ■ indicates a state in which the address field of the descriptor following the final descriptor is used as the address of a new descriptor. This is the last descriptor in Figure 1 (2+ and the next descriptor 1- provided in 4-2).
Descriptor f at the address pointed to by 2
314-3.

■ in the figure indicates that the chain focus of the final descriptor is ON.
Indicates the state in which This is the final descriptor (21
4-2 shows a state in which chain bit 2-2 provided in 4-2 is set to "1".

In the figure, ■ indicates a state in which the host 8 issues a chain restart command to the DMAC 7.

■ in FIG. 3 indicates a state in which the processes of ■ to ■ in FIG. 2 have been completed.

0 in the diagram means that the chain visibility of the final descriptor is ON.
Indicates the state in which it is determined whether or not. This is the chain bit 2 provided in descriptor (2) 4-2 in Figure 1.
This means determining whether or not -2 is ON. YE
In the case of S, 0 in the figure is executed. The reason why the final descriptor checks whether the chain bit is ON or not is because the host 8 is delayed in issuing the chain restart command to the DMAC 7, and the descriptor 13) 4-3
This is because there is a possibility that a chain may be performed by mistake when the process progresses to the point where the final point register 5 points to the descriptor (314-3). 3 is OFF, r) MA processing is stopped).

In the figure, ◎ indicates a state in which the contents stored in the field of the next descriptor 1-2 provided in the descriptor (2+4-2) are read.
New descriptor added after -2 (3) 4
This means reading the address pointing to -3.

■ in the figure indicates a state in which processing is performed for the next descriptor. This is the newly added descriptor (3) 4
-3 means to execute the process specified.

In the figure, [phase] indicates a state in which the channel is waiting for a chain restart command.

In the figure, [phase] indicates a state in which a chain restart command is notified to the channel. Then, repeat the steps below @ in the figure.

As explained above, the final point register 5 that points to the final descriptor is provided, the descriptor to be added is prepared, the address is set so that the final descriptor points to the added descriptor, and the chain bit is turned ON. After setting, the host 8 simply issues a chain restart command to the DMAC 7, and the DMAC 7 can process the newly added descriptor.

〔Effect of the invention〕

As explained above, according to the present invention, a final pointer pointing to the final descriptor is provided in the channel, a new descriptor to be added is prepared, and the chain is started by the notified chain restart command. If the process specified by the descriptor is currently being executed, the chain restart command will be ignored and the new descriptor will be processed, while if the process is currently being executed at the descriptor pointed to by the final point register. , after confirming that the chain bit provided in the final descriptor pointed to by the final point register is "1", the chain is controlled to execute the process instructed by the newly provided descriptor. Commands can be added to the DMA commands that have been sent using a single and simple procedure, regardless of the state of the channel.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of one embodiment of the present invention, FIGS. 2 and 3 are operational flowcharts of the present invention, and FIG. 4 is a conventional DMA
An explanatory diagram of the operation of the chain control method is shown. In the figure, 1-1 to 1-3 are the next descriptors, 2-1
to 2-3 are chain bits, 3-1 to 3-3 are DMA descriptors, 4-1 to 4-3 are descriptors, 5 is final point register, 6 is memory, 7 is DMAC, 8 is host (CPU) represents.

Claims (1)

[Claims] D that performs control by referring to chained descriptors.
In the MA chain control method, a next descriptor pointer (1) points to the next descriptor to be executed, a chain bit (2) indicating whether or not the next descriptor is chained, and a DMA descriptor that describes information to be processed. (3)
Prepare a new descriptor (4) to be added, each having a descriptor (4) with a final point register (5) pointing to the final descriptor, and chain this new descriptor (4). The next descriptor pointer (1) provided in the final descriptor is set to point to the new descriptor (4), and the chain bit (2) is set.
is set to "1" and a chain restart command issued to a channel triggers a process instructed by any chained descriptor to be executed, the chain restart command will be ignored. , processes the new descriptor, while waiting at the position of the descriptor pointed to by the final point register (5), A DMA chain control method is characterized in that after confirming that a chain bit (2) is "1", control is performed to execute a process instructed by a newly provided descriptor.