JPH04262449A - Data transfer system - Google Patents

Abstract

PURPOSE:To offer a data transfer system that is constituted of a simple circuit and that has high data transfer rate. CONSTITUTION:The data transfer system is equipped with a device specifying information storage means 14 for storing device specifying information WE that specifies a party device 13 or 12 that is a destination or source of data transfer, and a device control means 15 that uses a command of transfer request DREQ from CPU 11 for specifying one party device 13 or 12 specified by device specifying information WE for writing or reading data, and for specifying the other party device 12 or 13 that is either a source or destination of data transfer. Prior to data transfer, the CPU 11 writes device specifying information WE in device specifying information storage means 14, and when transferring data, by the control of CPU 11, address specifying is carried out for the other party device 12 or 13 and at the same time a command of transfer request DREQ is carried out for a device control means 15.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method for transferring data between two devices under the control of a CPU.

0002

2. Description of the Related Art Conventionally, methods for transferring data between two devices, such as memory and memory, memory and IO, or IO and IO, include a method that involves control by a CPU, and a method that uses DMA (direct memory access). There is a method according to

In the former method, data read from a transfer source device onto a data bus under the control of the CPU is temporarily stored in a register within the CPU, and the data stored in the register is transferred onto the data bus in the next write cycle. Write to the destination device.

That is, in this case, one data transfer is executed in two cycles: a read cycle and a write cycle.

[0005] The latter uses a dedicated controller (DMAC)
Data is transferred directly between two devices, away from the control of the CPU.

[0006]

However, the former method requires two cycles to transfer one data, so the transfer speed is slow.

[0007] In the latter method, reading and writing are performed in one cycle, so the data transfer speed is fast, but a dedicated controller is required for this purpose.
The circuit configuration was complicated and the cost was high.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a data transfer system with a simple circuit configuration and a high data transfer rate.

[0009]

[Means for Solving the Problems] In order to solve the above-mentioned problems, the method according to the invention of claim 1 is a data transfer method for transferring data between two devices under the control of a CPU, and in which the transfer destination or Device specification means is provided for storing device specification information for specifying one of the devices that is a transfer source, and for specifying the device based on the stored device specification information. device designation information is written in the device designation means, and at the same time, the device designation information is written to the device designation means, and an address designation and read or write command is given to the other device, which is the transfer source or the transfer destination, under the control of the CPU. A write or read command is given to the device specified by the means.

[0010] The method according to the invention of claim 2 includes a device specifying information storage means for storing device specifying information specifying one of the devices as a transfer destination or a transfer source, and a transfer request instruction from the CPU. , gives a write or read command to the device corresponding to the device designation information stored in the device designation information storage means, and gives a read or write command to the other device that is the transfer source or the transfer destination. device control means is provided, and prior to data transfer, the CPU writes device specification information in the device specification information storage means, and upon data transfer, the CPU controls whether the transfer source or At the same time as specifying an address for the other device, a transfer request command is issued to the device control means.

[0011]

[Operation] Prior to data transfer between devices, the CPU writes device designation information into the device designation information storage means.

[0012] The device control means writes data to the device corresponding to the device designation information when a transfer request command is received from the CPU, specifically, for example, when a memory access request signal becomes active. Alternatively, a read command is issued, and at the same time, a read or write command is issued to the other device. This allows data transfer between devices.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a data processing device 1 according to the present invention, and FIG. 2 is a timing chart when data is transferred from a memory 12 to an IO 13. In addition, in the figure,
Although the symbol "/" written before each signal name indicates that the signal is low active, the symbol "/" will be omitted in the following explanation.

The data processing device 1 is composed of a CPU 11, a readable/writable memory 12, an IO 13, an IO 14, and a memory controller 15, and an address bus 21, a data bus 22, and other control lines are connected between these. connected by.

The memory 12 stores programs to be executed by the CPU 11 and data necessary for the execution, and is selected by the MSEL signal and selected by the MR/MW
Reading or writing is designated by the signal.

[0016] IO13 and IO14 are for inputting and outputting data to/from the outside, and each G1
It is selected by the signal or G2 signal, and reading or writing is specified by the IR/W1 signal or the IR/W2 signal.

IO input/output to IO13 and IO14
Data is output to D1 and IOD2 even when the G1 signal or G2 signal is not active (when "H"), and can be read by an externally connected input/output interface (not shown). In this embodiment, IO13 and IO14 are capable of inputting and outputting 8-bit data, and IOD1 and IOD2 are also 8-bit each.

The IO 14 operates as a device specifying means or a device specifying information storage means in the present invention, and the content of the WE signal output from a specific bit (for example, the lowest bit) of the IOD 2, which is its input/output, is , corresponds to device specification information in the present invention. This WE signal is input to the memory controller 15, and during data transfer between devices, the memory controller 15
The device is specified based on the E signal.

The memory controller 15 directly controls these devices when the CPU 11 accesses the memory 12 or the IOs 13 and 14.

That is, when a DREQ signal indicating an access request to the memory 12 or IO 13, 14 is inputted from the CPU 11 to the memory controller 15, one of them is selected based on the address of the address bus 21. signal (MSEL signal, G1 signal, or G
2 signal) and designates reading or writing to the selected device based on the R/W signal.

[0021] Furthermore, when the memory controller 15 receives a signal for reading the memory 12, the IO1
4, and if the WE signal is active ("L") as shown in FIG. 2, the MSEL signal for selecting the memory 12 is activated ("L"). ), the G1 signal is made active (“L”) and the IR/W1 signal is made “L”. As a result, data read from the memory 12 and placed on the data bus 22 is sent to the IO13 in the same cycle.
will be written to. In other words, data transfer from the memory 12 to the IO 13 is performed in one cycle.

[0022] In order to make the WE signal of IO14 active, the bit corresponding to the WE signal of IO14 must be set to "L".
It is written in advance by the CPU 11 so that it becomes .

FIG. 3 is a flowchart showing the process of transferring data from the memory 12 to the IO 13.

First, the number of data to be transferred is set in a counter (step #11), and its start address is set (step #12).

The least significant bit of the IO 14 (the bit corresponding to the WE signal) is set to "L" (step #13). As a process for this purpose, for example, "0" is written to the IO14.

Data is read from memory 12 (step #14). At this time, data is simultaneously written to the IO 13 and transferred.

Decrement the counter (step #1
5) If the counter is not zero (No in step #16), increment the address (step #17)
, jump to step #14.

[0028] If the counter is zero in step #16,
Set the least significant bit of IO14 to “H” (step #18
), the process ends.

FIG. 4 is a diagram showing an example of a program for executing the flowchart of FIG. 3. In this program, 1000 bytes of data starting from address "A000H" are transferred from memory 12 to IO 13.

According to the embodiment described above, from memory 12 I
When data is transferred to the IO 13, data is written to the IO 13 at the same time as data is read from the memory 12, and therefore data is transferred only during the read cycle of the memory 12. This significantly reduces the time required for data transfer and increases the data transfer rate. Moreover, it can be realized at low cost with a simple circuit configuration without requiring a complicated dedicated controller such as a DMAC.

In particular, when the program shown in FIG. 4 is executed, the routine labeled "Retry" is repeatedly executed 1000 times. The long processing time-consuming instructions that were previously required for storage have been removed, resulting in a much faster data transfer rate.

In the above-mentioned embodiment, data was transferred only in the direction from the memory 12 to the IO 13. Next, an embodiment in which data is transferred in these directions will be described.

FIG. 5 is a block diagram of a data processing device 1a according to another embodiment of the present invention, and FIG.
Timing diagram when transferring data to 2, Figure 7 is IO
13 is a flowchart showing a process for executing data transfer from the memory 12 to the memory 12.

In the data processing device 1a, a gate 16 and a G3 signal for turning the gate 16 on and off are added to the data processing device 1 described above.

That is, the data bus 22 connected to the CPU 11 and the data bus 22a connected to devices such as the memory 12 are connected via the gate 16, and the G3 signal output from the memory controller 15 is connected to the data bus 22a connected to the memory 12 and other devices. Only when it becomes active (“L”), the gate 16 is turned on and these are connected to each other.

The G3 signal is normally transmitted from the memory 12 to the I
When data is transferred to P13, it is "L", and at this time, the data bus 22 and data bus 22a are connected, but when data is transferred from IO13 to memory 12, G3 is "L".
The signal becomes "H" and the data bus 22a is disconnected from the CPU 11. This prevents interference between the data output from the CPU 11 to the data bus 22 and the data output from the IO 13 to the data bus 22a.

To explain the operation of the data processing device 1a, as shown in FIG.
When a write signal to the memory 12 is received from the CPU 11, if the WE signal from the IO 14 is active, the MSEL signal for selecting the memory 12 is activated and the G1 signal for selecting the IO 13 is activated. Make it active. By this, I
The data read from IO13 and placed on the data bus 22a is written to the memory 12 in the same cycle.
3 to memory 12 is performed in one cycle. Therefore, data transfer speed is fast.

At this time, the CP signal is set in advance so that the G3 signal from the memory controller 15 to the gate 16 becomes "H".
It is set for the memory controller 15 by U11. Furthermore, setting the WE signal of the IO 14 active in advance is similar to the above.

In the flowchart shown in FIG. 7, the process of writing data to the memory 12 is performed in step #24, whereby the data read from the IO 13 is written to the memory 12.

[0040] In the process of writing data to the memory 12, a program written by an assembler as shown in FIG.
When the instruction is executed, the data in the register is transferred to the data bus 22. However, this data is not transferred to the data bus 22a because the gate 16 is off.

Note that the memory 12 in the data processing device 1a
Data transfer from IP 13 to IP 13 is performed in the same manner as described above with gate 16 turned on.

In the embodiment described above, memory 12 and I
An example was explained in which data was transferred between the memory 12 and other memories, and between the IO13 and other I/O13.
Data transfer can be performed between various devices such as O. In addition, although the IO14 is also used as a device specifying means or a device specifying information storage means,
A dedicated register or the like may also be used.

In the above embodiment, the memory controller 15 is a PLD (Programmable Logic Device).
c Device) or a hard circuit. The configuration of the data processing apparatuses 1 and 1a or their respective parts, the timing of data transfer, the processing contents or processing order of the flowchart, etc. can be changed in various ways other than those described above.

[0044]

According to the present invention, it is possible to provide a data transfer method with a simple circuit configuration and a high data transfer rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device according to the present invention.

FIG. 2 is a timing diagram during data transfer from memory to IO.

FIG. 3 is a flowchart showing a process for executing data transfer from memory to IO.

FIG. 4 is a diagram showing an example of a program for executing the flowchart of FIG. 3;

FIG. 5 is a block diagram of a data processing device according to another embodiment of the present invention.

FIG. 6 is a timing diagram during data transfer from IO to memory.

FIG. 7 is a flowchart showing a process for executing data transfer from IO to memory.

[Explanation of symbols]

11 CPU 12 Memory (device) 13 IO (device) 14 IO (device designation means, device designation information storage means)

Claims (2)

[Claims] Claim 1: A data transfer method for transferring data between two devices under the control of a CPU, which stores device specification information that specifies one of the devices that is a transfer destination or a transfer source, and stores the stored device specification. Device designation means is provided for designating the device based on the information, and prior to data transfer, the CPU
device designation information is written in the device designation means, and at the same time, the device designation information is written to the device designation means, and an address designation and read or write command is given to the other device, which is the transfer source or the transfer destination, under the control of the CPU. A data transfer method characterized by issuing a write or read command to a specified device using means. 2. A data transfer method for transferring data between two devices under the control of a CPU, wherein device specification information storage is provided for storing device specification information specifying one of the devices that is a transfer destination or a transfer source. and another device which, in response to a transfer request command from the CPU, issues a write or read command to a device corresponding to the device designation information stored in the device designation information storage means, and which is a transfer source or a transfer destination. device control means for instructing the device to read or write, and prior to data transfer, the CPU writes device designation information in the device designation information storage means, and the data transfer A data transfer method characterized in that, under the control of the CPU, an address is specified for the other device, which is a transfer source or a transfer destination, and at the same time, a transfer request command is issued to the device control means. .