JPS6146545A - Input and output instruction control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control system for transferring command information to a channel control device based on input/output commands executed by a central processing unit of a computer system.

Peripheral devices of many computer systems are connected to a central processing unit and a main memory of the main body of the computer system via a channel control device that controls one or more subchannels.

The channel control device receives control information constituted by input/output instructions executed by the central processing unit, and executes control such as data input/output of the subchannel specified by the control information.

[Conventional technology]

FIG. 2 is a configuration diagram of an example of a computer system, in which two central processing units (hereinafter referred to as CPUs) 1, two channel control units (hereinafter referred to as CHP) 2, and a main storage device 3 are used for system control. It is connected to device 4.

The CHP 2 holds information necessary for controlling each subchannel, and this information is stored using, for example, a part of the storage area of the main storage device.

Such an area is called, for example, the I10 system area,
It is fixedly allocated to CHP2 as a so-called hardware area that cannot be accessed directly from the program executed by CPU1.

The system control device 4 controls access from the CPUI and C) (P2 to the main storage device 3, and also controls the access between the CPU1 and C).
Controls information exchange between PUI and CHP2, between CHP2, etc.

When a program executed on the CPUI requires data transfer or other control regarding peripheral devices,
Issues input/output commands to send required command information to CHP2.

Commands belonging to input/output commands include a start l10 (S10
There are various types of instructions, with the 5IOF and 5IOF instructions being representative examples, and these instructions have conventionally been executed as described below.

For example, when issuing the 5IOF instruction, the program prepares a command control word (hereinafter referred to as cc-) that specifies the operation of the peripheral device in the main memory 3, and sets its memory address to the main memory. After storing the command address word (hereinafter referred to as CIV) at a specific storage address of the storage device, a 5lOF instruction is issued.

In the CPUI, when executing the 5IOF instruction, as shown in the timing diagram of FIG. 4, as the I10 request signal 10,
Command information including the operating code of the command and the subchannel address (peripheral device address) specified by the operand is sent to the system control device 4.

The system control device 4 selects the CHP and transmits the input/output control information together with the control signal and the source CPU number to the CHP 2.
It is relayed to the timing shown as information 11.

CHP2 is the C/C at a specific memory address determined by the CPU number.
V is read out, the CCU address, etc. are stored in the I10 system area, and a series of other processes are executed during time 12. Thereafter, the end signal 13 is returned together with the resulting condition code (hereinafter referred to as CC), so the system control device 4 relays it to the source CPUI as information@14.

The CPUI sets the CC in a predetermined register and completes the execution of the instruction.

[Problem that the invention seeks to solve]

As is clear from the above explanation, the CP is used for the period from time 15 to time 16 in FIG. 4 for the execution of input/output instructions.
The UI will be occupied.

Since this period includes information transfer between devices, there is a problem that it takes a relatively long time, and as the speed of the CPU 1 increases, this problem tends to become more widespread.

[Means for solving problems]

The above problem arises in a computer system that includes a central processing unit and a channel control device that operates by receiving command information based on input/output instructions executed by the central processing unit. The buffer has means for receiving command information from the central processing unit, and the central processing unit transfers predetermined command information based on the input/output command to the buffer and temporarily executes the input/output command. is solved by the input/output command control scheme of the present invention, which is configured to be completed by executing the transfer.

[Effect]

During the time period 120 in FIG. 4, which accounts for most of the time that the CPU
Generally speaking, the processing performed by the controller differs depending on the type of input/output instruction, but it can be roughly divided into two types.

The first type of instruction, such as the 5IOF instruction, is such that at this point, only the control information based on the instruction is transferred to the CHP2, and its execution may be performed asynchronously with the execution of the CPUI instruction. .

In the second type, information is exchanged with peripheral devices such as command transfer during the period of time 12, such as with the 510 instruction.
This is a so-called synchronous type, in which the instruction is completed when the result is obtained.

Therefore, a buffer is provided in the CHP 2 for the purpose of holding command information received from the CPUI, and in the case of the first type of command, execution of the input/output command is completed when the command information is transferred to the buffer. By doing so, even if the CHP2 is executing other processing, the CPUI can finish executing the input/output command.

In this case, for example, before transferring command information, the CPU
refers to the information of the required subchannel in the I10 system area, determines whether the subchannel is in a state where the command can be executed, and if possible, transfers the CC-memory address and other control information in the CAW to the subchannel. Store in the area.

Based on the result and the command information transfer result, the CPU can also generate a CC by itself.

These CPU processes can also be performed in parallel while CHF2 is executing other processes, so the CPU, which was previously idle, can be used in parallel.
This results in efficient use of I time and improves the overall performance of the system.

〔Example〕

FIG. 1(a) is a detailed block diagram of the configuration of an embodiment of the present invention, and FIG. 1(b) is a timing diagram of input/output command execution in this embodiment.

In executing input/output instructions, the CPUI uses C
Seeing the buffer full signal sent from HP 2, CH
If it is determined that there is space in the command information reception buffer of F2, the process proceeds.

In that case, first access the area of the subchannel in the I10 system area using the subchannel address specified by the operand of the input/output instruction, check the status of the subchannel, and check whether the subchannel can execute the command. If it is not, for example, at this stage, the process branches to a process such as setting a predetermined CC and ending the instruction execution.

If the command is executable, preprocessing (see Figure 1 (b ) After performing step 50), the transfer of command information is started.

The CPUI transfers the command information and request type onto the address bus 20 to the registers 21 and 22 of the system control device 4 (51 in FIG. 1(b)).

The request types for the register 22 are different from read/write to the main memory 3 and I10 requests, and in this case, I10.
It is an indication of a request.

For example, the command information in the register 21 has the configuration shown in FIG.
The operation code section 60 contains operation codes for input/output commands such as Sl, and a subchannel address section 61.
The subchannel address used in the preprocessing described above is placed in , and other control information is placed in the control section 62 when necessary.

Note that the numbers at the bottom of the figure are bit position numbers for indicating an example of the structure of command information. In this example, command information is composed of 32 bits from bit positions 0 to 31.

In the system control device 4, the selection circuit 23 selects one of the simultaneously generated requests according to a predetermined priority order, receives the request information, and inputs the request information to the address pipeline 24.

The above-mentioned three types of command information are sequentially input to the address pipeline 24 along with the request type and the source CPU number, and these pieces of information are shifted through the registers that make up the so-called pipeline, and are input to each request type. used for control depending on the

In the case of an I10 request, the request type is detected and the command information and source CPU number are copied to the channel selection circuit 25 at an appropriate stage in the pipeline.

The channel selection circuit 25 determines CHF2 based on a part of the subchannel address part (61 in FIG. 3) of the command information, and sends the command information to the register 26 of the CHP2.
Transfer the CPU number to (52 in tbl in Figure 1).

Command information in the register 26 is stored in a buffer register 35-1 or 35-2 provided corresponding to each CPU.

When command information and the like are set in the buffer registers 26 and 27, the control unit 29 immediately sends the CPU number to the register 30 of the system control device 4 and a reception confirmation signal to the latch 31.

In the system control device 4, the selection circuit 32 selects the CPU number CP tJ set in the register 30, and
By sending the reception confirmation signal to the latch 33 for U, the reception confirmation signal is transferred to the CPU (see Fig. 1(b)
) of 53).

At the same time, the control section 29 of the CHF2 also sends the buffer full signal latch 34-1 or 34-2 of the system control device 4.

The buffer full signal latches 34-1 and 34-2 correspond to the buffer register 3 for each CPU, corresponding to each CHP.
5-1.35-2 is in use, and when the control unit 29 is notified by the processing unit 28 of the empty space of the pa-nofa register 35-1 or 35-2. , retained until reset.

The Buffer Full Signal Launch 34-1, 34-2 signal transfers the Buffer Full signal to each CPU by setting the latch 36 by ORing the signals for that CPU. Therefore, each CPUI has all C1 (buffer register 35-1 or 35 for own CPU'U in P2).
-2 are all empty, the off state of the buffer full signal is detected.

When the CPUI receives the reception confirmation signal transferred by the register 33, if the input/output instruction being executed is the above-mentioned asynchronous type, it immediately sets a CC with predetermined contents in a predetermined register and completes the execution of the instruction.

Therefore, in the execution of asynchronous input/output instructions,
Connection with the CPU (!:CHP) is required only during the period shown at 54 in b).

If the input/output instruction being executed is the synchronous type described above,
Furthermore, it waits for a response from CHP2.

When processing becomes possible, the processing unit 28 of the CHP 2 reads the command information from the buffer register 35-1 or 35-2 and performs input/output control processing according to the conventional method. However, in this case, since the CIV information has already been transferred to the I10 system area by the CPUI, the CHP2 does not read the CAM as in the conventional case.

In that case, the processing unit 28 first notifies the control unit 29 that the read buffer register 35-1 or 35-2 is empty, so the control unit 29 stores the corresponding buffer register.
Reset full signal latch 34-1 or 34-2.

If the operation determined by the operation code section (60 in Figure 3) of the command information is an asynchronous type, the command execution on the CPUI is completed as described above, and no further response to the command is issued from CH'P2. .

If the processing unit 28 determines that the operation is synchronous, it creates a CC indicating the result of the control when the control based on the command information (for example, peripheral device startup control in the case of an sro instruction) is completed. The data is then transferred to the register 37 of the system control device 4. At the same time, the source CPU number of the input/output command is stored in the register 30, and the processing end signal is stored in the latch 3.
8 (57 in Figure 1 (bl)).

The CC and processing end signal pass through the selection circuit 32 and are sent to the target CP.
It is set in register 39 and lunch 40 for U, and CP
It is transferred to the UI (55 in FIG. 1(b)).

The CPUI receives them and sets the CC in a predetermined register, thereby completing execution of the synchronous input/output instruction. Therefore, in the case of synchronous type input/output instructions,
), during the period indicated by 56, CPtJ and CI(P) are bonded.

In the above explanation, the buffer register 35-1 of each CHP is
．． 35-2 is provided for each CPU, but if two or more are provided for each CPU, or if multiple CPUs
A plurality of pools of buffer registers may be provided in common for all the buffer registers, and these can be easily configured as a modification of this embodiment.

〔Effect of the invention〕

As is clear from the above description, the present invention has a significant industrial effect of shortening the CPU hold time due to the execution of input/output instructions and improving the processing capacity of the computer system.

[Brief explanation of the drawing]

FIG. 1(a) is a block diagram of the configuration of one embodiment of the present invention.
(bl is a timing diagram of an embodiment of the present invention, FIG. 2 is a configuration diagram of a computer system, FIG. 3 is a configuration diagram of command information, and FIG. 4 is a conventional input/output command execution timing diagram. , 1 is a central processing unit (CPU), 2 is a channel control device (CHP), 3 is a main storage device, 4 is a system control device, 21.
22, 26, 27 are registers, 23 is a selection circuit, 24 is an address pipeline, 25 is a channel selection circuit, 28 is a processing section, 29 is a control section, 32 is a selection circuit, 34-1.34-2 is a buffer. Full signal launch, Japan
1 Figure (d> Figure 1 (1)) 22 Figure 13 Figure %4 Figure

Claims (1)

[Claims] In a computer system having a central processing unit and a channel control unit that operates by receiving command information based on input/output commands executed by the central processing unit, the channel control unit stores information stored in one or more buffers in the central processing unit. the central processing unit transfers predetermined command information based on the input/output command to the buffer, and execution of the specific input/output command is completed by execution of the transfer. An input/output command control method characterized by being configured to: