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JPS614234U - Electronic computer - Google Patents

Electronic computer

Info

Publication number
JPS614234U
JPS614234U JP8751384U JP8751384U JPS614234U JP S614234 U JPS614234 U JP S614234U JP 8751384 U JP8751384 U JP 8751384U JP 8751384 U JP8751384 U JP 8751384U JP S614234 U JPS614234 U JP S614234U
Authority
JP
Japan
Prior art keywords
storage device
range
data
electronic computer
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8751384U
Other languages
Japanese (ja)
Inventor
弘司 大野
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP8751384U priority Critical patent/JPS614234U/en
Publication of JPS614234U publication Critical patent/JPS614234U/en
Pending legal-status Critical Current

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  • Storage Device Security (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案による電子計算機の全体構成図、第2
図は中央処理装置の一部を具体的に示す図、第3図は記
憶保護装置を具体的に示す図である。 図中、1(7ま記憶装置、2は中央処理装置、3は記憶
保護装置、4はメモリーアドレスを表わすデータ、5は
命令内容を表わすデータ、6はエラー信号、7はプログ
ラムカウンタ、8は加竃器、9は命令レジスタ、10は
命令デコーダ、11は演算器、12はメ毛リーアドレス
、13はメモリーヂータ、14は範囲設定回路、15.
16はメモリー、17.18は比較回路、19は命令選
択回路、20は論理積素子、21は命令レジスタ変更回
路、22は停止命令を表わす内容である。 なお、図中、同一あるいは相当部分には同一符号を付し
て示してある。
Figure 1 is an overall configuration diagram of the electronic computer based on this invention, Figure 2
The figure specifically shows a part of the central processing unit, and FIG. 3 specifically shows the storage protection device. In the figure, 1 (7 is a storage device, 2 is a central processing unit, 3 is a memory protection device, 4 is data representing a memory address, 5 is data representing instruction content, 6 is an error signal, 7 is a program counter, and 8 is a 10 is an instruction decoder, 11 is an arithmetic unit, 12 is a memory address, 13 is a memory datater, 14 is a range setting circuit, 15.
16 is a memory, 17 and 18 are comparison circuits, 19 is an instruction selection circuit, 20 is an AND element, 21 is an instruction register change circuit, and 22 is a stop instruction. In the drawings, the same or corresponding parts are denoted by the same reference numerals.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 各種の演算を行なう演算部および命令やデータの流れを
制御する制御蔀から構成される中央処理装置と、命令及
びデータを格納する記憶装置と、上記記憶装置内の任意
の範囲を指定し、上記範囲内の記憶装置申の内容を変更
することを禁止する記憶保護装置とを有し、任意の指定
範囲の記憶保護が可能であることを特徴とする電子計算
機。
A central processing unit consisting of an arithmetic unit that performs various operations and a control gate that controls the flow of instructions and data, a storage device that stores instructions and data, and an arbitrary range within the storage device, and What is claimed is: 1. A computer comprising: a memory protection device that prohibits changes to the contents of a storage device within the range; and capable of protecting memory of any specified range.
JP8751384U 1984-06-13 1984-06-13 Electronic computer Pending JPS614234U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8751384U JPS614234U (en) 1984-06-13 1984-06-13 Electronic computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8751384U JPS614234U (en) 1984-06-13 1984-06-13 Electronic computer

Publications (1)

Publication Number Publication Date
JPS614234U true JPS614234U (en) 1986-01-11

Family

ID=30639800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8751384U Pending JPS614234U (en) 1984-06-13 1984-06-13 Electronic computer

Country Status (1)

Country Link
JP (1) JPS614234U (en)

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