JPS6087050U - data transfer control device - Google Patents
data transfer control deviceInfo
- Publication number
- JPS6087050U JPS6087050U JP17694383U JP17694383U JPS6087050U JP S6087050 U JPS6087050 U JP S6087050U JP 17694383 U JP17694383 U JP 17694383U JP 17694383 U JP17694383 U JP 17694383U JP S6087050 U JPS6087050 U JP S6087050U
- Authority
- JP
- Japan
- Prior art keywords
- data transfer
- transfer control
- control device
- main storage
- storage device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bus Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のデータ転送制御装置の構成を示した図、
第２図はこの考案の一実施例の構成を示した図である。
図において、１は中央処理装置、２はメモリバス、３は
主記憶装置、４は外部機器、５はデータレジスタ、６は
制御部、７は転送要求信号、８は転送要求信号、９は転
送指示信号、１０はアドレスレジスタ、１１はメモリで
ある。なお、図中同一符号は同一または相当部分を示す
。FIG. 1 is a diagram showing the configuration of a conventional data transfer control device.
FIG. 2 is a diagram showing the configuration of an embodiment of this invention. In the figure, 1 is a central processing unit, 2 is a memory bus, 3 is a main storage device, 4 is an external device, 5 is a data register, 6 is a control unit, 7 is a transfer request signal, 8 is a transfer request signal, and 9 is transfer An instruction signal, 10 an address register, and 11 a memory. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
行するプログラムによらないでデータ転送を行うのを制
御するデータ転送制御装置において、データ転送の対象
となる主記憶装置のアドレスを複数記憶可能なメモリを
設け、そのメモリを、データ転送要求した外部機構番号
により、転送開始時に索引することにより、データ転送
する主記憶装置のアドレスを設定するようにしたことを
特徴とするデータ転送制御装置。In a data transfer control device that controls data transfer between multiple external devices and a main storage device without depending on a program executed by a central processing unit, multiple addresses of the main storage device that are the targets of data transfer are specified. A data transfer control characterized in that a memory capable of storing data is provided, and the address of the main storage device to which the data is transferred is set by indexing the memory according to the external mechanism number that requested the data transfer at the time of starting the transfer. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17694383U JPS6087050U (en) | 1983-11-16 | 1983-11-16 | data transfer control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17694383U JPS6087050U (en) | 1983-11-16 | 1983-11-16 | data transfer control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6087050U true JPS6087050U (en) | 1985-06-15 |
Family
ID=30384548
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17694383U Pending JPS6087050U (en) | 1983-11-16 | 1983-11-16 | data transfer control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6087050U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63266568A (en) * | 1987-04-24 | 1988-11-02 | Hitachi Ltd | Data transfer controller |
-
1983
- 1983-11-16 JP JP17694383U patent/JPS6087050U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63266568A (en) * | 1987-04-24 | 1988-11-02 | Hitachi Ltd | Data transfer controller |
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