JPS61251319A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a steep inverting characteristic by adopting a depletion MOSFET for a MOSFET to which an input voltage is applied to apply voltage comparison near a power supply voltage with high sensitivity. CONSTITUTION:Depletion MOSFETs are employed for a PMOSFET 1 and NMOSFET 2 connected respectively to input terminals 6, 5. When a reference voltage inputted to the terminal 6 is set near a power voltage VDD, a gate-source voltage of the FET 1 inputting the said voltage gets smaller, and since the FET 1 is of depletion type, a sufficient current flows and the FET 1 is operated at the saturated state. Since the FET 3 is connected to be operated with saturation, a bias voltage decided by the FETs 1, 3 fed to a gate of a MOSFET 4. When the comparison voltage inputted to the gate of the FET 2 approaches the reference voltage, the FET 4 is operated in saturated state and the FET 2 is operated also in the saturated state. When the input voltage to the FET 2 exceeds a reference voltage, the output is inverted immediately.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit that compares two input voltage values and changes the output depending on the magnitude relationship.

[Summary of the invention]

The present invention is a semiconductor integrated circuit that compares two input voltage values and changes the output depending on the magnitude relationship between them, and has a gate connected to one input terminal, nine sources connected to 10,000 power supply terminals, and reverse conduction. 3rd MO8F of the mold]! ! a first MO of a first conductivity type, the drain of which is connected to the drain of T;
8FI [IT and the gate to which the other input terminal is connected,
Source with 10,000 power supply terminals connected, fourth MO87F of reverse conductivity type! T drain, genit and third MOSF
A second MO8FEIT of the first conductivity type consisting of a drain connected to the gate of the ET;
The source of OEIFFT is connected to the other power supply terminal, and the first
By making the second MO8FKT a depression type, the voltage value near the power supply voltage is compared to the sensitive layer, and the output is sharply inverted.

[Conventional technology]

Conventionally, as shown in Fig. 2, the drain and gate of PMO8PIT8, the gate of PM08F]1CT9 and NMO
8FIT 12 drains are connected.

The drain of PMO8FIT9 and the drain of NMO8FmT15 are connected and % PMO day T++1! XT8 and 9
The source is one power terminal, terminal 31 (hereinafter referred to as VDD)
NMO87! ! ! TIO and 11 are connected to the other power supply terminal 30 (hereinafter referred to as 711g+), one input terminal 12 is connected to the gate of NMOFFET10 (C1), and the other input terminal is connected to the gate of NMOSFET11, and each input terminal 12 is connected to the gate of NMOSFET11. A semiconductor integrated circuit is known that compares the voltages applied to the terminals 1 and 13 and changes the output depending on the magnitude relationship.

This circuit connects PMO81FIT8 and NMOslP?, which are connected to saturation by applying a reference voltage to be compared to the input terminal 12, for example. ! ! A bias potential determined by T10o voltage-current characteristics is applied to the gate of PMOEIFET9. When the voltage to be compared is applied to the input terminal 13 and gradually changed.

PMO8F'1ltT9 and NM near the reference voltage
If the O8F'KT 11 is operating in the saturation region, when the voltage at the input terminal 13 exceeds the reference voltage input to the input terminal 12, the level of the output 14 will be rapidly reversed.

[Problem that the invention seeks to solve]

However, the conventional circuit has a drawback that when the reference voltage becomes close to the power supply voltage, the inversion characteristic of the output 14 deteriorates and the offset voltage increases. This state will be explained in more detail with reference to FIG. 3, which shows a conventional example. When the input 12 becomes high, NMOEIFKTlo has a current-voltage characteristic as shown in the curve 18, and when the bias voltage V is determined by the current-voltage characteristic curve 15 of the PMO8711iτ8, the NMOEIFKTlo
81F]]'l'IO will operate in the non-saturation region.

PM08FIC with bias voltage V, applied to the gate
'l' 9 has a current-voltage characteristic shown in curve 16 when bias voltage 'VOO' is applied. When the voltage to be compared is applied to input 13, 8M08? The current-voltage characteristics of KT 11 are shown by curve 17 when the voltage at input 13 is lower than the voltage at input 12, by curve 18 when they match, and by curve 19 when they are higher. Therefore PM08F'll
! Current-voltage characteristic curve 16 and curve 17, 18.19 of T9
The output voltage of output 14 is determined at the intersection of 1M08
7mT11 operates in the non-saturation region, so the output 1
4 voltage change is curve 17 and song I! Only the voltage V obtained at the intersection of curves 19 and 16 can be obtained up to the voltage v1 obtained at the intersection of curves 19 and 16. Therefore, the reversal characteristic of the output 14 becomes dull as shown by curve 27 in FIG. If the voltage at the input 13 is further increased, the output at the output 14 will change significantly, but this will result in a large difference from the voltage applied to the input 2, and the pinch offset voltage will increase.

Therefore, in order to solve these conventional drawbacks, the present invention aims to obtain a semiconductor integrated circuit with a steep output 140 reversal characteristic and a small offset voltage even when the reference voltage to be compared is near the power supply voltage. There is.

[Means for solving problems]

In order to solve the above problems, the present invention provides a fifth MO87m! having a gate connected to one input terminal, a source connected to one power supply terminal, and a fifth MO87m! of opposite conductivity type. A first conductive i-type MOB F whose drain is connected to the drain of iT.
]! ! T, gate % to which the other input terminal is connected
4th MO87I with 10,000 power supply terminals connected, 9 sources, and reverse conductivity type! ! T drain, gate, and fifth MO
EIIPII! M'0I3FE of the first conductive lic type consisting of the drain connected to the gate of T! ? , third and fourth
The source of the MO81PIliT is the bottom of the tank connected to the other power supply terminal, and the first and second MOEIFl[tT are depletion type, so that the output has a steep inversion characteristic with respect to the reference voltage near the power supply voltage. I made it last.

[Effect]

In the above-described semiconductor integrated circuit, when the reference voltage is set near the power supply voltage, the first MO8FInTO gate-source voltage that receives this voltage as input becomes small, but this MO8Fm! ! Since T is a depletion type, a sufficient current can flow therethrough and it can be operated in a saturated state.

Since the third MO8FICT is also connected in saturation.

sgl and a bias voltage determined by the fifth MO8FIT is applied to the gate of the fourth MO8′FKT;
When the voltage to be compared that is input to the gate of the second MOSFET approaches the reference voltage.

4th MO8FI! ! T does not operate in a saturated state, and the second MO8FIIIT also operates in a saturated state because the gate-y-sum pressure becomes small. Therefore, when the voltage input to the gate of the second MOSFET exceeds the reference voltage applied to the gate of the first MO8F11tT, the output does not immediately invert, and a sharp inversion characteristic can be obtained. be.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, the input terminal 6f of the gate of the depression type PMO8FKT1 is connected to VDD31 and the reference voltage is set to 71)D.

PMOEIPKT 10 source connects to ynn31,
Connect the drain to the drain and gate of NMO87mT3 and N
MO8Fm! Connect to the gate of 1T4. A depression type PMO87m with the input terminal 5 of the voltage to be compared connected to the gate! ! The source of T2 is connected to VD131, and the drain is connected to the drain of NMO81FIIiT4, serving as an output terminal.

NMO87FfT! and 40 are connected to yas30. (In this case, ysg50 is set to the ground potential.) The gate-source voltage of PM08F]nT6 is O
NMOE1?1!, which exhibits the voltage-current characteristics shown by curve 22 in FIG. 5 because it is a depression type. IT
Since PMO8FE! has the current-voltage characteristics shown in curve 20 because it is connected in saturation (the drain and gate are connected), PMO8FE!
A bias voltage V is set so that the current values flowing through T1 and NMO8FIItTl match. This bias voltage V,
is the gate voltage of NMO8FmT4, so NMO8
The current-voltage characteristic of P]lCτ4 is shown by a curve 24. When the output cuff is near the bias voltage V, NMO8Fm! iT
4 means that it is operating in a saturated state. Now, depression type PMO8IPI! ! As the input 5 applied to the gate of T2 is changed, when the voltage of ynn51 is slightly lower, this PMO8Fm! ! T2 is also a drain.
Since the gate-to-source voltage is sufficiently lower than the source-to-source voltage, it operates in the saturation region and has the current-voltage characteristics shown by curve 21. Therefore, the voltage of the output 17 is the voltage vl, which is the intersection of the curves 24 and 21.7 When the human power 5 matches the voltage of the input 4, the current-voltage characteristic of PM08Fmτ2 becomes as shown in the curve 22, and becomes slightly higher. I'M
The voltage between the gate and source of O81PIIIT2 becomes negative, but since it is a depression type, sufficient current can flow, resulting in the characteristics shown in curve 23 - At this time, the voltage at which the current values of curve 24 and curve 23 match becomes the voltage vl.

As the voltage at the input 5 passes around the reference voltage ynn510, the output cuff sharply changes from the voltage V to the voltage Vl.

That is, it is possible to have a steep output reversal characteristic as shown by curve 25 in FIG.

FIG. 4 shows another embodiment of the present invention, in which a constant current source 8
It is designed to be driven by In this case each MO
Since the gate-source voltage of the 8FET is lower, the voltage range in which it operates in the saturation region is wider (as shown in curve 26 in Figure 6), and it is possible to obtain a steep inversion characteristic. Therefore, the operating current can be kept constant and the power supply can be stabilized.It should be noted that the output voltage of curve 26 is 7
What is decreasing on the DD side is the PM caused by the constant current circuit 8.
o 8 FIIXT 1 and 2 source 32 is VDD5
1] is also lower.

In the embodiment, input 6 of PMO8F'llXT1 was used as the reference voltage, but PM08FI! Using input 5 of fT2 as the reference voltage, FMOEIFE! Even if the thermal power 6 of T1 is changed, the polarity of the reversal characteristic of the output cuff will be reversed.Also, although 7rrD51 was set as the reference voltage, if the voltage value allows the depression M0 and F1nT to operate in the saturation region. There are no particular problems. Furthermore, the constant current circuit 8'
Although it is provided on the VDD side, it goes without saying that the same effect can be obtained even if it is provided on the yss side.

Moreover, when comparing voltage values near ygs+, MO8FBiT1 constitutes the circuit shown in FIG.

2.5,4. MOSFE of opposite conductivity type
If the polarity of the power source 7ss30 and VDD31 is reversed, exactly the same effect can be obtained.

〔Effect of the invention〕

As explained above, the present invention provides M
By using the OSFET as a depression disk, voltage comparison near the source voltage can be performed as a sensitive layer, and there is an effect that a steep reversal characteristic can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a voltage comparison circuit according to the present invention. FIG. 2 is a circuit diagram of a conventional voltage comparison circuit, FIG. 3 is a voltage-current characteristic diagram showing the operation of the conventional voltage comparison circuit, and FIG. 4 is a circuit diagram of another voltage comparison circuit according to the present invention. Figure 5 is a current-voltage characteristic diagram showing the operation of the voltage comparison circuit according to the present invention;
FIG. 6 is an output inversion characteristic diagram of the present invention and a conventional circuit. 1... 1st conductive shop MO8711! T 2・-1st conductivity type M087EltT 5 ... 2nd conductivity m M OEI F K T4・
...Second conductive ff1M011117IIIT5...Input terminal 6...Input terminal 8...Current source 30...Power supply terminal 51...Power supply terminal and above Applicant: Seiko Electronics Co., Ltd. SS Japanese wire according to the present invention 1i ratio comparison route rjj route diagram Figure 4 Figure 5

Claims (1)

[Claims] A first conductivity type MOSFET consisting of a gate connected to four input terminals, a source connected to one power supply terminal, and a drain connected to the drain of a third MOSFET of opposite conductivity type. 1st
MOSFET, a gate connected to the other input terminal, a source connected to one power supply terminal, and a fourth MOSFET of opposite conductivity type.
The drain and gate of the MOSFET and the third MOSFET
a second MOSFET of the first conductivity type, the drain of which is connected to the gate of the SFET; the sources of the third and fourth MOSFETs are connected to the other power supply terminal; is a semiconductor integrated circuit characterized by being a depression type. (2) The semiconductor integrated circuit according to claim 1, wherein the one power supply terminal or the other power supply terminal is driven by a constant current source.