JPH0521446B2 - - Google Patents
Info
- Publication number
- JPH0521446B2 JPH0521446B2 JP62284919A JP28491987A JPH0521446B2 JP H0521446 B2 JPH0521446 B2 JP H0521446B2 JP 62284919 A JP62284919 A JP 62284919A JP 28491987 A JP28491987 A JP 28491987A JP H0521446 B2 JPH0521446 B2 JP H0521446B2
- Authority
- JP
- Japan
- Prior art keywords
- fet
- field effect
- effect transistor
- drain
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 claims description 19
- 238000010586 diagram Methods 0.000 description 6
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
Landscapes
- Amplifiers (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電界効果トランジスタ（以下FETと
いう）負荷増幅回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor (hereinafter referred to as FET) load amplification circuit.
従来、この種の増幅回路は、第４図に示す如
く、ソース接地で用いるFET１１と、ゲートと
ソースを共通電位にした負荷FET４１とを接続
し、負荷FET４１のドレイン端から直流電源電
圧VDDを供給し、入力端子４２から信号を入力し
端子１２から出力を取り出していた。
Conventionally, as shown in FIG. 4, this type of amplifier circuit connects a FET 11 used with a common source to a load FET 41 whose gate and source are at a common potential, and receives a DC power supply voltage V DD from the drain end of the load FET 41. A signal was input from the input terminal 42 and an output was taken from the terminal 12.
〔発明が解決しようとする問題点〕
上述した従来のFET増幅回路は、FET４１の
ドレイン・ソース間抵抗を負荷として用いるた
め、容易に高抵抗が得られ、同時に高い電圧利得
が得られている。しかし、出力端子１２のDC電
圧、即ちソース接地FET１１の動作電圧が、素
子のバラツキに非常に敏感であり、安定な動作電
圧が得られなかつた。従つて、FET１１とFET
４１が少しでも異なる特性を持つた場合は、設計
値から大きくずれた動作状態となり所定の電圧利
得が得られないという欠点を持つていた。[Problems to be Solved by the Invention] The conventional FET amplifier circuit described above uses the drain-source resistance of the FET 41 as a load, and therefore can easily obtain a high resistance and at the same time obtain a high voltage gain. However, the DC voltage at the output terminal 12, ie, the operating voltage of the common source FET 11, is extremely sensitive to variations in the elements, and a stable operating voltage cannot be obtained. Therefore, FET11 and FET
If 41 has even a slightly different characteristic, the operating state will deviate greatly from the designed value, resulting in a disadvantage that a predetermined voltage gain cannot be obtained.
本発明は、従来の増幅回路に対し、FETを負
荷とし高い電圧利得を得ると同時に、負荷FET
のゲート供給電圧を別回路から導入することによ
り安定な動作状態が得られるという相違点を持つ
ている。 The present invention uses a FET as a load to obtain a high voltage gain, and at the same time, compared to a conventional amplifier circuit, the load FET is
The difference is that a stable operating state can be obtained by introducing the gate supply voltage from a separate circuit.
本発明のFET負荷増幅回路は、電源の一端に
接続されたソースを有しゲートを信号の入力端子
としドレインを信号の出力端子とする第１の電界
効果トランジスタと、電源の他端に接続されたド
レインと前記第１の電界効果トランジスタのドレ
インに接続されたソースとを有する第２の電界効
果トランジスタと、電源の一端に電圧降下発生装
置を通して接続されたソースを有する第３の電界
効果トランジスタと、電源の他端に接続されたド
レインと前記第３の電界効果トランジスタのドレ
インに接続されたソースとを有する第４の電界効
果トランジスタとを備え、前記第１および第３の
電界効果トランジスタのゲートを抵抗を通して接
続して構成される。
The FET load amplification circuit of the present invention includes a first field effect transistor having a source connected to one end of a power supply, a gate serving as a signal input terminal, and a drain serving as a signal output terminal; a second field effect transistor having a drain connected to the drain of the first field effect transistor and a source connected to the drain of the first field effect transistor; and a third field effect transistor having a source connected to one end of the power supply through a voltage drop generator. , a fourth field effect transistor having a drain connected to the other end of the power supply and a source connected to the drain of the third field effect transistor, the gates of the first and third field effect transistors connected through a resistor.
次に、本発明について図面を用いて説明する。 Next, the present invention will be explained using the drawings.
まず、第１図を見るに、ソース接地のFET１
１のドレイン端子に負荷のFET１３のソース端
子を接続し、負荷となるFET１３のドレイン端
子に直流電源電圧VDDを供給する。一方、負荷の
FET１３のゲート端子１４の電圧を、ゲートと
ソースが抵抗１５を介して接続された電流源の
FET１６と、この電流源のFET１６のソースに
接続されたFET１７と、このFET１７のソース
に接続された抵抗１８とから成るバイアス回路に
より、抵抗１９を介して設定される。 First, looking at Figure 1, FET 1 with a common source
The source terminal of the load FET 13 is connected to the drain terminal of the load FET 13, and the DC power supply voltage V DD is supplied to the drain terminal of the load FET 13. On the other hand, the load
The voltage at the gate terminal 14 of the FET 13 is controlled by a current source whose gate and source are connected via a resistor 15.
It is set via a resistor 19 by a bias circuit consisting of an FET 16, a FET 17 connected to the source of the FET 16 of this current source, and a resistor 18 connected to the source of this FET 17.
このバイアス回路でFET１３のゲート端子１
４の電圧が設定されることによりFET１１のド
レイン端子１２すなわち出力端子１２の電圧が決
定され安定な動作が得られる。しかし、端子１４
に接続されるバイアス回路のインピーダンスが十
分に高く設定されない場合は、FET１３のゲー
ト・ソース間容量CGSを介して端子１２の高周波
電圧も決定されるため高周波利得を低下させるこ
とになる。これを防ぐため、本実施例のバイアス
回路は、端子１４から見たインピーダンスを高く
する設計がされている。 With this bias circuit, gate terminal 1 of FET13
By setting the voltage No. 4, the voltage at the drain terminal 12, that is, the output terminal 12 of the FET 11 is determined, and stable operation can be obtained. However, terminal 14
If the impedance of the bias circuit connected to the FET 13 is not set high enough, the high frequency voltage at the terminal 12 will also be determined via the gate-source capacitance CGS of the FET 13, reducing the high frequency gain. To prevent this, the bias circuit of this embodiment is designed to increase the impedance seen from the terminal 14.
まず、本バイアス回路の直流電圧は次の様に設
定される。電流源FET１６により、抵抗１８を
流れる電流IBが設定される。従つて、端子２０の
直流電位は、抵抗１８の抵抗値をＲとするとＲ・
IBとなる。この時、FET１７にも同じ電流IBが流
れており、このFET１７のゲート電位はこの電
流を流すために必要なゲート・ソース間電圧VGS
を保つ必要があるため、Ｒ・IB＋VGSの電位にな
る。FET１７とFET１３のゲート端子間を結ぶ
抵抗１９にはほとんど直流電流は流れない（通常
1μA以下）ため、端子１４のDC電位はFET１７
のゲート電位Ｒ・IB＋VGSに設定される。 First, the DC voltage of this bias circuit is set as follows. A current I B flowing through the resistor 18 is set by the current source FET 16 . Therefore, if the resistance value of the resistor 18 is R, the DC potential of the terminal 20 is R.
It becomes I B. At this time, the same current I B is flowing through FET 17, and the gate potential of this FET 17 is the gate-source voltage V GS required for this current to flow.
Since it is necessary to maintain the voltage, the potential becomes R・I B +V GS . Almost no direct current flows through the resistor 19 connecting the gate terminals of FET17 and FET13 (normally
1μA or less), so the DC potential of terminal 14 is
The gate potential R・I B +V GS is set.
また、端子１４から見たバイアス回路は、ソー
スホロアー回路と等価になつているため、高周波
インピーダンスも高くなり、抵抗１９の抵抗値を
RG，FET１７のゲート容量をCGS、トランスコン
ダクタンスをgnとすると、このバイアス回路の
インピーダンスはおおむねRG＋［（１＋gnRS）／
（jωCGS）］となる。FET１３のゲート容量CGSは
十分小さくすることが可能なため、このインピー
ダンスを高くすることは容易である。 In addition, since the bias circuit viewed from the terminal 14 is equivalent to a source follower circuit, the high frequency impedance is also high, and the resistance value of the resistor 19 is
R G , the gate capacitance of FET 17 is C GS , and the transconductance is g n , the impedance of this bias circuit is approximately R G + [(1+g n R S )/
(jωC GS )]. Since the gate capacitance C GS of the FET 13 can be made sufficiently small, it is easy to increase this impedance.
従つて、このバイアス回路により、FET１１
のドレイン直流電圧を安定に設定できると同時
に、高周波利得を劣化させない増幅器が得られ
る。 Therefore, with this bias circuit, FET11
An amplifier can be obtained in which the drain DC voltage of the amplifier can be set stably and at the same time the high frequency gain does not deteriorate.
次に、本発明の第２の実施例について説明す
る。 Next, a second embodiment of the present invention will be described.
第２図は、本発明の第２の実施例の構成を示
し、第１の実施例の抵抗１８をダイオード２１で
置き換えた構成のバイアス回路を用いた増幅器で
ある。電流源FET１６により定電流IBがダイオー
ドに流れ、ダイオードの順方向電圧VFにより端
子２０の直流電位は３×VFに設定される。ダイ
オードの順方向電圧VFは電流IBの変化に対しても
安定なため、端子２０の電位は容易に安定に設定
でき、第１の実施例と同様に、端子１２の電位を
安定させた増幅器を構成することができる。この
実施例のバイアス回路のインピーダンスは多少低
下するが、FET１７のゲート容量CGSのインピー
ダンス以下に低下することは無いため、RF利得
に大きな影響を与えるまでには低下しない。 FIG. 2 shows the configuration of a second embodiment of the present invention, which is an amplifier using a bias circuit in which the resistor 18 of the first embodiment is replaced with a diode 21. A constant current I B flows through the diode by the current source FET 16, and the DC potential of the terminal 20 is set to 3×V F by the forward voltage V F of the diode. Since the forward voltage V F of the diode is stable even with changes in the current I B , the potential of the terminal 20 can be easily set to be stable, and the potential of the terminal 12 can be stabilized as in the first embodiment. An amplifier can be configured. Although the impedance of the bias circuit in this embodiment decreases to some extent, it does not decrease to below the impedance of the gate capacitance CGS of the FET 17, so it does not decrease to the extent that it significantly affects the RF gain.
次に、本発明の第３の実施例について説明す
る。 Next, a third embodiment of the present invention will be described.
第３図は、本発明の第３の実施例の構成を示す
回路図で、第２の実施例と同じバイアス回路を用
いた差動型の増幅回路である。このバイアス回路
のダイオード２１を抵抗１８と組合せて使うこと
も可能である。従つてFET４２Ａ，４２Ｂのゲ
ートが入力端子となり、FET４２Ａ，４２Ｂの
ドレインが出力端子１２Ａ，１２Ｂとなり、負荷
用のFET１３Ａ，１３Ｂのゲートはそれぞれ抵
抗１９Ａ，１９Ｂを介してバイアス回路のFET
１７のゲートに接続されている。また、FET１
１Ａ，１１Ｂのソースの端子４２Ａ，４２Ｂは低
電流回路を形成するFET３１の通し、直流電流
電圧VDDと反対符号の直流電源電圧VSSに接続さ
れている。 FIG. 3 is a circuit diagram showing the configuration of a third embodiment of the present invention, which is a differential amplifier circuit using the same bias circuit as the second embodiment. It is also possible to use the diode 21 of this bias circuit in combination with the resistor 18. Therefore, the gates of FETs 42A and 42B become input terminals, the drains of FETs 42A and 42B become output terminals 12A and 12B, and the gates of load FETs 13A and 13B are connected to the bias circuit FETs via resistors 19A and 19B, respectively.
It is connected to 17 gates. Also, FET1
The source terminals 42A and 42B of 1A and 11B are connected to a DC power supply voltage V SS having the opposite sign to the DC current voltage V DD through a FET 31 forming a low current circuit.
以上説明したように本発明は、定電流源FET
と抵抗あるいはダイオードによりDC電圧を決定
し、これらの間に接続されるFETのゲート電位
を増幅器の負荷となるFETのゲート電位として
与えることにより、増幅用のFETの直流ドレイ
ン電圧を安定に設定すると共に、FET負荷の持
つ高い電圧利得を同時に得られるという効果があ
る。
As explained above, the present invention is a constant current source FET.
By determining the DC voltage using a resistor or diode, and applying the gate potential of the FET connected between these as the gate potential of the FET that serves as the load of the amplifier, the DC drain voltage of the amplification FET can be set stably. At the same time, the high voltage gain of the FET load can be obtained at the same time.
第１図は本発明の第１の実施例の構成を示す回
路図、第２図は本発明の第２の実施例の構成を示
す回路図、第３図は本発明の第３の実施例の構成
を示す回路図、第４図は従来の技術によるFET
負荷増幅回路の一例を示す回路図。
１１，１３，１５，１７……電界効果トランジ
スタ（FET）。
FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the invention, FIG. 2 is a circuit diagram showing the configuration of a second embodiment of the invention, and FIG. 3 is a circuit diagram of a third embodiment of the invention. A circuit diagram showing the configuration of , Figure 4 is an FET using conventional technology.
FIG. 2 is a circuit diagram showing an example of a load amplification circuit. 11, 13, 15, 17...field effect transistor (FET).
Claims (1)
を信号の入力端子としドレインを信号の出力端子
とする第１の電界効果トランジスタと、電源の他
端に接続されたドレインと前記第１の電界効果ト
ランジスタのドレインに接続されたソースとを有
する第２の電界効果トランジスタと、電源の一端
に電圧降下発生装置を通して接続されたソースを
有する第３の電界効果トランジスタと、電源の他
端に接続されたドレインと前記第３の電界効果ト
ランジスタのドレインに接続されたソースとを有
する第４の電界効果トランジスタとを備え、前記
第１および第３の電界効果トランジスタのゲート
を抵抗を通して接続したことを特徴とするFET
負荷増幅回路。1 A first field effect transistor having a source connected to one end of a power supply, a gate serving as a signal input terminal, and a drain serving as a signal output terminal; a drain connected to the other end of the power supply; and the first field effect transistor having a source connected to one end of the power supply. a second field effect transistor having a source connected to the drain of the effect transistor; a third field effect transistor having a source connected through a voltage drop generator to one end of the power supply; and a third field effect transistor having a source connected to the other end of the power supply. and a fourth field effect transistor having a drain connected to the third field effect transistor, and a source connected to the drain of the third field effect transistor, and the gates of the first and third field effect transistors are connected through a resistor. FET
Load amplifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62284919A JPH01125108A (en) | 1987-11-10 | 1987-11-10 | Fet load amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62284919A JPH01125108A (en) | 1987-11-10 | 1987-11-10 | Fet load amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01125108A JPH01125108A (en) | 1989-05-17 |
| JPH0521446B2 true JPH0521446B2 (en) | 1993-03-24 |
Family
ID=17684757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62284919A Granted JPH01125108A (en) | 1987-11-10 | 1987-11-10 | Fet load amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01125108A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0621346A (en) * | 1992-05-05 | 1994-01-28 | Xerox Corp | Integrated linear high-voltage device |
| FR2816133B1 (en) * | 2000-10-31 | 2003-04-04 | St Microelectronics Sa | ASSISTANCE CIRCUIT FOR SWITCHING A LOGIC CIRCUIT |
| JP4950568B2 (en) * | 2006-06-19 | 2012-06-13 | 旭サナック株式会社 | Mixing paint supply device |
| JPWO2009096192A1 (en) * | 2008-01-31 | 2011-05-26 | パナソニック株式会社 | Buffer circuit, image sensor chip including the same, and imaging device |
-
1987
- 1987-11-10 JP JP62284919A patent/JPH01125108A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01125108A (en) | 1989-05-17 |
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