JPS60236188A - Multi-port register cell - Google Patents

Abstract

PURPOSE:To enable register cells to execute the simultaneous reading and writing by inputting complementary signals to a pair of write lines so as to execute writing to a register cell and reading out the complementary signals on plural pairs of read lines different from the write lines. CONSTITUTION:Prior to reading, voltage of pairs of read lines B11-14 are precharged at high levels. At the time of reading, one or both if pairs of read word lines W11-14 are rised to high levels, and read n-MOSFET is conducted. Then voltages of the selected pairs of read lines B11-14 are changed complementarily in correspondence to voltages of respective terminals N1 and N2, and reading actions are executed. At the time of writing, voltages of a pair of write word lines W21-22 are rised to high levels, and write n-MOSFETQs 21- 22 are conducted, whereby complementary signals on a pair of write lines B21- 22 are written in the terminals N1 and N2.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to register cells used in semiconductor integrated circuits, and particularly to multi-register registers used in microprocessors and integrated memories.

(Prior art and its problems) In general, in order to perform logic operations in a microprocessor, two O(lands) stored in separate register cells are read out, they are input to a logic operation unit, After performing the addition #2, a method is used in which data is written to the register cell again.The register cell used for these purposes has at least two output terminals and one input terminal.These registers Conventional examples of cells are described in the commentary published by Tomizawa, Tokuda, and Enomoto in the September 1988 issue of the Information Processing Society of Japan, pages 1070 to 1078, entitled ``A new method for vLSI design.'' 1st
A 22-tresistor cell as shown is shown. In the figure, II II! is the inverter, N, and the inverter 9-11.
The output terminal of , Nt is the input terminal of Inver II, Qtt is
, Q+* is the read transistor of the register cell, Q
tt +Qtt is a write transistor, B, ,B,
is a read/write line, W, , W, , is a read word line of the register cell, W2 l+W22 is a write word line, Qs+rj is a refresh transistor,
RI indicates refresh clock lines, respectively. The operation of this register cell is as follows. When reading a register cell, one of the read word lines W and 1° Wl (more than one is possible) is selected, and the read transistor coupled to that word line is made conductive.
The information stored in the terminal Nl is read out to the read/write line corresponding to the selected read word line. When writing information to a register cell, the write word line is selected, one of the write transistors Q*t+Qtt is made conductive, and information is written from the read/write line to the terminal N2. During this write, the refresh clock line R1 is held at a level that makes the refresh transistor Qs+ non-conductive, and the refresh clock line R1 is held at a level that makes the refresh transistor Qs+ non-conductive. The voltage passes through all the two stages of inverters I, , I and is stored at the terminal Nl. However, in such register cells, because the read line and the write line are commonly used, reading and writing from the register must be performed at different times, which is a major barrier to speeding up logical operations. I was strong. As shown in Figure 2, when a large number of logical operations are pipelined into three processes: register reading, logical operation, and register writing, each logical operation is performed within the width of one time period. processing, enabling high-speed calculations. But for this,
It is necessary to have a configuration in which separate register cells can be read and written at the time of D1, and it is necessary to separate the read line and the write line.

OBJECTS OF THE INVENTION An object of the present invention is to provide a multi-port register cell that eliminates these conventional drawbacks and allows register cells to read and write simultaneously.

(Structure of the Invention) The present invention provides a flip-flop consisting of first and second inverters that mutually couple the output terminal of one inverter to the input terminal of the other inverter, and a pair of input/output terminals of a nuclear flip-flop. A pair of 41 write transistors respectively couple a pair of complementary write lines, a pair of input/output terminals of the flip-flop and a plurality of pairs of phase i1
This is a multi-port register cell characterized in that it is constituted by a plurality of pairs of read transistors each coupled to a 1+ +n't extension line.

(Principle and operation of the present invention) According to the present invention, writing to a register cell is performed by inputting complementary signals to a pair of blue write lines, while reading from a register cell is performed using a pair of blue write lines that are different from the write lines. By reading complementary signals to multiple pairs of read lines, register cells can read and write simultaneously.

(Example) Examples of the present invention will be explained below with reference to the drawings.

FIG. 3 is a circuit diagram showing a typical embodiment of the present invention.

In the figure, 11+11 are the first and second inverters constituting a flip-flop, N1 is the]E logic user output terminal of FRI, GFRO, DE, Nt is the negative-ready input/output terminal of FRI, ZFLODE, and Qr 1+Qt *( 5) and Qra, Qr4rJ: a pair of transistors for reading the register cell, Qz+, Q22 are a pair of transistors for writing, B1+ +R12 and f3ts l B10 are two pairs of complementary read lines, 82118211 are a pair of complementary write lines, W+1・"12 and N13 and N14 are the read word line pair of the register cell, W2t r Wt t
Each Fi write word line pair is shown. The broken line shown in the figure means that even if the number of read transistor pairs and read line pairs is further increased by IW, the number of transistor pairs and read line pairs will similarly increase.

In the embodiment, when reading a register cell, read word line pairs Wl, , W, and W, 3°N14 .
. . . (multiple pairs are possible) is selected, and the read transistor pair coupled to the word line pair is made conductive, and the stored information at terminals N and Nt is transferred to the selected read word line pair. The signals are read out as complementary signals to the corresponding readout line pair. Here, positive logic information is at terminal Nl,
For example, if ``1'' information is stored, terminal N
Since the negative logic information ``0'' is stored in t, the readout line (6) B11 (or 81!) has Ichikazu Rieuse ``1'', and the 1st resistance line B11 (or B ) has negative argument 11j information°′(
)” are read simultaneously in pairs 111-1.
Ru. In the J4A board that writes information to the register cells, write word line pairs W, , W, , iA bus, and write transistor pair Qt + r Q are made conductive and the write line pair is B! 1. Bl! Complementary signals are inserted into terminals N, , Nt from . As mentioned above, in order to store 1 [logic information in terminal N1 and negative logic information in terminal N2,
Positive logic information must be input to the write line Bll, and negative logic information must be input to R22.

The register cell of the present invention performs writing to and reading from the cell using complementary signals.

In order for this register cell to perform the conventional 4111 operation, an inverter 1111. and transistor Q++ +Q+a.

Qss 1Q141...+Qt+ 1022's current drive capability is determined by the read transistor Q11 when reading.
゜Even if all Qs official IQII IQ+41... become conductive, the terminals N, 1, and 1 are set so that the Narita level of the terminal N1 r N is not inverted when the ti writing transistor pair Q2+IQ22 becomes conductive during writing
It must be set so that the voltage level of IN2 is inverted.

FIG. 4 is a circuit diagram showing an example of the case where the present invention is applied to a C-MOS. For the sake of clarity, we will explain the 2-port register cell. In the figure, Q+ and Q* are p-MOSFET and n-MOSFET that constitute the first inverter.
.

Ql and Q4 are p-MOS that constitute the second inverter
FET and n-MOSFET, N (is the first and second
N2 is the input/output terminal for the negative logic of Frizzoflozzo, which is created by an inverter with
n-MO8FET for protruding pair of register cells %
Q 211 Q 2 t is n-MO8FE for depression
T pair, Bll l Bltl and B, 3° B10 are two pairs of complementary signal readout lines, B11. Bl is a complementary signal write line pair, w+, W, 2 and W13, W14 is a register cell read word line pair, WII.

W22 indicates a single write word line pair, respectively.

An example of the operation of this embodiment is shown below. Before reading, the terminals of the read line pairs B11+RI2 and B13°B10 are precharged to a high level.

During reading, the read word line pair Wt+, W,.

and one or both word line pairs of W, , W, 4 are raised to high level, and the read n-MO8FlieT
When conductive, the selected read line pair B1. .

The Bll or +3ts l R+40 voltage changes complementary to the voltage at the terminal N I r N 1, respectively, and a read operation is performed. When the storage voltage of the terminal N1 is positive logic and the voltage of the terminal N is negative logic, the selected read line fl11 or nts has positive logic information of 1.
Negative logic information is read out to the 3tt spans 814, respectively. In order to prevent storage information from being destroyed during reading, n-M
Let the channel width of OSFET Q * r Q 4 be n-M
O8F'lT Q @ 1 and Q+s or Qtm and Ql4
It is desirable that the channel width be greater than or equal to the sum of the channel widths. During filling, the write word line pair Wt r w, ,
Increase the voltage of n-MO8FIT for writing to a high level.
Qtt.

Qmm is made conductive and complementary signals on the write line pair "11 * 8 @@ are written to terminals N1 and N. When writing, the voltage and voltage of the terminal N t * N are correctly inverted (
9) It is desirable that the current drive capability of the n-MOSFET Q 21 IQ 21 be at least twice that of the p-MOSFET Q + or FiQ s. Since writing and reading of this register cell are performed using complementary signals, high-speed operation is possible, and at the same time, the operating margin is also greatly increased. The write and read operations of this register cell may be performed separately or simultaneously during the same time period.

(Effects of the Invention) When the register cell of the present invention is used in a microprocessor and a series of processes of register reading, logical operations, and register writing are performed in a four-ignline manner as shown in FIG. to maximize its benefits. In other words, since the read line pair and the write line pair are separate, register cells can read and write at the same time, and register reading is performed in the first time period, and logical operation is performed in the second time period. , by writing to another register in the third time slot, a large number of logical operations can be processed in the width of one time slot.・9(10) Since calculation processing can be performed three times faster than in the case without ebrining, non-δ is advantageous for speeding up the micro-Zoro-7Ser. Also, as mentioned +4:1,
One of the advantages is that since it is possible to read and write data into and out of register cells at high speed using complementary signals, the width of the time period can also be reduced.

In the register cell of the present invention, 3. three or more pairs of read transistor pairs and three or more read line pairs are respectively coupled to the input/output terminals j of the flip-flop. It can also be used as a multi-port 1/dista cell with more than ff-to.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a conventional 2-boat register cell, Fig. 2 is an explanatory diagram of pipeline processing of m-arithmetic operations, Fig. 8i43 is a circuit diagram showing a flat embodiment of the present invention, and Fig. 4 is FIG. 2 is a circuit diagram showing an embodiment of a 2, je-Trenosta cell in which the present invention is applied to a C-MOS. In the figure, ■ is an inverter, Q is a transistor, N is a terminal, W is a word line, BVi read or write line,
R is the refresh clock line, VDD is the power supply line, and GND
indicate the ground wire, respectively. Patent applicant: NEC Corporation CrND 6ND

Claims (1)

[Claims] (1) A flip-flop from the first and second inverters that couples the output terminal of one inverter to the input terminal of the other inverter, and a pair of input/output terminals of the flip-flop and a pair of complementary flip-flops. a pair of writing transistors that respectively couple the input/output terminals of the flip-flop to a plurality of pairs of complementary readout lines; /-) register cell.