JPH04318395A - Memory cell circuit - Google Patents

Abstract

PURPOSE: To provide a memory cell circuit having plural access ports for writing/reading, which are suitable for a memory having the array of cells arranged in rows and columns. CONSTITUTION: In the pertinent memory, first word lines 20 which address- designate first ports in the respective cells of the pertinent row and second word lines 24 which address-designate second ports are arranged in the respective rows. First bit lines 22L and 22R which are connected with the first ports in the respective cells of the pertinent column and second bit lines 26L and 26R connected to the second ports are arranged in the respective columns. The respective cells contain four bipolar transistors 68, 70, 72 and 74 and the transistors 68, 70, 72 and 74 are connected with two central nodes 110 and 112. In one execution example, the collector terminals 88, 90, 94 and 98 of all the bipolar transistors are connected to power terminals.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a memory cell circuit.
In particular, the present invention is suitable for application to a memory cell made of a bipolar transistor suitable for a random access memory, and a cell structure having a plurality of ports for cell reading and writing made of FETs (field effect transistors).

0002

BACKGROUND OF THE INVENTION Memories, such as random access memories for digital computers or data processing equipment, generally consist of an array of memory cells arranged in rows and columns, with word lines signal on the bit line and the signal on the bit line. The bit lines of a column of cells act as a common port, and each cell within a column is accessed through the common port for reading or writing. For example, the memory element of a cell has a bistable flip-flop, and when reading out stored data, the state of the flip-flop is detected,
And when writing new data, the state is changed, and this detection and change are done by detecting voltage and supplying current to the common port terminal, respectively.

In order to meet the increasing demands on computers and other data and signal processing devices, the physical size of memory has been reduced by increasing the density of memory cells constructed on semiconductor circuit chips; Thus, it is advantageous to build greater storage capacity within a given physical dimension. It would also be advantageous to improve the operational response or performance of a memory so that cells of the memory can be accessed more quickly for writing new data and reading previously stored data. Reducing memory dimensions contributes to performance because signal propagation distance within the memory cell array can be reduced. Performance can also be improved by using devices that operate at higher speeds, such as bipolar transistors, and by providing multiple ports to access each cell, creating a multi-port array.

It is preferable to use FETs to reduce the physical size of a memory because the physical structure of a FET occupies less space than the physical size of a bipolar transistor. However, bipolar transistors have a much faster response. Therefore, in order to obtain the benefits of both types of transistors, it is advantageous to construct memory cells using both bipolar transistors and FETs in the circuit, and such circuits using both types are referred to as BiFET circuits. call.

[0005]

The problem is that currently available memory circuits do not combine both features of the BiFET structure and multiple ports for each cell, resulting in the inability to achieve the performance described above. I have it too. Furthermore, the large area of the doped semiconductor regions within a memory chip is susceptible to contamination by alpha particles emitted from the metal surfaces of the intrachip interconnects that interconnect the chip's cells, resulting in extremely large physical dimensions. This problem becomes even more difficult in cell arrays with Alpha particle contamination disrupts the operation of individual cells and causes erroneous data to be output from the memory.

[0006]

[Means for Solving the Problems] In order to solve the problems, the present invention provides first, second, third, and fourth bipolar transistors, a first node, a second node, a first, second, and Third and fourth field effect transistors (FETs)
), and the first and second transistors 68, 68A are connected to each other to form flip-flops 92, 9.
2A, and the third and fourth transistors 72, 72A
stabilizes the operating state of the flip-flop 92, 92A by adjusting the current to the transistors of the flip-flop, each transistor having a base terminal and two terminal terminals, one of the terminal terminals being an emitter terminal. and the other of the terminal terminals is a collector terminal, and the first terminal is a collector terminal.
Node 110 connects the base terminal 86 of the second transistor to the terminal terminals 88 of the first and fourth transistors.
106, and a second node 112 connects the base terminal 84 of the first transistor to the terminal terminals 90, 102 of the second and third transistors, and
ETs 76, 78 are connected to a first node 110 and a second node 112, respectively, thereby forming first ports 76, 78 for accessing the memory cells;
FETs 80 and 82 are connected to the first node 110 and the second node, respectively.
It is connected to node 112 to form a second port 80, 82 for accessing the memory cell.

[0007]

Operation: A memory consisting of an array of memory cells arranged in rows and columns, each memory cell containing a semiconductor circuit using both bipolar transistors and field effect transistors, and in which write and A memory designed to include multiple ports from which it is accessed for reading overcomes the above-mentioned problems and provides other benefits.

According to the invention, the cell includes two bipolar NPN transistors connected as a flip-flop and two bipolar PNP transistors connected as a flip-flop, the two flip-flops being interconnected to form a logic It is designed to cooperate in establishing the state. Also, the two transistors of each flip-flop act as current steering transistors for the two transistors of the other flip-flop. A first pair of N type FETs is connected to the collector terminals of the two flip-flop transistors to form the first port of the memory cell;
A second pair of FETs is connected to the collector terminals of the two flip-flop transistors to form a second port of the memory cell. Within each column of the array, the first and second pairs of bit lines are
port, and the second port to provide for simultaneous access to the memory cells. A computer using such memory can simultaneously perform multiple tasks that require reading data from the same cell of the memory, as an example of simultaneous access. Each row of the memory is provided with a first word line and a second word line for addressing a first port and a second port of each cell in the row. The word line is connected to the gate terminal of the FET of each port of each cell in the row.

In the configuration of a bipolar transistor,
It should be noted that a base-collector junction, which is different from a base-emitter junction, is used, yet has an optimal configuration to bring out the desired properties of this connection. Typically, transistors are operated in a forward mode, with current flowing from the collector region to the emitter region in an NPN transistor and from the emitter region to the collector region in a PNP transistor. However, bipolar transistors can also operate in reverse mode, in which case the current flows in the opposite direction. In the reverse mode, the current gain decreases and the magnitude of the junction voltage drop changes compared to the forward mode of operation. However, this voltage level is suitable for the operation of logic circuits such as flip-flops. Reverse mode is important here because it is used in one embodiment of the invention.

In a second embodiment of the cell, two bipolar NPN transistors and two bipolar PNP transistors are interconnected to form two cooperating flip-flops, as in the previous embodiments. , the circuit positions of the collector terminal and emitter terminal of each transistor are swapped. The four transistors operate in reverse mode. This is beneficial in the presence of alpha particle radiation originating from metal surfaces within the chip. The alpha particles propagate into the base-collector junction of the transistor, providing an instantaneous current shunt path that suddenly causes an instantaneous change in the base-collector junction voltage. This voltage change flips the cell to the opposite logic state. This destroys the data stored within that cell. The configuration of the second embodiment places the collector terminals of all four bipolar transistors of the cell in contact with the power supply terminal. Therefore, none of the base-collector junction shunt current paths causes more than a small change in the voltage across the junction, and the shunt current paths operate as base-emitter junctions in the reverse mode. The voltage change is too small to reverse the logic state of the cell. This embodiment therefore provides satisfactory memory operation even when the array of cells has large physical dimensions. The arrangement of the components in the second embodiment is in contrast to the arrangement of the components in the first embodiment, in which the emitter terminals of the four bipolar transistors of the memory cell contact the power supply terminals.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a memory system 10 having an array 12 of memory cells 14 arranged in rows 16 and columns 18. In accordance with a feature of the present invention, each memory cell 14 is provided with a plurality of ports for accessing the cell for reading or writing to the cell, as described below; 14 has two ports. A first set of word lines 20 and a first set of bit lines 22 are provided for addressing and accessing each cell 14 of array 12 via a first port of cell 14. A second set of word lines 24 and a second set of bit lines 26 are connected to array 12 via a second port of cell 14.
are provided for addressing and accessing each cell 14 of the cell 14 . In the memory system 10,
Column access circuit 28 arranged for each column 18
The column access circuit 28 accesses the column 18 via one or two pairs of bit lines 22 and 26.
interacts with the designated cell 14 of. Each column access circuit 28 has a first set 30 of column address lines.
and one of the second set 32 of column address lines.
The first pair of bit lines 22L, 22R and the second pair of bit lines 26L, 26R are activated, respectively.

System 10 includes a memory controller 34 that outputs a row address on one or both word lines of word line sets 20 and 24 and a column address on one or both of column address lines 30 and 32. By outputting an address, a particular cell of the memory cells 14 is addressed and one or both ports of the addressed cell 14 are designated. For ease of reference, subsequent bit lines 22 and 26 may be considered to be the same.
It is convenient to distinguish the left bit lines 22L and 26L on the left side of the memory cells 14 of column 18 from the right bit lines 22R and 26R on the right side of column 18. Data read from the cells 14 of any one column 18 is output from the corresponding column access circuit 28, with the data obtained via the bit line 22 being output along the output data line 36. The obtained data is output along output data line 38. Word line 20 connects to memory cell 14 via terminal 40, left bit line 22L of column 18 connects to cell 14 via terminal 42, and right bit line 22R of column 18 connects to cell 14 via terminal 44. do. Word line 24 connects memory cell 14 via terminal 46.
and the left bit line 26L of column 18 is connected to terminal 4.
The right bit line 26R of column 18 is connected to cell 14 via terminal 50. The controller 34 also connects the first pair of bit lines 52 by sending an input data signal to each column access circuit 28 via one of the first set 52 of input data lines.
activating the second set 26 of bit lines connected to the access circuit 28 by activating the bit lines 28 and sending an input data signal to each column access circuit 28 via one of the second set 54 of input data lines. It is made to be.

Illustrating the structure of column access circuit 28, column access circuit 28 includes components shown in dashed lines, including a restoring circuit that equalizes the voltage on bit line 22 after writing to cell 14. 56, a detection circuit 58 which reads out the data of the cell 14 via the bit line 22 and outputs the read data via the line 36;
This is a drive circuit 60 that performs cell writing by changing the state of the cell.

Column access circuit 28 includes a corresponding set of components for use with bit line 26; The bit line 26 includes a detection circuit 64 for reading data through the bit line 26 and outputting the read data over the line 38, and a drive circuit 66 for writing the cell 14 by passing current through the bit line 26 to change the state of the cell 14.

FIG. 2 shows a detailed configuration of one of the memory cells 14 of FIG. 1, with each cell 14 having the same configuration. In FIG. 2, word lines 20 and 24 connect to cell 14 through terminals 40 and 46, bit lines 22L and 22R connect to cell 14 through terminals 42 and 44, and bit line 26L through terminals 48 and 50. and 26R connect to cell 14. Cell 14 has two NPN
bipolar transistors 68 and 70, two PNP bipolar transistors 72 and 74 and four N type F
Including ET76, 78, 80 and 82. transistor 6
Base terminals 84 and 86 and collector terminals 88 and 90 of 8 and 70 are interconnected to form a bistable flip-flop 92. The base and collector terminals of transistors 72 and 74 are similarly connected together to form a flip-flop and are connected to transistors 68 and 70 to stabilize the two alternating states of flip-flop 92. is being done. The collector current of transistor 70 flows through the collector of transistor 72 and the collector current of transistor 68 flows through the collector of transistor 74. A collector terminal 94 of transistor 72 is connected to a base terminal of transistor 68 and a collector terminal of transistor 70, and a base terminal 96 of transistor 72 is connected to a collector terminal of transistor 68 and a base terminal of transistor 70. Similarly, the collector terminal 98 of transistor 74 is connected to the base terminal of transistor 70 and the collector terminal of transistor 68, and the base terminal 100 of transistor 74 is connected to the collector terminal of transistor 70 and the base terminal of transistor 68. FET 76 and FET 78 constitute the first of two port sets of cell 14 and operate as transfer or pass devices for coupling signals between bit line 22L and cell 14 and between bit line 22R and cell 14, respectively. . FET 80 and FET 82 constitute the second of the two port sets of cell 14, and are connected to bit line 26L and between cell 14 and bit line 26R, respectively.
It operates as a transfer device, ie, a pass device, that couples signals between the cells 14 and 14.

In operation, FET 76 and FE associated with the first of the two port sets of cell 14
The gate terminal of T78 is connected to word line 20 via terminal 40 of cell 14. The left bit line 22L is connected to the base terminal of transistor 72 through the source and drain terminals of FET 76 and terminal 42. It is connected from the right bit line 22R to the base terminal of transistor 74 via the source and drain terminals of FET 78 and terminal 44. FET 8 for the second of the two port sets of cell 14
0 and the gate terminal of FET 82 are connected to word line 24 via terminal 46 of cell 14. The left bit line 26L is connected to the base terminal of transistor 72 via the source and drain terminals of FET 80 and terminal 48. It is connected from the right bit line 26R to the base terminal of transistor 74 through the source and drain terminals of FET 82 and terminal 50.

A composition of four transistors 72, 74, 68 and 70 is connected between the voltages of two terminals of the power supply, with the higher (more positive) of the two voltages of the power supply being designated +V; The lower (more negative) of the two voltages is indicated by -V. The emitter terminals of transistor 72 and transistor 74 are connected to the +V terminal of the power supply, and the emitter terminals of transistor 68 and transistor 70 are connected to the -V terminal of the power supply. For the first of the two port sets 76, 78 of the cell 14, the relatively high voltage on the word line 20 is
ET 76 and FET 78 to conduct, energize the collector terminals of transistors 68 and 70 for reading the contents of cell 14, and to set flip-flop 92 to the desired state during writing of cell 14. Apply sufficient voltage to the base of transistor 68. For the second of the two port sets 80, 82 of cell 14, word line 2
The relatively high voltage on each FET 80 and FET 82
conduction, energizing the collector terminals of transistors 68 and 70 for reading the contents of cell 14, and setting flip-flop 92 to the desired state during writing of cell 14. Apply sufficient voltage to the base.

FIG. 3 shows in detail the structure of a cell 14A, which is another embodiment of the cell 14 shown in FIG. Cell 14A is P
It includes NP bipolar transistors 72A and 74A, which replace transistors 72 and 74 of FIG. Additionally, cell 14A includes NPN bipolar transistors 68A and 70A, which replace transistors 68 and 70 of FIG. In FIG. 3, four transistors 72A, 74
The composition consisting of A, 68A and 70A is connected between the voltages of the two terminals of the power supply and the higher of the two voltages of the power supply (
The one that is more positive) is indicated by +V, and the lower of the two voltages (one that is more negative) is indicated by -V. These four transistors 72A, 74A, 68A and 70
A operates in reverse mode. The collector terminals of PNP transistors 72A and 74A are connected to the +V terminal of the power supply, and the N
The collector terminals of PN transistors 68A and 70A are connected to the -V terminal of the power supply. The configuration of two transistors 68A and 70A forms flip-flop 92A, which functions similarly to flip-flop 90 of FIG. Two transistors 72A and 74A are connected together to form a flip-flop and are connected to transistors 68A and 70A to act as current steering transistors to stabilize the two alternating states of flip-flop 92A. do. Current flows from the emitter terminal 104 of transistor 72A via emitter terminal 102 of transistor 70A, and current flows from emitter terminal 108 of transistor 74A via emitter terminal 106 of transistor 68A.

In cell 14 of FIG. 2, all four emitter terminals of four transistors 72, 74, 68 and 70 contact the power supply terminal, while in cell 14A of FIG. ,
All four collector terminals of 68A and 70A contact the power supply terminals. The circuitry in both cell 14 and cell 14A is constructed on a semiconductor chip, which typically includes a large number of cells and associated control circuitry. These chips are large enough to exhibit significant sensitivity to alpha particles that can interfere with cell operation. Alpha particles are, for example, transistor 6
8A into the collector region, creating an instantaneous shunt current path between the collector and base terminals of transistor 68A. Since the base-collector junction in the reverse mode of operation functions as a base-emitter junction, the voltage across the junction is only small. Therefore, the instantaneous shunt current path can cause only a small voltage change across the base-collector junction, which is too small a change to reverse the logic state of cell 14A. In the configuration of the cell 14A in FIG. 3, the collector terminal and power supply terminal are connected to transistors 72A, 74A,
Advantageously, reducing the sensitivity of cell 14A operation to the possible presence of alpha particles at 68A and 70A ensures proper operation of cell 14A.

The interconnections and operation of the circuit elements of cell 14A are similar to those of cell 14, except that the collector and emitter terminals described above have been interchanged. Thus, the emitter terminal of transistor 68A in cell 14A of FIG. 3 is connected via node 110 to the base terminal of transistor 72A, the base terminal of transistor 70A, and the emitter terminal of transistor 74A. The emitter terminal of transistor 70A is connected via node 112 to the base terminal of transistor 74A, the base terminal of transistor 68A, and the emitter terminal of transistor 72A. Node 110 is connected to bit line 22L through FET 76 and terminal 42, and to bit line 26L through FET 80 and terminal 48. node 1
12 is connected to bit line 2 via FET 78 and terminal 44.
2R and, via FET 82 and terminal 50, to bit line 26R. FET76 and FET
78 is the first of two port sets in cell 14A.
The bit line 22L and the cell 14A each operate as a transfer device, that is, a pass device, for coupling signals between the bit line 22L and the cell 14A, and between the bit line 22R and the cell 14A. FET80 and FET
82 is the second of the two port sets of cell 14A.
The bit line 26L and the cell 14A each operate as a transfer device, that is, a pass device, for coupling signals between the bit line 26L and the cell 14A, and between the bit line 26R and the cell 14A.

For the first of the two portsets of cell 14A, the relatively high voltage on word line 20 causes each FET 76 and FET 78 to become conductive, causing the transistors to read out the contents of cell 14A. Voltage is applied to the emitter terminals of 68A and 70A to provide sufficient voltage to the base of transistor 70A or transistor 68A to set flip-flop 92A to the desired state during writing of cell 14A. Cell 14A
With respect to the second of the two port sets, the relatively high voltage on word line 24
T80 and FET 82 are placed in a conductive state, energizing the emitter terminals of transistors 68A and 70A for reading the contents of cell 14A, and transistor 70A or 70A for setting flip-flop 92A to the desired state during writing of cell 14A. Apply sufficient voltage to the base of transistor 68A.

While the invention has been particularly illustrated and described in accordance with the best preferred embodiment thereof, as noted above, various changes may be made in both form and detail without departing from the spirit and scope of the invention. It's okay.

[0024]

Effects of the Invention In both the cell 14 in FIG. 2 and the cell 14A in FIG.
Only one exists. However, according to the present invention, more pairs of FETs are used at node 110 and node 11.
More ports can be provided by connecting each pair of FETs to an additional pair of bit lines and addressing them by an additional word line.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram of a memory system including an array of memory cells each having a plurality of ports.

FIG. 2 is a connection diagram schematically showing the memory cells of the system of FIG. 1 according to a first embodiment of the present invention.

FIG. 3 is a connection diagram schematically showing the memory cells of the system of FIG. 1 according to a second embodiment of the present invention.

[Explanation of symbols]

10...Memory system, 12...Array, 14, 14
A...Memory cell, 16...Row, 18...Column, 2
0...first set of word lines, 22...first set of bit line pairs, 24...second set of word lines, 26...second set of bit line pairs, 28...
Column access circuit, 30...first set of column address lines, 32...second set of column address lines, 34...memory controller, 36, 38...output data lines, 40, 42, 44, 46, 48 ,50...
... terminals, 52 ... first set of input data lines, 54
. . . second set of input data lines, 56, 62 . . . restorage circuit, 58, 64 . . . detection circuit, 60, 66 . 72A, 74, 74A...P
NP bipolar transistor, 76, 78, 80, 82
... N-type FET, 84, 86, 96, 100 ... Base terminal, 88, 90, 94, 98 ... Collector terminal, 92
, 92A... Bistable flip-flop, 102, 104
, 106, 108... emitter terminal, 110, 112...
…node.

Claims (6)

[Claims] 1. First, second, third and fourth bipolar transistors, a first node and a second node, and a first and second bipolar transistor.
, third and fourth field effect transistors (FETs), wherein the first and second transistors are interconnected to form a flip-flop;
and the fourth transistor stabilizes the operating state of the flip-flop by adjusting current to the transistor of the flip-flop, each transistor having a base terminal and two terminal terminals, one of the terminal terminals being The other of the emitter terminals and the terminal terminals is a collector terminal, the first node connects the base terminal of the second transistor to the terminal terminals of the first transistor and the fourth transistor, and the second node connects the base terminal of the second transistor to the terminal terminals of the first transistor and the fourth transistor. The base terminal of the first transistor is connected to the terminal terminals of the second transistor and the third transistor, and the first and second FETs are connected to the first node and the second node, respectively, so that the memory forming a first port for accessing the memory cell; and the third and fourth FETs are connected to the first node and the second node, respectively, thereby forming a second port for accessing the memory cell. Characteristic memory cell circuit. 2. Collector terminals of the first and fourth bipolar transistors are connected to the first node, and collector terminals of the second and third bipolar transistors are connected to the second node. The memory cell circuit according to claim 1. 3. Emitter terminals of the first and fourth bipolar transistors are connected to the first node, and emitter terminals of the second and third bipolar transistors are connected to the second node. The memory cell circuit according to claim 1. 4. A memory system comprising an array of memory cells arranged in rows and columns, each cell having a first access port and a second access port; a first word line and a second word line disposed within each said row respectively addressing a second port and providing for reading and writing cells via a port addressed by one of said word lines; a first bit line and a second bit line arranged in each column so as to be connected to the first port and the second port in the cell of the column, respectively; , second
, third and fourth bipolar transistors, first nodes and second nodes, and first, second, third and fourth field effect transistors (FETs), the first and second transistors comprising: the third and fourth transistors being interconnected to form a first flip-flop; and the third and fourth transistors being interconnected to form a second flip-flop and regulating current to the transistors of the first flip-flop. to stabilize the operating state of the first flip-flop, each transistor having a base terminal and two terminal terminals, one of the terminal terminals being an emitter terminal and the other of the terminal terminals being a collector terminal; , the first node connects the base terminal of the second transistor to the terminal terminals of the first and fourth transistors, and the second node connects the base terminal of the first transistor to the second and third transistors. connected to the terminal terminals of the first and second FETs.
are connected to the first node and the second node, respectively, to form the first port, and the third and fourth FETs are connected to the first node and the second node, respectively.
A memory system configured to form the second port by being connected to a node. 5. In each of the memory cells, collector terminals of the first and fourth bipolar transistors are connected to the first node, and collector terminals of the second and third bipolar transistors are connected to the second node. The memory system according to claim 4, characterized in that the memory system is connected. 6. In each of the memory cells, emitter terminals of the first and fourth bipolar transistors are connected to the first node, and emitter terminals of the second and third bipolar transistors are connected to the second node. The memory system according to claim 4, characterized in that the memory system is connected.