JPS63197088A - Multi-port memory cell - Google Patents

Abstract

PURPOSE:To speed-up the rewriting of data by interrupting a bidirectional transfer gate constituting a flip flop circuit only to connect two levels of invertors in series at the time of write action by a write control line in a data storage means. CONSTITUTION:Since the write control line Wp goes to 'L' level in the write action, a transfer gate 26 becomes in a non-conductive state and the output of the invertor 24 is not connected to the input of the invertor 22 in a flip flop 2. Therefore, the flip flop circuit 2 goes to a mere constitution where two levels of invertors are connected in series, so that one of data in a bit line Bw1 and data in a bit line Bw2 is selected by a word line W1 or W2 and the transfer gate 4 or 6 goes to a conductive state to fix the electric potential of a node Q. When the electric potential of the node Q is fixed, the electric potential of the node Q* is fixed by the invertor 22. At this time the collision of the data does not occur because the flip flop circuit 2 has a simple constitution where two levels of invertors are connected in series and the rewriting of the data can be executed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a multiport memory cell necessary for constructing a multiport memory.

BACKGROUND OF THE INVENTION Conventionally, in order to configure a multi-port memory, memory cells of a static random access memory are mostly multi-ported.

FIG. 2 shows a conventional multiport memory cell. Second
The figure shows an example of a multi-port memory cell having two write/read ports and two read-only ports.

Inverters 22 and 24 constitute flip-flops for storing data. Word lines W1 and W2 select words for both write and read operations, and word lines W3 and W4 select words for only read operations. Bit lines B1, B1*.

B2. B2* is a bit line used for reading and writing operations, and bit lines B3 and B4 are bit lines exclusively used for reading operations.

In a write operation, either word line W1 or W2 is selected and the transfer gate (30, 32 or 34, 3e) of the multi-board memory is made conductive, and the bit line (B1°B1))C or B2,
Rewrite to the write data in B2*). At this time,
For example, if the bit line is B 1 = "H'", B1*=
As “L”, the state of the flip-flop is data “L”.
``(Q2 ``L'', Q* = ``H''), in the write operation, the data on the bit line and the data stored in the flip-flop collide, so the DC
A path (there is a current bus flowing from the power line through the P-channel MOSFET, through the N-channel MO8FFT, and into the ground line). Of course, in order to perform a write operation, the drive capacity of the write circuit must be sufficiently large between the drive capacity of the inverter forming the flip-flop and the drive capacity of the write circuit that drives the bit line. If there is such a data collision between the write circuit and the flip-flop, it is difficult to speed up the write operation.

Furthermore, if there is a data collision, a DC path is created, which leads to an increase in current consumption.

Problems to be Solved by the Invention In conventional multiport memory cells, it is difficult to speed up operation cycles for both read and write operations. On the other hand, in order to improve the performance of a processing device using a multi-port memory, it is desired to speed up the operation cycles of both read and write operations of the multi-port memory.

The present invention has been developed in view of this problem, and speeds up the write operation by preventing collision between the data stored in the multiport memory and the data on the bit line that is not to be rewritten during the write operation. . This provides a multi-port memory cell that can perform both read and write operation cycles at high speed.

Means for Solving the Problems In order to solve the above problems, the present invention provides a write control line, m write-only bit lines, n read-only bit lines, and n (however, n) bit lines. m) word lines, data storage means, m writing means, and n reading means, the data storage means having a first inverter, a second inverter, and a bidirectional transfer gate. the output of the first inverter is connected to the input of the second inverter, the output of the second inverter is connected to one node of the bidirectional transfer gate, and the other node of the bidirectional transfer gate is connected to the input of the second inverter. The write control line is connected to the input of an inverter, and the write control line is used to turn the bidirectional transfer gate into a non-conductive state during a write operation.
The SFETs are connected in series with their sources connected to a ground line and their drains connected to a read-only bit line, with one of their two gate inputs connected to a word line and the other connected to the first or second of said data storage means. The writing means is connected to the output of an inverter, and the writing means is one n-channel MOSFE.
The multi-port memory cell has a source connected to a write-only bit line, a drain connected to an input of the first inverter of the data storage means, and a gate connected to a word line.

According to the above-described structure, the present invention has a structure in which, during a write operation, the bidirectional transfer gate of the flip-flop of the data storage means is brought into a non-conductive state by the write control line, thereby cutting off the feedback path of the inverter.

This means that two stages of inverters are simply connected in series, and thereby data can be easily rewritten. From this, it is possible to speed up the write operation.

Embodiment FIG. 1 is a circuit diagram showing an embodiment of a multiport memory cell of the present invention. In FIG. 1, Wp is a write control line, Bwl, Bw2 are write-only bit lines, Br1
．． Br2. Br3 and Br4 are read-only bit lines,
Wl, W2. W3. W4 is a word line, 2 is a data storage means, 4, 6 is a write means, and 8, 10, 12.14 is a read means.

Similar to FIG. 2, FIG. 1 shows an example having two write and read ports and two read-only ports.

The write means is composed of a transfer gate for transferring the signal of the write-only bit line to the data storage means. The reading means connects two MO8FIi:Ts in series to transfer the data in the data storage means to a read-only bit line corresponding to the selected word line, and connects the word line to the gate of one MOSFET and the other The storage data is connected to the gate of the MOSFET, the source is connected to the ground line, and the drain is connected to the read-only bit line.

In the write operation, the write control line Wp is “L”
The transfer gate 26 is in a non-conducting state and the output of the inverter 24 of the flip-flop 2 is not connected to the input of the inverter 22. As a result, the flip-flop circuit 2 has a configuration in which two stages of inverters are simply connected in series, so that the bit lines BW1. BW
Either one of the data at node Q is selected by word line W1 or W2, transfer gate 4 or 6 becomes conductive, and the potential at node Q is determined. When the potential of node Q is determined, the inverter 22 determines the potential of node Q*.

At this time, the flip-flop circuit 2 is simply an inverter 2.
Since the stages are connected in series, data can be rewritten at high speed without data collision.

In the read operation, the write control line Wp is set to ``H''
Since the transfer gate 26 becomes conductive, the flip-flop circuit 2 retains the stored data because the output of the inverter 24 is electrically connected to the input of the inverter 22. by this,
Node Q.

Since the potential of Q* is determined, a read operation is performed by selecting a port to be read using a word line. The bit line of the port to be read is precharged to H'' level, and depending on the selection of the word line, it is held at tt Hn level or changes to tt 1.'' level depending on the stored data.

Further, even when the number of multi-boards is increased, the load on the inverters 22 and 24 can be applied evenly, so that it is possible to speed up the cycles of both the write operation and the read operation.

Effects of the Invention According to the present invention, the data storage means for storing data is configured by simply connecting two stages of inverters in series by cutting off the bidirectional transfer gate that constitutes a flip-flop circuit during a write operation using a write control line. By doing so, it is possible to rewrite data at high speed, and thereby both read operation and write operation cycles can be realized at high speed.

Furthermore, since there is no collision between write data and stored data in a write operation, there is no need for a C pass, which is effective in reducing power consumption.

Furthermore, even when the number of multi-port ports is increased, the load can be equally divided between the two inverters of the flip-flop circuit, making it possible to achieve high-speed cycles for both read and write operations. Can be done.

4. Brief Description of the Drawings FIG. 1 is a circuit diagram showing an embodiment of the multi-port memory cell of the present invention, and FIG. 2 is a circuit diagram showing a conventional multi-port memory cell.

11.

2...Flip-flop circuit, 4,6...
...Writing transfer gate, 8, 10, 12
゜14...Transfer gate for reading.

Claims (1)

[Claims] a write control line, m write-only bit lines,
n read-only bit lines and n (where n>m
), a data storage means, m writing means, and n reading means, and the data storage means has a first inverter, a second inverter, and a bidirectional transfer gate. the output of the first inverter is connected to the input of the second inverter, the output of the second inverter is connected to one node of the bidirectional transfer gate, and the other node of the bidirectional transfer gate is connected to the input of the second inverter. The write control line is connected to the input of an inverter, and the bidirectional transfer gate is made non-conductive during a write operation using the write control line. and connect the drain to the read-only bit line,
One of the two gate inputs is connected to a word line, and the other is connected to the output of the first or second inverter of the data storage means, and the write means has one n-channel MOSFET, and the source is connected to the output of the first or second inverter of the data storage means. A multi-port memory cell configured by being connected to a write-only bit line, having a drain connected to an input of a first inverter of the data storage means, and having a gate connected to a word line.