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JPS60178620A - Manufacture of semiconductor substrate - Google Patents

Manufacture of semiconductor substrate

Info

Publication number
JPS60178620A
JPS60178620A JP3347484A JP3347484A JPS60178620A JP S60178620 A JPS60178620 A JP S60178620A JP 3347484 A JP3347484 A JP 3347484A JP 3347484 A JP3347484 A JP 3347484A JP S60178620 A JPS60178620 A JP S60178620A
Authority
JP
Japan
Prior art keywords
silicon
film
magnesia spinel
single crystal
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3347484A
Other languages
Japanese (ja)
Inventor
Akihiko Ishitani
石谷 明彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3347484A priority Critical patent/JPS60178620A/en
Publication of JPS60178620A publication Critical patent/JPS60178620A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

PURPOSE:To obtain an silicon-on-insulator having a large area by forming the triple structure of magnesia spinel-SiO2-silicon, using an opening section in the structure as a seed and depositing a single crystal silicon film on the whole surface of a wafer in a homoepitaxial manner. CONSTITUTION:An epitaxial film 11 consisting of MgO.Al2O3 is grown on an Si single crystal substrate 10. When a wafer is thermally oxidized, oxygen diffuses to silicon through magnesia spinel, and SiO2 is formed between magnesia spinel and silicon. A striped pattern is formed to the wafer having obtained triple structure of magnesia spinel-SiO2-silicon. The wafer is charged to an epitaxial growth device, and silicon is deposited. Silicon is not deposited on magnesia spinel because a source gas SiH2Cl2 contains Cl at that time. The film 11 is grown selectively in an epitaxial manner while using silicon in opening sections as seeds. The whole surface is coated with a single crystal 13 in which there is no micro-twin of silicon.

Description

【発明の詳細な説明】 本発明は表面に絶縁膜のパターンを有する単結晶シリコ
ン基板上K、シリコンエピタキシャル膜を気相で成長さ
せる方法VClする。
DETAILED DESCRIPTION OF THE INVENTION The present invention describes a method of growing a silicon epitaxial film in a vapor phase on a single crystal silicon substrate having an insulating film pattern on its surface.

絶縁基板上の単結晶薄膜を能動層として用〜・た集積回
路は、素子間の分離が容易であり、また寄生容量を低減
できることから、高密度化、高速化、高耐圧化に適して
いる。絶縁基板上に単結晶膜を形成する方法としては、
シリコンオンサファイアやシリコンオンスピネルのよう
に単結晶絶縁物基板上に単結晶半導体膜を形成する方法
、非晶質絶縁物基板上に多結晶あるいは非晶質のシリコ
ンを堆積し、レーザ等の熱源九より7二−ル、Iして再
結晶化する方法がある。これらの方法のうちへテロエピ
タキシャル法では、基板とシリコン膜の格子不整により
マイクロツイン等の格子欠陥が発生し、そのためシリコ
ン膜中の易動度がバルクシリコン中での易動度の値より
小さいとい5欠点がある。また、再結晶化法は大面積の
単結晶膜を形成することは難しく、まだ実用化には遠い
Integrated circuits that use a single crystal thin film on an insulating substrate as an active layer are suitable for higher density, higher speed, and higher voltage resistance because elements can be easily separated and parasitic capacitance can be reduced. . As a method for forming a single crystal film on an insulating substrate,
A method of forming a single crystal semiconductor film on a single crystal insulating substrate such as silicon on sapphire or silicon on spinel, or depositing polycrystalline or amorphous silicon on an amorphous insulating substrate and using a heat source such as a laser. There is a method of recrystallizing from 9 to 7 yl, I. Among these methods, in the heteroepitaxial method, lattice defects such as microtwins occur due to lattice misalignment between the substrate and silicon film, and therefore the mobility in the silicon film is smaller than the value of the mobility in bulk silicon. There are five drawbacks. Furthermore, it is difficult to form a large-area single crystal film using the recrystallization method, and practical application is still far away.

シードを用いることができる場合に制限されるが、シリ
コン気相成長法によりても絶縁物上のシリコン単結晶膜
な得ることができる。
Although limited to cases where seeds can be used, a silicon single crystal film on an insulator can also be obtained by silicon vapor phase epitaxy.

しかしながら、この方法(エビタキシャルラテラルオー
パーグ1−ス: ELO)は、通常のエピタキシャル成
長条件で成長させると絶縁膜上にシリコン微粒子が析出
することを防ぐことができない。それを防ぐため釦、堆
積とガスエツチングを繰り返す方法では、ウェーハー面
に平行な方向の成長速度のウェーハー面に垂直な方向の
成長速度に対する比がほぼ1対lで広い面積でシリコン
オンインシェレーターを形成するためには必然的にエビ
成長シリコン膜の厚さが厚くなってしまう。
However, this method (Evitaxial Lateral Overgrowth: ELO) cannot prevent silicon fine particles from precipitating on the insulating film when grown under normal epitaxial growth conditions. In order to prevent this, in the method of repeating deposition and gas etching, the ratio of the growth rate in the direction parallel to the wafer surface to the growth rate in the direction perpendicular to the wafer surface is approximately 1:1, and the silicon-on-in-shell film is deposited over a wide area. In order to form a shrimp-grown silicon film, the thickness of the shrimp-grown silicon film inevitably becomes thicker.

また、成長中に塩酸ガスを導入しZ絶縁物上にシリコン
を堆積させない方法では成長と共にファセットが発達り
広いシリコンメンインシ菖レータ−を得ることができな
かった。
Further, in a method in which hydrochloric acid gas is introduced during growth and silicon is not deposited on the Z insulator, facets develop as the growth progresses, making it impossible to obtain a wide silicon oxide layer.

本発明は、このようなシードを用いた気相成長法での問
題を解決し、かつヘテーエピ成長法や再結晶化法よりも
優れた結晶性を有するエビ成長シリコン膜より成るSo
l基板を製造する方法を提供するものである。
The present invention solves the problems with the vapor phase growth method using such seeds, and also provides a So-grown silicon film made of a shrimp-grown silicon film that has better crystallinity than the epitaxial growth method or the recrystallization method.
The present invention provides a method for manufacturing a 1-substrate.

すなわち、シリコン単結晶上圧マグネシア@スピネルエ
ピタキシャル膜を形成し、次いで熱酸化法によってマグ
ネシア−スピネル膜を通してシリコン単結晶を酸化tて
マグネシアスピネル:SiO。
That is, a magnesia@spinel epitaxial film is formed on a silicon single crystal, and then the silicon single crystal is oxidized through the magnesia-spinel film by a thermal oxidation method to form magnesia spinel:SiO.

:シリコンの3重構造を形成し1次いでマグネシウム蒸
気lしおよび5ly2をパターンニングしてシリコン単
結晶の開口部を設け、その開口部をシードとしてウェー
ハー全面にホモエピタキシャルに単結晶シリコン膜を堆
積すること忙よって大面積のシリコンオンインシ諷レー
タ−を得るものである。
: Form a silicon triple structure, then apply magnesium vapor and pattern 5ly2 to form a silicon single crystal opening, and homoepitaxially deposit a single crystal silicon film over the entire wafer surface using the opening as a seed. As a result, a large-area silicon-on-in-silicator is obtained.

ここで810□は誘電率が低く、形成することが容易で
あるので、インシ孤し−タ一層の厚さをかせいで寄生容
量を低減させるために挿入されている。また、マグネシ
アスピネル膜は、Ctを含むシリコンのンースガスでは
、その上にシリコンが堆積せず、また、シリコンとの格
子不整が小さいのでラテラルエピ成長時にオーバーグロ
ースの妨げにならないのでウェー/−−面内方向の成長
速度がStO,上のELOより速くなることを利用する
ためKvtけられている。
Here, 810□ has a low dielectric constant and is easy to form, so it is inserted to increase the thickness of the insulator layer and reduce parasitic capacitance. In addition, with a silicon source gas containing Ct, the magnesia spinel film does not deposit silicon on it, and since the lattice mismatch with silicon is small, it does not interfere with overgrowth during lateral epitaxial growth. Kvt is set to take advantage of the fact that the growth rate in the direction of StO is faster than that of ELO.

以下に本発明によるSOI基板の作成方法な実施例に従
って詳細に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Below, a method for manufacturing an SOI substrate according to an embodiment of the present invention will be described in detail.

実施例 金属マグネシウム及び塩化アルミラムを蒸発させて、そ
れぞれマグネシウム蒸気及び塩化アルミニウム蒸気とし
、これをN2ガスによって輸送し、別にN ガスによっ
て輸送された酸素ガスと混合Wネジ7スピネルを81単
結晶基板上にエピタキシャル成長した。第1図はこのエ
ピタキシャル成長に用いた気相エピタキシャル装置を示
【、た。
Example Metallic magnesium and aluminum chloride are evaporated to form magnesium vapor and aluminum chloride vapor, respectively, which are transported by N2 gas, and mixed with oxygen gas separately transported by N2 gas. epitaxially grown. Figure 1 shows the vapor phase epitaxial apparatus used for this epitaxial growth.

反応管は2重管方式で内径80悄鯛の外管lと内径70
ss*の内管2の2つからなり、さらに内管は2つの部
屋(3及び4)k分離し1部M3に塩化7100℃、部
屋“4の金属マグネシウムの温度を700℃としてXI
さぜ、ガス注入口5とガス注入口6からそれぞれN、ガ
スを101 /minの流量で流した。一方ガス注入ロ
アからN’Aガスを0.1ce/m l n 、窒素ガ
スを10 t /minの流量で流した。
The reaction tube is a double tube system with an outer tube of 80mm inner diameter and a 70mm inner diameter tube.
The inner tube is further separated into two chambers (3 and 4), and one part M3 is chlorinated at 7100°C, and the temperature of the metal magnesium in room 4 is set at 700°C.XI
First, N gas was flowed from the gas injection port 5 and the gas injection port 6 at a flow rate of 10 1 /min, respectively. On the other hand, N'A gas was flowed at a flow rate of 0.1 ce/ml n and nitrogen gas was flowed at a flow rate of 10 t/min from the gas injection lower.

成長室8には基板ホルダー9の上に設けられた( 10
0 ) Sli単結晶基板10を置き、その温度を95
0℃とした。その結果、St単結晶基板10の上に約1
4m/hrの波長速度でMO11At203のエピタキ
シャル膜が成長した。
The growth chamber 8 has a substrate holder 9 (10
0) Place the Sli single crystal substrate 10 and set its temperature to 95%.
The temperature was 0°C. As a result, approximately 1
An epitaxial film of MO11At203 was grown at a wavelength speed of 4 m/hr.

MO・At203がエピタキシャル成長するときのM 
oeAz、o、の生成反応は ない良質のエピタキシャル膜11が成長した。
M when MO・At203 grows epitaxially
A high-quality epitaxial film 11 was grown without any reactions producing oeAz, o.

X線回折二結晶法によりて、8i単結晶基板と方位の合
致した( 100 )方向のエピタキシャル膜であるこ
とを確認した。本実施例においてガス注入口から酸素ガ
ス0.IA/winの代りに炭酸ガスCO□0.IL/
mi口を供給しても同様の#i釆を得た。
It was confirmed by X-ray diffraction double crystal method that the epitaxial film was oriented in the (100) direction, which matched the orientation of the 8i single crystal substrate. In this example, 0.00% oxygen gas is supplied from the gas inlet. Carbon dioxide CO□0 instead of IA/win. IL/
A similar #i pot was obtained even when mi mouth was supplied.

得られたi、さの約1JWIマグネシアスピネルオンシ
リコン構造のウェーハーを熱酸化すると、″wマグネシ
アスピネル通して赦講がシリコンへ拡散しマグネシアス
ピネルとシリコンの間に810.が形成される。((b
)図)DRY O,中1000’c?−10時間酸化し
て約11’ sI/) S L Oz層を形成した0番
主容量を低減するためKはマグネシアスピネルよりもS
tO,の誘電率が小さいので、StO,の絶縁物層が厚
い方が好ましい。しかし、酸化時間を長くするとコスト
が上昇するので、S10.の厚さは0.5 μm−2p
mの範囲が実用的である。
When the obtained wafer with a magnesia spinel-on-silicon structure of about 1 JWI is thermally oxidized, the ``w'' diffusion into the silicon through the magnesia spinel causes 810. to be formed between the magnesia spinel and the silicon. (( b
) Figure) DRY O, middle 1000'c? - oxidized for 10 hours to approximately 11' sI/) S L In order to reduce the main capacitance of No.
Since the dielectric constant of tO is small, it is preferable that the insulating layer of StO is thick. However, increasing the oxidation time increases cost, so S10. The thickness of is 0.5 μm-2p
A range of m is practical.

このようKして得られたマグネシアスピネル:StO,
:シリコン3重構造のウェーッ、−tc@i。
Magnesia spinel obtained by K in this way: StO,
: Silicon triple structure wow, -tc@i.

μm、 ピッチ100μmのストライプ状のパターンを
形成した。((C)図)。本実施例ではストッパー用の
レジストを通常のフォトリソグラフィーの技術でパター
ンニングし、す7クテイブスバツタエツチングでマグネ
シアスピネルとStO,を同時にパターンニングした。
A striped pattern with a pitch of 100 μm was formed. (Figure (C)). In this example, a resist for a stopper was patterned using a conventional photolithography technique, and magnesia spinel and StO were simultaneously patterned using a single block batch etching process.

スパッタエツチング以外にマグネシアスピネルをHC/
=系エツチング液でウェットエッチしStO,をHF系
エツチング液でウェットエッチしてパターンニングする
ことも可能である。
In addition to sputter etching, magnesia spinel is HC/
It is also possible to pattern StO by wet etching with an HF-based etching solution.

パターンニングしたマグネシアスピネル:SIO。Patterned magnesia spinel: SIO.

:シリコンウェーハーをガランソン洗浄した後、減圧シ
リンダ型赤外線加熱方式のエピタキシャル成長装置にチ
ャージし、キャリアガスH8を120A/m1rL、ソ
ースガスSiH,(、/、を500 ce/mln、成
長温度1080℃、成長圧力50 TORHの条件でシ
リコンを堆積させた。この時ソースガスSiH,C4は
Ctを含むのでマグネシアスピネル上にはシリコンが堆
積しない。開口部のシリコンをシードとして、選択的に
エピタキシャル成長する。成長面が810.層を越え、
マグネシアスピネル表面を越えると面内方向へのラテラ
ルエピタキシャル成長が始まった。成長中にHCtは添
加されていないのでファセットの発達は少ない。従って
長時間成長させてもファセットの発達でラテラルエピタ
キシャル成長が停止することがない。
: After the silicon wafer was cleaned by Galancon, it was charged into a vacuum cylinder type infrared heating type epitaxial growth apparatus, and the carrier gas H8 was 120 A/ml, the source gas SiH, (, /, was 500 ce/ml, and the growth temperature was 1080° C.). Silicon was deposited under a pressure of 50 TORH. At this time, the source gases SiH and C4 contain Ct, so silicon is not deposited on the magnesia spinel. Using the silicon in the opening as a seed, selective epitaxial growth is performed. Growth surface exceeds the 810. layer,
Lateral epitaxial growth in the in-plane direction began beyond the magnesia spinel surface. Since HCt was not added during growth, there was little facet development. Therefore, even if it is grown for a long time, the lateral epitaxial growth will not be stopped due to the development of facets.

また、マグネシアスピネルは、ホモエピタキシャル成長
と直角方向のへテロエビ基板となり、S1ヘ の場合の
よ5にラテラルエピタキシャル成長を抑制することがな
い。
Moreover, magnesia spinel becomes a heterogeneous substrate in a direction perpendicular to homoepitaxial growth, and does not suppress lateral epitaxial growth as much as in the case of S1.

更に% SiH,C4をソースガスとした場合%マグネ
シアスピネル上には核発生することができないので、マ
グネシアスピネルに到達した反応種目マグネシアスピネ
ル上を動きラテラルエピタキシャル成長速度をt’t(
r加させる。このようKして、面と垂直方向の成長速度
を1としたとき、面内方向の成長速度が平均して11.
5となり、約10分で全面をシリコンのマイクロツイン
の見られない単結晶13でυうことができた。((d)
図)。
Furthermore, when %SiH, C4 is used as a source gas, nuclei cannot be generated on the %magnesia spinel, so the reaction species that reach the magnesia spinel move on the magnesia spinel and the lateral epitaxial growth rate is expressed as t't(
Add r. In this way, when the growth rate in the direction perpendicular to the plane is 1, the growth rate in the in-plane direction is 11.
5, and in about 10 minutes the entire surface could be coated with single crystal 13 in which no silicon microtwins were observed. ((d)
figure).

上記実施例ではマグネシアスピネルエピタキシャル成長
膜の厚さを0.1μmとした。マグネシアスピネルエピ
タキシャル膜を厚くすると平滑度が低下するので、ラテ
ラルエピタキシャル成長速度は遅くなる。マグネシアス
ピネル膜厚が簿すぎるとアイランド状のマグネシアスピ
ネル膜になり、SiO2が露出してくるのでラテラルエ
ピタキシャル成長速度が遅くなる。ラテラルエピタキシ
ャル成長速度を、ウェーハー面に垂直な方向の成長速度
の10倍以上にするKは、マグネシアスピネル膜厚を0
05μfP1〜0.2μmの間にすることが好ましい。
In the above example, the thickness of the magnesia spinel epitaxial growth film was 0.1 μm. As the magnesia spinel epitaxial film becomes thicker, its smoothness decreases, so the lateral epitaxial growth rate slows down. If the thickness of the magnesia spinel film is too small, the magnesia spinel film becomes island-like and SiO2 is exposed, which slows down the lateral epitaxial growth rate. K, which makes the lateral epitaxial growth rate more than 10 times the growth rate in the direction perpendicular to the wafer surface, reduces the magnesia spinel film thickness to 0.
It is preferable to set it between 0.05μfP1 and 0.2μm.

マグネシアスピネル膜厚な0.08μmとしたとき、ラ
テラルエピタキシャル成長速度はウェーッ\−面に垂直
な方向の成長速度の約15倍になった。またソースガス
としてはsin、cz、以外にもSiH4+HCt、5
iC4,5IHCt3、SiH,CLも使うことができ
る。
When the magnesia spinel film thickness was 0.08 μm, the lateral epitaxial growth rate was approximately 15 times the growth rate in the direction perpendicular to the wave plane. In addition to sin and cz, source gases include SiH4+HCt, 5
iC4,5IHCt3, SiH, CL can also be used.

以上述べたように、本発明は従来待られなかった気相成
長法によるシリコンオンインシーレータ−膜を形成でき
る基板を提供するものであり、その工業的価値は太きい
As described above, the present invention provides a substrate on which a silicon-on-insulator film can be formed by a vapor phase growth method, which has not been expected in the past, and has great industrial value.

【図面の簡単な説明】[Brief explanation of the drawing]

H1図はマグネシアスピネルのエピタキシャル成長装置
を示す概略断面図である。第2図(ml、(bl、(c
l(diは本発明による半導体基板の製造工種を説明す
るための概略断面図である。 1・・・・・・反応管外管、2−・・・・・反応管内管
、3.4・・・・・・原料室、5.6.7・・・・・・
ガス注入口、8・・・・・・成長室、9・・・・・・基
板ホルダー、lO・・・・・・St単結晶基板、11・
・・・・・マグネシアスピネル膜、12・・・・・・5
totll1113・・・・・・ELO単結晶シリコン
膜。
Figure H1 is a schematic cross-sectional view showing an apparatus for epitaxial growth of magnesia spinel. Figure 2 (ml, (bl, (c)
1(di) is a schematic cross-sectional view for explaining the type of manufacturing process of the semiconductor substrate according to the present invention. 1... Outer tube of reaction tube, 2-... Inner tube of reaction tube, 3.4.・・・・・・Raw material room, 5.6.7・・・・・・
Gas injection port, 8...Growth chamber, 9...Substrate holder, lO...St single crystal substrate, 11.
...Magnesia spinel film, 12...5
totll1113...ELO single crystal silicon film.

Claims (1)

【特許請求の範囲】[Claims] シリコン単結晶上にマグネシアスピネルエピタキシャル
膜を形成し、次いで熱酸化法によってマグネシアスピネ
ル膜を通してシリコン単結晶を酸化してマグネシアスピ
ネル膜とシリコンとの間KStO,膜を形成し、次いで
マグネシアスピネルおよびSiO□膜をノ(ターンニン
グしてシリコン単結晶が露出した開口部を設け、その開
口部をシード
A magnesia spinel epitaxial film is formed on a silicon single crystal, and then the silicon single crystal is oxidized through the magnesia spinel film by a thermal oxidation method to form a KStO film between the magnesia spinel film and silicon, and then magnesia spinel and SiO□ Turn the film to create an opening where the silicon single crystal is exposed, and use that opening as a seed.
JP3347484A 1984-02-24 1984-02-24 Manufacture of semiconductor substrate Pending JPS60178620A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3347484A JPS60178620A (en) 1984-02-24 1984-02-24 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3347484A JPS60178620A (en) 1984-02-24 1984-02-24 Manufacture of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS60178620A true JPS60178620A (en) 1985-09-12

Family

ID=12387540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3347484A Pending JPS60178620A (en) 1984-02-24 1984-02-24 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS60178620A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6318655A (en) * 1986-07-11 1988-01-26 Canon Inc Semiconductor device
JPS6344720A (en) * 1986-04-11 1988-02-25 Canon Inc Manufacture of crystalline deposited film
JPS63107016A (en) * 1986-03-28 1988-05-12 Canon Inc Forming method for crystal and crystal article obtained through said method
JPS63182810A (en) * 1987-01-26 1988-07-28 Canon Inc Manufacture of crystal base material

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS586147A (en) * 1981-07-03 1983-01-13 Nec Corp Semiconductor device and its manufacture
JPS5848415A (en) * 1981-09-18 1983-03-22 Hitachi Ltd Formation of semiconductor single crystal film
JPS58159322A (en) * 1982-02-26 1983-09-21 ゼネラル・エレクトリック・カンパニイ Method of forming single crystal layer on mask

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS586147A (en) * 1981-07-03 1983-01-13 Nec Corp Semiconductor device and its manufacture
JPS5848415A (en) * 1981-09-18 1983-03-22 Hitachi Ltd Formation of semiconductor single crystal film
JPS58159322A (en) * 1982-02-26 1983-09-21 ゼネラル・エレクトリック・カンパニイ Method of forming single crystal layer on mask

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63107016A (en) * 1986-03-28 1988-05-12 Canon Inc Forming method for crystal and crystal article obtained through said method
JPS6344720A (en) * 1986-04-11 1988-02-25 Canon Inc Manufacture of crystalline deposited film
JP2692804B2 (en) * 1986-04-11 1997-12-17 キヤノン株式会社 Method of forming crystalline deposited film
JPS6318655A (en) * 1986-07-11 1988-01-26 Canon Inc Semiconductor device
JP2515301B2 (en) * 1986-07-11 1996-07-10 キヤノン株式会社 Method for manufacturing semiconductor device
JPS63182810A (en) * 1987-01-26 1988-07-28 Canon Inc Manufacture of crystal base material

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