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JPS60193324A - Manufacture of semiconductor substrate - Google Patents

Manufacture of semiconductor substrate

Info

Publication number
JPS60193324A
JPS60193324A JP4984084A JP4984084A JPS60193324A JP S60193324 A JPS60193324 A JP S60193324A JP 4984084 A JP4984084 A JP 4984084A JP 4984084 A JP4984084 A JP 4984084A JP S60193324 A JPS60193324 A JP S60193324A
Authority
JP
Japan
Prior art keywords
substrate
layer
insulating film
silicon
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4984084A
Other languages
Japanese (ja)
Inventor
Naoki Kasai
直記 笠井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4984084A priority Critical patent/JPS60193324A/en
Publication of JPS60193324A publication Critical patent/JPS60193324A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To provide an epitaxial layer with better crystallization, by forming an opening through an insulating film being coated on an Si substrate, and by growing the opitaxial layer only in the opening after a polycrystalline or amorphous Si thin film touching the substrate surface is formed on the walls of the opening. CONSTITUTION:After an SiO2 film is coated on an Si substrate 11 and an SiO2 film pattern 12 with a vertical cross sectional area is formed with photolithography and reactive ion etching, a contaminated layer produced on the substrate 11 surface is removed with wet etching. Next, an amorphous Si layer 13 is deposited over all faces including top faces and side faces of the pattern 12, and the layer 13 only on the side faces of the pattern 12 is left and the other is removed with reactive ion etching. Thereafter, using H2 gas and SiH2Cl2 gas containing HCl gas of about 1vol%, an epitaxial layer 14 having the approximately same height as that of the pattern is grown. Accordingly, the epitaxial layer free from crystal defect which is surrounded by the amorphous layer can be provided.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、表面に絶縁膜パターンを有する単結晶シリコ
ン基板上に選択的にシリコンエピタキシャル層を成長さ
せるような半導体基板の製造方法に関するものである@ (従来技術の問題) 従来の半導体デバイスにおける能動素子間の分離は部分
酸化法(LOCOa法)が用いられていた。
Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor substrate in which a silicon epitaxial layer is selectively grown on a single crystal silicon substrate having an insulating film pattern on its surface. Yes (Problems with the Prior Art) A partial oxidation method (LOCOa method) has been used to isolate active elements in conventional semiconductor devices.

しかし、選択熱酸化工程における酸化層の横方向の喰い
込み(バーズビーク)が生じマスク寸法に対し変化する
ため高密度化の障害となっていた。
However, in the selective thermal oxidation step, the oxidized layer undergoes lateral bite (bird's beak), which changes with respect to the mask dimensions, which has been an obstacle to achieving higher density.

上記の欠点を改善する技術の一つとして選択エピタキシ
ャル技術がある。この方法は半導体単結晶基板上に部分
的に絶縁膜を形成し、その絶縁上には堆積することなく
露出した基板領域のみ基板と同種の半導体結晶をエピタ
キシャル成長し、その部分を素子の能動領域とするもの
である。
Selective epitaxial technology is one of the techniques for improving the above-mentioned drawbacks. In this method, an insulating film is formed partially on a semiconductor single crystal substrate, and a semiconductor crystal of the same type as the substrate is epitaxially grown only on the exposed substrate area without depositing on the insulating film, and that part is used as the active area of the device. It is something to do.

従来の選択エピ夛キシャルに用いられる基板は単結晶基
板上に絶縁膜を形成した後、絶縁膜を部分的に開口して
形成するため絶縁膜とエピタキシャル膜の界面は用いる
単結晶基板の面方位の影響を受ける。つまルエピタキシ
ャル層の表面は平滑であるが、結晶成長速度が結晶面に
よシ異なるためファセットが生じ凹凸のない平担な面が
得られなかった。これを平担化する目的で開口部の絶縁
膜側壁にのみ多結晶または非晶質シリコン薄膜を形成し
、つづいてシリコンをエピタキシャル成長させることで
基板面によらず平担な構造を形成する半導体基板の製造
方法が特願昭57−153766に記載されてしる。
The substrate used in conventional selective epitaxy is formed by forming an insulating film on a single crystal substrate and then partially opening the insulating film, so the interface between the insulating film and the epitaxial film depends on the plane orientation of the single crystal substrate used. be influenced by. Although the surface of the pinched epitaxial layer is smooth, since the crystal growth rate differs depending on the crystal plane, facets occur and a flat surface without irregularities cannot be obtained. A semiconductor substrate in which a polycrystalline or amorphous silicon thin film is formed only on the side walls of the insulating film in the opening to flatten this, and then silicon is epitaxially grown to form a flat structure regardless of the substrate surface. The manufacturing method is described in Japanese Patent Application No. 57-153766.

この半導体基板の構造について図を用いて詳しく説明す
る。
The structure of this semiconductor substrate will be explained in detail using the drawings.

第1図(a) l (b) j (C1j (d)は前
記製造方法の主な製造工程における基板の断面構造を順
を追って模式的に示したものである。第1図(a)は8
i基板1上の8i02絶縁膜に反応性イオンエツチング
等によシ所望の部分K 8 i 0.絶縁層2を形成し
たものである。この場合の反応性イオンエツチングはカ
ーボンを含むエツチングガスを主に用いるので8i0゜
エツチング後のに露出するシリコン表面に不純物汚染層
が形成される。これを防ぐために8i基板1上にあらか
じめ厚さ5ooX程度の薄い絶縁膜3を残すかあるいは
形成する必要がある。次に第1図(b)に示すように多
結晶あるいは非晶質8i′膜4を全面に堆積した後、反
応性イオンエツチングによシ絶縁膜の側壁にの゛み、多
結晶あるいは非晶質Si層を残す。第1図(a)で示し
た薄い絶縁膜3は、第1図(b)K示した多結晶あるい
は非晶質8i を反応性イオンエツチングする際のスト
ッパーとなシ8i単結晶基板1への結晶損傷や不純物汚
染を防止するものである。次に第1図(C)の薄い絶縁
膜をフッ酸を含む湿式、エツチング法で除去した後、選
択的なエピタキシャル成長を施して第1図(d)に示す
開口された8i基板上にのみSi t−堆積した平担な
エピタキシャルSi層5を得る。しかし、絶縁膜側壁を
被覆したシリコン層は絶縁膜層6を介在して単結晶シリ
コン基板と接触しないのでエピタキシャル成長中に良質
な単結晶に再配列することは困難であシ、絶縁膜の近傍
に結晶欠陥の多い層7が形成される。こうしたエピタキ
シャルシリコン層に例えばp−n 接合が設けられると
り−ク電流が発生したシ、絶縁耐圧が低下する原因とな
り製造歩留りを著しく低下する欠点があった0またシリ
コン基板に対するエツチングのストッパーの役割をする
絶縁膜3を介さずにシリコン薄膜全形成し、反応性イオ
ンエツチングによシ絶縁膜側壁2を被覆したシリコン層
が8i基板に接触して形成した半導体基板ではSi基板
上に不純物汚染層を生じる。この汚染層は900°Cの
熱処理によって一応回復できるが、絶縁膜側壁を被覆し
ていたシリコン層の結晶化が進み、結晶粒子が増大する
ためにエピタキシャル成長における単結晶への再配列化
を困難としていた。
Figure 1 (a) l (b) j (C1j (d) schematically shows the cross-sectional structure of the substrate in the main manufacturing steps of the above manufacturing method in order. 8
A desired portion K8i0. An insulating layer 2 is formed thereon. Since the reactive ion etching in this case mainly uses an etching gas containing carbon, an impurity contamination layer is formed on the exposed silicon surface after the 8i0° etching. In order to prevent this, it is necessary to leave or form a thin insulating film 3 with a thickness of about 50X on the 8i substrate 1 in advance. Next, as shown in FIG. 1(b), after a polycrystalline or amorphous 8i' film 4 is deposited on the entire surface, it is etched onto the side walls of the insulating film by reactive ion etching. Leave the quality Si layer. The thin insulating film 3 shown in FIG. 1(a) serves as a stopper during reactive ion etching of the polycrystalline or amorphous 8i shown in FIG. 1(b)K. This prevents crystal damage and impurity contamination. Next, after removing the thin insulating film shown in FIG. 1(C) using a wet etching method containing hydrofluoric acid, selective epitaxial growth is performed to form Si only on the 8i substrate with the opening shown in FIG. 1(d). A t-deposited flat epitaxial Si layer 5 is obtained. However, since the silicon layer covering the side walls of the insulating film does not come into contact with the single crystal silicon substrate through the insulating film layer 6, it is difficult to rearrange it into a high-quality single crystal during epitaxial growth. A layer 7 with many crystal defects is formed. For example, when a p-n junction is provided in such an epitaxial silicon layer, a leakage current is generated, which causes a decrease in dielectric strength and a significant drop in manufacturing yield. In a semiconductor substrate in which a silicon thin film is entirely formed without intervening an insulating film 3, and the silicon layer covering the side walls 2 of the insulating film is in contact with an 8i substrate by reactive ion etching, an impurity contamination layer is formed on the Si substrate. arise. Although this contamination layer can be recovered by heat treatment at 900°C, the crystallization of the silicon layer covering the sidewalls of the insulating film progresses and the number of crystal grains increases, making it difficult to rearrange into a single crystal during epitaxial growth. there was.

(発明の目的) 本発明の目的はシリコン単結晶基板上に形成した絶縁膜
パターンの側壁近傍にも結晶欠陥のない良質な結晶性を
有する選択エビタキシャy層を得るための半導体基板の
製造方法を提供することにある。
(Object of the Invention) The object of the present invention is to provide a method for manufacturing a semiconductor substrate for obtaining a selective epitaxy layer with good crystallinity and no crystal defects even near the sidewalls of an insulating film pattern formed on a silicon single crystal substrate. It is about providing.

(発明の構成) 本発明によればシリコン単結晶層を備えた基板上に絶縁
膜を形成し、次いで該絶縁膜の所望の部分に開口部を設
け、次いで前記開口部にのみ選択的に単結晶シリコン膜
をエピタキシャル成長する半導体基板の製造方法におい
て、絶縁膜開口部を□設けた後に露出するシリコン表面
に形成されるドライエツチングによる汚染層を除去し、
次いで多結晶あるいは非晶質シリコン薄膜を形成し、次
いで炭素を含まなりエツチングガスによシ反応性イオン
エツチングし、絶縁膜側壁に基板シリコンと接触して多
結晶または非晶質シリコン薄膜を形成することを特徴と
した半導体基板の製造方法。
(Structure of the Invention) According to the present invention, an insulating film is formed on a substrate having a silicon single crystal layer, an opening is provided in a desired portion of the insulating film, and then an opening is selectively formed only in the opening. In a method for manufacturing a semiconductor substrate in which a crystalline silicon film is grown epitaxially, a contamination layer formed on the exposed silicon surface after forming an opening in the insulating film by dry etching is removed,
Next, a polycrystalline or amorphous silicon thin film is formed, and then reactive ion etching is performed using an etching gas containing carbon to form a polycrystalline or amorphous silicon thin film on the side wall of the insulating film in contact with the substrate silicon. A method for manufacturing a semiconductor substrate, characterized by:

(実施例) 次に図を用いて本発明の詳細な説明する。第2図(a)
 (b) (c) (dlは本発明の詳細な説明するた
めの図で、主な製造工程における基板の断゛面を順を追
って示した断面模式図である。
(Example) Next, the present invention will be explained in detail using the drawings. Figure 2(a)
(b) (c) (dl is a diagram for explaining the present invention in detail, and is a schematic cross-sectional view sequentially showing the cross-section of the substrate in the main manufacturing process.

まず(100)面をもつシリコン単結晶基板11上に1
00σCで熱酸化して約2μm膜厚のSin、膜を形成
した後、通常の写真蝕刻技術と反応性イオンエツチング
法によって垂直断面をもつ8i0.絶縁膜パターン12
ft形成する。シリコン基板表面にドライエツチングに
よシ形成される汚染層を除−去tルタメPAv2化1c
ヨ、6200〜300X程度5i02膜を形成し、その
5i02膜を通常の湿式エツチングによりエツチングす
ると第2図(a)の構造を得る。
First, a silicon single crystal substrate 11 having a (100) plane is
After thermally oxidizing at 00σC to form a Si film with a thickness of approximately 2 μm, an 8i0. Insulating film pattern 12
Form ft. Removes a contamination layer formed on the surface of a silicon substrate by dry etching.
When a 5i02 film of about 6200 to 300X is formed and the 5i02 film is etched by ordinary wet etching, the structure shown in FIG. 2(a) is obtained.

次にプラズマCVD 法によシアモルフガスシリコン1
3を700 X堆積すると第2図(b)を得る。次に平
行平板型ドライエツチング装置を用いてstG/*ガス
40 cc/1ninを導入し1、圧力80mTorr
 電力密度0.1 wA−rlで反応性イオンエツチン
グするとシリコン基板面と5i02絶縁膜パタ一ン上部
のみエラエツチングガスを用いると基板中に混入する不
純物はclたけなので、不活性ガス中の熱処理によって
容易に除去できる。次に8iH,CI、とH,から構成
されるガス系にHCII を約1 vol %程度加え
900’Cから1100′Cの範囲の温度で選択的にシ
リコン基板表面にのみシリコンをエピタキシャル成長さ
せ、成長膜厚が2μmのとき第2図(d)が得られる。
Next, sheamorph gas silicon 1 was produced using plasma CVD method.
2(b) is obtained by depositing 3 at 700X. Next, stG/* gas 40 cc/1 nin was introduced using a parallel plate dry etching device, and the pressure was 80 mTorr.
When reactive ion etching is performed at a power density of 0.1 wA-rl, only the silicon substrate surface and the upper part of the 5i02 insulating film pattern are etched.If etching gas is used, only Cl impurities are mixed into the substrate, so heat treatment in an inert gas Can be easily removed. Next, about 1 vol% of HCII is added to the gas system consisting of 8iH, CI, and H, and silicon is epitaxially grown selectively only on the silicon substrate surface at a temperature in the range of 900'C to 1100'C. When the film thickness is 2 μm, the result shown in FIG. 2(d) is obtained.

前記実施例では絶縁膜側壁に形成するシリコン薄膜とし
て700A膜厚のプラズマCVD−’J”モルフガスシ
リコン薄膜を用いたが、エピタキシャル成長中に書記列
が可能であるならば、これに限定されるものでなく、減
圧CVD 法、光CVD法、スパッタリング法による多
結晶または非晶質シリコンでもよい。また、前記実施例
で、反応性イオンエツチングに用いる導入ガスとして8
 IC/ 4ガスを用いたが、カーボン等の汚染のない
ガスであればC72とArの混合ガスでもよい。
In the above embodiment, a plasma CVD-'J' morph gas silicon thin film with a thickness of 700A was used as the silicon thin film formed on the side wall of the insulating film, but the invention is not limited to this if writing alignment is possible during epitaxial growth. Instead, polycrystalline or amorphous silicon formed by low-pressure CVD, photoCVD, or sputtering may also be used.
Although IC/4 gas was used, a mixed gas of C72 and Ar may be used as long as it is free from contamination such as carbon.

また、前記実施例では絶縁膜として熱酸化によるSin
、膜を用いたが、Si、N4膜、8i0.膜を堆積した
膜、PSG膜(リンガラス膜)でもよい。
Further, in the above embodiment, the insulating film is made of Sin by thermal oxidation.
, Si, N4 film, 8i0. It may be a deposited film or a PSG film (phosphorus glass film).

また、前記実施例で、選択エピタキシャル成長に用いる
ガスとしてS I H2Cit p Hz p 1”I
 C1混合ガスを用いたが、これに限定するものでなく
sic/、4゜H,、H(l 混合ガス、5il14.
II2,14CI混合ガス等を用いてもよい。また、こ
れら混合ガスにAsH3゜PH,、B、H6等のドーピ
ングガスを含ませておいてもよい。
Further, in the above embodiment, S I H2Cit p Hz p 1”I was used as the gas used for selective epitaxial growth.
Although a C1 mixed gas was used, it is not limited to this.
II2, 14CI mixed gas or the like may be used. Further, a doping gas such as AsH3°PH, B, H6, etc. may be included in these mixed gases.

(発明の効果) 本発明を用いるとシリコン単結晶基板表面に不純物汚染
層を形成することもなく、シリコン基板と接触して絶縁
膜側壁部に多結晶または非晶質シリコン層が形成される
ために、エピタキシャル成長中での多結晶または非晶質
シリコンの再配列化が容易で、結晶欠陥のない平担なエ
ピタキシャル層を得ることができる。
(Effect of the invention) By using the present invention, a polycrystalline or amorphous silicon layer is formed on the side wall of the insulating film in contact with the silicon substrate without forming an impurity contamination layer on the surface of the silicon single crystal substrate. In addition, polycrystalline or amorphous silicon can be easily rearranged during epitaxial growth, and a flat epitaxial layer without crystal defects can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(d)は従来方法による主な製造工程に
おける基板の断面を順に示した模式的断面図であるO 第2図(at〜(d)は本発明の実施例について主な工
程における基板の断面を順に示した模式的断面図である
。 図中の番号は以下のものを示す。 1.11・・・シリコン単結晶基板、2.12・・・絶
縁膜ノきターン、3・・・薄い絶縁膜、4・・・多結晶
シリコン膜、5.14・・・単結晶化したエピタキシャ
ルシリコン領域、6・・・多結晶シリコン膜とシリコン
基板の間の薄い絶縁膜、7・・・結晶欠陥を含んだエピ
タキシャルシリコン領域、13・・・アモルファスシリ
コン薄膜。 第1図 第2図
1(a) to 1(d) are schematic cross-sectional views sequentially showing the cross sections of the substrate in the main manufacturing steps according to the conventional method. 1 is a schematic cross-sectional view sequentially showing the cross-section of a substrate in the process. Numbers in the figure indicate the following: 1.11...Silicon single crystal substrate, 2.12...Insulating film cut turn , 3... Thin insulating film, 4... Polycrystalline silicon film, 5.14... Single crystallized epitaxial silicon region, 6... Thin insulating film between polycrystalline silicon film and silicon substrate, 7...Epitaxial silicon region containing crystal defects, 13...Amorphous silicon thin film.

Claims (1)

【特許請求の範囲】[Claims] シリコン単結晶層を備えた基板上に絶縁膜を形成し、次
いで該絶縁膜の所望の部分に開口部を設け、次いで前記
開口部にのみ選択的に単結晶シリコン膜をエピタキシャ
ル成長する半導体基板の製造方法において、絶縁膜開口
部を設けた後に露出するシリコン表面に形成されるドラ
イエツチングによる汚染層を除去し、次いで多結晶ある
いは非晶質シリコン薄膜を形成し、次いで炭素を含まな
いエツチングガスによシ反応性イオンエツチングし、絶
縁膜側壁に基板シリコンと接触して多結晶または非晶質
シリコン薄膜を形成することを特徴とした半導体基板の
製造方法。
Manufacturing a semiconductor substrate by forming an insulating film on a substrate having a silicon single crystal layer, then providing an opening in a desired portion of the insulating film, and then epitaxially growing a single crystal silicon film selectively only in the opening. In this method, after forming an insulating film opening, a contamination layer formed on the exposed silicon surface by dry etching is removed, a polycrystalline or amorphous silicon thin film is formed, and then a carbon-free etching gas is used. 1. A method for manufacturing a semiconductor substrate, which comprises performing reactive ion etching to form a polycrystalline or amorphous silicon thin film on the sidewall of an insulating film in contact with substrate silicon.
JP4984084A 1984-03-15 1984-03-15 Manufacture of semiconductor substrate Pending JPS60193324A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4984084A JPS60193324A (en) 1984-03-15 1984-03-15 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4984084A JPS60193324A (en) 1984-03-15 1984-03-15 Manufacture of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS60193324A true JPS60193324A (en) 1985-10-01

Family

ID=12842269

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4984084A Pending JPS60193324A (en) 1984-03-15 1984-03-15 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS60193324A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4963506A (en) * 1989-04-24 1990-10-16 Motorola Inc. Selective deposition of amorphous and polycrystalline silicon
US4980301A (en) * 1988-12-21 1990-12-25 At&T Bell Laboratories Method for reducing mobile ion contamination in semiconductor integrated circuits
US4988632A (en) * 1990-01-02 1991-01-29 Motorola, Inc. Bipolar process using selective silicon deposition
US5202284A (en) * 1989-12-01 1993-04-13 Hewlett-Packard Company Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2
US5213989A (en) * 1992-06-24 1993-05-25 Motorola, Inc. Method for forming a grown bipolar electrode contact using a sidewall seed
US5453396A (en) * 1994-05-31 1995-09-26 Micron Technology, Inc. Sub-micron diffusion area isolation with SI-SEG for a DRAM array

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980301A (en) * 1988-12-21 1990-12-25 At&T Bell Laboratories Method for reducing mobile ion contamination in semiconductor integrated circuits
US4963506A (en) * 1989-04-24 1990-10-16 Motorola Inc. Selective deposition of amorphous and polycrystalline silicon
US5202284A (en) * 1989-12-01 1993-04-13 Hewlett-Packard Company Selective and non-selective deposition of Si1-x Gex on a Si subsrate that is partially masked with SiO2
US4988632A (en) * 1990-01-02 1991-01-29 Motorola, Inc. Bipolar process using selective silicon deposition
US5213989A (en) * 1992-06-24 1993-05-25 Motorola, Inc. Method for forming a grown bipolar electrode contact using a sidewall seed
US5453396A (en) * 1994-05-31 1995-09-26 Micron Technology, Inc. Sub-micron diffusion area isolation with SI-SEG for a DRAM array

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