JPS60149160A - High efficiency dynamic random access memory and method of producing same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to semiconductor structures and methods;
In particular, it relates to high efficiency cells for improved dynamic random access memories, as well as methods of manufacturing such cells.

DESCRIPTION OF THE PRIOR ART In the fabrication of large dynamic random access memories (RAMs here), single transistor random access memory cells are widely used to provide economical random access read/write memory cells. Information is stored as a charge on a small capacitor in this type of cell. In a typical RAM, the value of this capacity is on the order of 50 femtofarads. A binary zero is represented by a zero charge, and a binary one is represented by a charge of several hundred femtocoulombs.

In such a RAM cell, the J transistor functions as an on/off switch and connects this capacitor to a bit line shared with other RAM cells. The transistor is also connected to a word line shared by many other RAM cells.

When a word line is energized, it turns on all of the transistors connected to it, but only 11 of these transistors are with the bit line energized at the same time. Thus, when the cell is selected for a read operation, the charge stored in the storage capacitor is shared between that capacitor and the capacitance of the data line. The well-known peripheral circuits are provided for reading and writing RAM cells, while also periodically refreshing their contents.

One conventional dynamic RAM cell was a 64 Kbit 462 with a new memory capacitor (1980).
(April, p. 184). In that paper I, it is 64 kilopits) Dynamic RA for RAM
M cells are stored.

The RAM cell discussed there uses three separate layers of polycrystalline silicon to provide storage nodes, ground plates and metal lines as word lines and bit lines. Although this random access memory cell U is suitable for 64,000 bit size memories, it is difficult to implement in higher density memories for a number of reasons. First, higher memory densities have typically been achieved by reducing the cell size of individual cells in dynamic RAM while maintaining a substantially constant physical size. Accordingly, storage capacitors for individual RAM cells have become smaller and smaller, making it increasingly difficult to detect voltage changes when the bit lines for such cells are sensed.

Another drawback of many conventional dynamic random access memory cells is that they require an undesirably large amount of surface area for their fabrication. Typically, this type of cell is a switch,
Typically, transistors have been designed to be placed on the wafer surface at 1- adjacent to the area to be used with the capacitor. Besides consuming more wafer surface, this type of design requires the use of a processing process in which the transistor and capacitor are fabricated using a single step, which is therefore also non-optimal for misalignment. .

Such a structure requires vertical transfer from cell to cell through diffusion and conductive lines/lines without forming undesirable transistors.

The increase in overall roughness of the cell surface, such as that associated with the fabrication of vertical Jeannot ξ-, all creates problems such as step coverage, alignment, edge effects, fringe fields, and other well-known problems.

Furthermore, random access in such a scheme
Memory cell design requires that all areas of the transistor and all areas of the capacitor be defined, typically using photolithographic methods. As is well known, compensation for manufacturing tolerances during such processes requires a substantial increase in goo surface area. Another disadvantage of conventional random access memory cells is the limitations that this type of cell design creates in making electrical connections to the word lines and the P-I lines. This drawback arises from fabricating word lines and bit lines north of the wafer surface and fabricating many layers below the l:,11411 surface of the semiconductor structure. This makes it difficult to provide electrical connections to such lines.

Another dynamic RAM cell known in the prior art is the IEEE Transactions of El
electronicdevices, Vol ED-27,
/f6B, August 1980.

Published on page 1596 ([16 Kbit Stacked Capacitor MOS RAM (5-V Dedicated for 5V)
only■6-to pigeon 5tacked-Capac
It is described in i-tor MOS RAM month. That publication describes a memory cell in which the storage capacitor is one transistor each (formed partially on the transfer gate of an AM cell). Application to very large dynamic memory arrays is difficult for several reasons.

Firstly, due to the need to allow space to form an electrical connection to one pole of the transistor through a large number of layers, among other reasons, the cell desirably has an extremely large surface area. occupies wafer north. Providing space for electrical connections is the storage capacitor's tolerance.
It limits the area to be obtained and requires a large number of separate masking and etching steps to define the capacitor's lower plate and L side plate as well as the capacitor's dielectric. The resulting structure has an extremely rough surface morphology, which leads to the well-known difficulties of edge insulation of multiple layers, fringing effects, and fabrication of particle junctions.

Due to the particular cell structure, the word line of this cell cannot be used, so the cell has a relatively high RC constant t and operates at a slower speed than desired. Furthermore, due to the constraints imposed by the scheme of connection formation to the word line, the storage capacitor cannot occupy as large an area as desired and therefore cannot store the maximum amount of charge. SUMMARY OF THE INVENTION Invention 1- An improved dynamic RAM cell is provided that is suitable for fabricating very high density dynamic RAM on the order of 1.256 kilobits and beyond. The present invention provides a dynamic RAM cell that utilizes the entire cell area as a unique condenser.

This cell eliminates the need for metal bit lines, allowing for the creation of a simpler and more reliable electrical connection between the source and the storage capacitor.

The present invention also provides a dynamic RAM cell with a flatter morphology than conventional cells. Additionally, the present invention uses a separate implant to form such bit lines and protects them with a relatively thin insulating layer, allowing the word 9 line to cross the bit line without forming a gate. This allows for the fabrication of embedded bit lines.

The dynamic random access memory cell of the present invention provides numerous other advantages over conventional cells of choice as random access memory. Because the capacitor is stacked entirely above the switch (transistor), the cell can be fabricated in a substantially smaller wafer surface area than conventional cells. The stacking of transistors and capacitors then allows the use of methods optimized for the manufacture of each rather than a standardized method for the manufacture of both. In this way, the most suitable method can be used to make the desired type of transistor, and then the most suitable method can be used to make the desired capacitor.

The method and structure of the present invention avoids the formation of transistors by eliminating the need for .xi.-tical jumpers with diffusions. By eliminating the particle jumper, the resulting surface morphology of the cell is substantially smoother than traditional structures;
It also enables the fabrication of smaller cells with higher precision. In a preferred embodiment, metal is not required for the connection between the bit line and the transistor because the bit line is formed with a first implant or diffusion and the source/drain region is formed with a second implant or diffusion. Formed by diffusion. Lateral diffusion of impurities used in each creates a reliable contact between the two.

This particular cell arrangement allows the cell capacitor to be approximately the same size as the overall cell, maximizing the conductor/height size for a given cell size. This structure eliminates the well-known difficulty of accurately and reliably insulating the edges of the various layers, and allows reliable ξ turns of thin A silicon dioxide or other insulating materials. The well-known difficulties of application are avoided. In a preferred embodiment, the ground plate for the entire array of memory cells consists of a single sheet of electrically conductive material, which only exposes the peripheral circuitry and the pumping tips of die L). Because it is ξ-turned, the manufacturing tolerances are tighter and the overall processing method is simpler.

The special cell structure associated with the stacked array of the present invention is:
Shorting either bit lines or word lines to metal without the difficulties of forming vias through intervening layers. Exotic metals such as titanium, platinum, or metal silicides can also be readily used without significant modification of the process. This structure is easily connected to those crossed by providing electrically conductive lines at L, so that the RAM cell of the present invention can be used in microcells or memory arrays crossed by other conductive lines. It can be used in other devices where it is often desirable.

In one embodiment of the invention, the random access memory cell includes: a semiconductor substrate; a data line area for data transfer east of this substrate; a data line area and a charge storage means; a switch means such as a transistor connected for electrical connection; a lower electrically conductive region located at least partially on this switch means 1; a lower electrically conductive region located on all of this lower electrically conductive region; an insulating layer; and an upper electrically conductive region located north of the data line region, the switch means and the lower electrically conductive region.

In another preferred embodiment of the present invention, a method of fabricating a random access memory cell in a semiconductor substrate includes applying a first conductivity type impurity into the substrate opposite an electrically conductive transfer gate region and selectively forming a random access memory cell in a semiconductor substrate. a region adjacent to the transfer gate, thereby forming a north region and a drain region adjacent to the transfer gate and spaced a distance apart, and at least one bit line region in a selected region of L; forming a first electrically conductive plate connected only to the source region and overlapping the entirety of the transfer gate and the entirety of the source region; depositing at least the entire north of the plate; and forming a second electrically conductive plate at least the entire length L of the first electrically conductive plate.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1-9 depict a structure from which the method of fabricating the random access memory cell of the present invention can be obtained. As shown in Figure 1, a p-type semiconductor (100) semiconductor/recon board with a resistivity of 6-7 ohms α was used.
A first relatively thin layer 12 of silicon dioxide is formed. Silicon dioxide 12 is approximately 700 angstroms thick and is made by heating the substrate IO to a temperature of 900° C. for 30 minutes in an atmosphere of oxygen and hydrogen. On the north side of the silicon dioxide 12, a layer 14 of silicon nitride approximately 1500 angstroms thick is deposited, typically using chemical vapor deposition.
- Deposit by evaporation. A layer 16 of photoresist approximately 12,500 angstroms thick is deposited across the L-plane of nitride 14 using well known methods. Mask the photoresist layer 16 using well-known methods 1 and ξ.
[turning] to create regions 6α and I6b.

Photoresist layers 16a and 1.6.6 define field oxide regions, regions of relatively thick silicon dioxide used to electrically isolate individual devices or groups of devices from other devices. It works like this.

The areas of silicon nitride protected by mask 16 are then removed using plasma etching with a CF4 plasma. Boron or other p-type conductivity type impurities are then implanted at 1- through the openings in masking layer 16 to form field implant regions 18a, 18h1 and 18C as shown in FIG. Field oxide region I
It has an impurity concentration of about 8,2.5 X I O13 atoms/d and is formed by an ion implantation method with an implantation energy of 75 KgV. The resulting structure is then 950
In °C! As shown in FIG. 2, silicon dioxide regions 21 (1, 21b1 and 2
Form an IC. During this step, a silicon dioxide r/'i crystal layer I4 formed from the oxidation of the silicon dioxide substrate is deposited as a second
As shown in the figure, it will hold up. The resulting silicon dioxide field region 21 is approximately 8,250 Angstroms thick.

Mask ■6 is then removed 1. , a new mask 23 is formed using a photosonography method. The mask 23 and the underlying structure at this stage of the process are shown in FIG. In a preferred embodiment, mask 2
3 is also formed of photoresist and is approximately 12,500 onogstroms thick.

As will be apparent from subsequent process steps, mask 23 is used to locate the bit line areas.

The exposed portions of nitride layer 14 in FIG. 2 are then removed as illustrated by FIG. 3 and using the same method described with respect to the removal of nitride layer 14 in FIG. 1. The underlying relatively thin silicon dioxide layer 12 is also removed, for example by wet etching.

Ion implantation is used to introduce a diopter or other suitable conductive type beepant into the substrate lOO through an opening in mask 23. In a preferred embodiment, arsenic is introduced with an implant energy of 4 Q KeV to produce an impurity concentration of 5 X'I O"5 atoms/- in the substrate. The resulting focus line region 25 is In Fig. 3: Indicated by @ plane.

Generally, bit lines are connected to each transistor in the substrate as shown in FIG. 9, and are typically formed orthogonally to the word lines. This semiconductor structure is then reoxidized in steam at 950°C for 60 minutes to
A relatively thick layer of silicon dioxide 27 is created between field oxide regions 21b and 212 as shown in FIG. This relatively thick silicon dioxide 27 and arsenic implant allows for the deposition of electrically conductive material across the L-plane of bit 2-in 25 without forming undesirable gates or transistors. This recessed bitline also eliminates the need for a "bridge" with a particle jumper north of the bitline. The appearance of the structure after silicon dioxide 27 is formed is shown in FIG.
- the silicon nitride layer 4 and the silicon dioxide layer 12 are then removed from the surface of the structure; The structure is then heated to 900° C. for 98 minutes to form a layer of silicon dioxide 30 across the substrate surface between Neuert'' oxide regions 2.1b and 21C;
Its thickness is approximately 300 angstroms. Silicon dioxide 30 is the bulk gate oxide of the MO8I-transistor formed within this region. Selected p like boron
Type conductivity type impurities are then added to silicon dioxide 21h and 2I.
Introduced into the area between C. In a preferred embodiment,
6 X I 011 atoms/d boron impurity concentration is 50K
This is achieved using an implant energy of gV. These impurities form the region 32 shown in FIG.

The impurity concentration of region 32 is chosen to achieve the desired threshold voltage of the transistor to be formed, which together with the capacitor forms the random access memory cell.

A layer of polycrystalline silicon 35 is then deposited as shown in FIG.
formed across the wafer surface. In the preferred embodiment, polycrystalline silicon 35 is deposited using known chemical vapor deposition techniques to a thickness of approximately 5500 angstroms. The backside of the wafer is then etched to remove the polysilicon from the backside.

The polycrystalline silicon 35 is then doped by introducing an impurity of n-type conductivity type, such as phosphorus, to lower its resistivity to about 20 ohms/row.

As also shown in FIG. 4, a layer of photoresist 36 approximately 12,500 Angstroms thick is then deposited across the L side of the wafer and conventionally patterned to
Identify 5a135j and 36C. The photoresist field always remains on the north side of the polycrystalline silicon layer 35.

The exposed areas of layer 35 are then ablated with a plasma typically consisting of C12 and SF6.

Masking layer 36 is removed from the structure and a relatively thin layer of silicon dioxide (not shown) is formed by heating the substrate to 900° C. for 36 minutes. This relatively thin layer of silicon dioxide coats the substrate in the regions of the substrate that serve as the sources and transistors of the MOS transistors.
, bind single crystal silicon. An N-conducting type impurity, preferably arsenic, is then implanted to form the transfer gate region 35!, as shown in FIG. on the hills on each side of l/
A train area is formed. In a preferred embodiment,
This base/train region is formed by ion implantation at an energy of 6V into 50'.
resulting in an impurity concentration of O15 atoms/crIl.

Generally, the train region for each transistor is implanted over a surface area approximately similar to one of the heavy bit line regions 25 in the wafer surface. Therefore, during subsequent thermal processing steps, the impurities in the bit lines and drains will diffuse laterally and simultaneously deep into the wafer. By appropriate selection of the planar position of the bitline and drain regions, this lateral diffusion joins these two regions together, thereby connecting the drain region to the bitline. As is clear from the above description, the bit line and drain regions may be arbitrarily shaped. Their shape in the preferred embodiment is most apparent in the plan view of the structure shown in FIG.

By applying the insulating layer to the deposited silicon dioxide and heating the structure to 950 DEG C. for 13 minutes, an interpoly silicon dioxide layer 40 is created, also shown in FIG. In a preferred embodiment, silicon dioxide 40 has a thickness of 3,000 mm.
Angstrom.

A layer of photoresist 42 is deposited across the L-plane of the entire structure to a thickness of typically 12.5.00 Angstroms. The photoresist layer 42 is patterned in the north region 38I! Area 43 where electrical connection to I is desired
remove from The appearance of the structure at this stage of the process is shown in FIG.

Mask 42 is removed and a second layer of polycrystalline silicon 45 is deposited approximately 1700 m across the L-plane of the structure, as shown in FIG.
Deposited to a thickness of angstroms. The polycrystalline silicon 45 was then heated to 80 Ke. An arsenic implant is used to improve the electrical conductivity of this layer at V to a concentration of 8×10 atoms/crir.

depositing a photoresist layer 48 across the sides of the structure;
Patterning is performed to identify the lower electrode of the storage capacitor, for example by removing the bit line 25 and drain region 38 (Z) from one side as shown in FIG. The polysilicon first layer is then removed from these exposed areas using the same plasma method described for the first layer 1. The appearance of the structure at this stage of the process is depicted in FIG.

A top view of the structure illustrating the extent of the polycrystalline silicon regions is shown in FIG. 9. Each region of electrically conductive polycrystalline silicon functions as the lower plate of a capacitor for the corresponding random access memory cell. As is clear, the particular placement of each plate with respect to the underlying structure has no significance other than that the plate is electrically connected to the switch, ie, the source of the corresponding MOS device. To this extent at least, the boundaries of the individual plates of the capacitor are arbitrary. For example, all of the lower plates of the capacitors in the memory array may be rotated any angle from their position in FIG. 9, if desired. The dimensions of the lower plate of each capacitor are determined by the minimum line width necessary to ensure that the plate does not touch any of its neighboring plates.

Mask 48 is removed and approximately 300 Angstroms of silicon nitride is then deposited across the entire L-plane of the structure using chemical vapor deposition to form layer 50 shown in FIG. This structure is then heated to reoxidize any second layer of polycrystalline silicon that is exposed as a result of defects in the nitride 50. This reoxidation fills such defects with silicon dioxide and prevents shorts that would otherwise occur between the overlying layers and the second polysilicon layer 45. Across the L-plane of the silicon nitride 50 (i- and any silicon dioxide formed during the reoxidation step), about 33
A third layer of polycrystalline silicon 53 with a thickness of 0.00 Angstroms is also deposited using a chemical vapor deposition method. This third layer of polycrystalline silicon 53 is then doped with phosphorous to improve its conductivity and, if necessary, back-etched again. Another layer of photoresist is deposited across one side of the structure and patterned, and polycrystalline silicon 53 and silicon nitride 50 are etched using a plasma containing CIJ and SF6, respectively. Generally, polycrystalline silicon 53 and silicon nitride 50 are left across the entire surface of the sea urchin unless peripheral circuitry is desired to control the random access memory cell array. These well-known peripheral circuits are not shown in any of the figures, so
Polycrystalline silicon 53 and nitride 50 are L in the drawn structure.
Shown in place across the entire surface.

The fact that neither silicon nitride 50 nor polycrystalline silicon layer 53 needs to be ξ-turned provides a substantial advantage to the method and structure of the present invention over conventional methods.

Numerous well-known semiconductor fabrication problems resulting from difficulties with step coverage, edge effects, patterned fringe fields of thin insulating materials, and other effects are all avoided. The use of Plunkett insulation layers and blanket ground plates for capacitors allows for the fabrication of the largest capacitors for a given cell size, and requires masking and layout tolerances for the upper plate and insulation layer of each capacitor. Eliminate sex. The structure and method of the present invention allows chisel-turning of the edges of the upper plate and thin insulator only near the periphery of the random access memory array. This feature enables the fabrication of higher density memories than 1-1 by allowing the cell dimensions of individual RAM cells to be reduced.

The fabrication of capacitor plates above the transistors or switches used to connect the capacitors to the data bus allows optimization of the semiconductor processes involved. In conventional random access memory cells, a single process is used to fabricate the transistor and capacitor, and norothesis optimization for both functions is not easily obtained. A particular advantage of the method of the invention is that optimal transistor fabrication methods can be used without much consideration of their effect on capacitor fabrication. In contrast to conventional methods, in a preferred embodiment, the inventive method fabricates the capacitors after the transistor fabrication, allowing a more optimal method to be used for each.

As shown next in FIG. 8, a layer 60 of silicon dioxide approximately 9.800 Angstroms thick is deposited across the north face of the sea urchin. This protective layer can be heated to 900℃ for 20
Densify by heating for minutes. Another mask, not shown, is formed across the wafer and patterned to expose areas where metal connections are desired, such as N+ conductive regions or polysilicon. In the preferred embodiment, metal connections are desired to be made at periodic intervals to the first layer of polycrystalline silicon to reduce its resistance. Polycrystalline silicon 3 in the paybox <VCLPOC) 60 using a plasma containing CHF3
Etching is performed in the underlying layers as necessary to expose desired portions of the first layer of polysilicon 5, or desired portions of the third layer of polysilicon, such as those needed in the N+ region or peripheral circuitry. The mask is removed and a contact diffusion step is performed to reduce the contact resistivity.

An alloy of aluminum and 1.5% silicon is then sputtered across the metal body on one side of the wafer to a thickness of approx.
A layer 62 of 2,000 angstroms is created. Layer 62 is then masked and etched using well known photolithography techniques to form metal 62 (Z
, 62h, and 62C are defined. This metal is then turned into a base metal by heating to 500° C. for 30 minutes. A particular advantage of the method and structure of the present invention is that the present invention provides the ability to short any desired underlying layer of polycrystalline silicon by relocating the electrical connections thereto. be. As is apparent from FIG. 9, the vias are formed through material overlying J: to short either the bit line or the word line where desired. Conventional cell arrangements do not allow for this stretchability.

FIG. 8 also depicts the completed appearance of a random access memory cell of a preferred embodiment of the present invention.

As shown in FIG. 8, the cell is a transfer gate 35b.
1 source and train regions 38h and 38α (respectively), and f (a buried bit line 25 used to connect to the desired number of train 8 lanes of the AM nacelle). 45, in combination with a proximate but electrically isolated third layer of polysilicon 53. Metal 62 shorts the first layer of polysilicon at desired intervals to form the entire word line. Used to reduce physical resistance.

FIG. 9 is an F-view of the structure shown in FIG. 8 with several surrounding random access memory cells fabricated in the same substrate. Figure 9 illustrates how the cell design depicted in cross section in Figure 8 can be arranged to create extremely high density random access memory. As shown in FIG. 9, an I-series bit line 25 traverses the structure from one side to the other, with periodic scoops extending from the bit line 25 to abut the drain regions formed after the transistor pairs.

I-series polycrystalline silicon word 8 lines 35 traverse the structure from top to bottom I~, each overlaid by a metal line 62 in the preferred embodiment. This periodic shorting between metal line 62 and polysilicon line 35 reduces the effective resistance of the overall structure.

These numbers are determined by the desired first layer polysilicon wordline delay. These shorts are formed by etching openings in the insulating material overlying the third layer of polysilicon 53.

The gate oxide is thin enough and the polysilicon line 3
5 is the source and train region 38a and 3
Whenever the board is crossed between 8b and 8b, the transfer game)
35! l is formed. Second layer 45 of polycrystalline silico/
C is placed practically all north of L in the cell area. A plate of this type of polycrystalline silicon 45 is shown in FIG. Laid across the entire top surface of the structure, and therefore not shown in FIG. Provide a common insulator and grounding grate for capacitors.

FIG. 10 shows the random access memory shown in cross section in FIG. 8 and in top view in FIG.
It is an electrical circuit diagram of a cell. Word components in Figure 1Θ that correspond to those in other figures are given corresponding reference numbers. FIG. 1O shows that the word line consists of a polycrystalline silicon layer 35b and metal 62; the bit line consists of an implant region 25; and the north plate of the storage capacitor is made of a polycrystalline silicon third layer along with the power supply line. layer 5
It is illustrated that it consists of 3 parts. The switch connecting the capacitive storage to the bit line includes a MOS transistor's polysilicon gate 35b1 and train and source regions 38α and 35b (respectively). Gate oxide 3o separates the first layer of polysilicon from the source and drain regions. Is the plate of the capacitor connected to the source polycrystalline silicon 451? The second layer consists of

As explained, the first layer of polycrystalline silicon is used for the transfer gate, while the second and third layers are used to provide storage in the switch device L stack.

In the preferred embodiment A, the metal is random access.
Not used directly in memory cells, but at periodic intervals to connect word lines throughout the memory cell arrangement.

This allows the fabrication of polycrystalline silicon wordlines with very short or ZRC delays.

In the preferred embodiment, a separate implant is used for bitline fabrication and a thick layer of silicon dioxide is then formed so that the polycrystalline wordline intersects the bitline without forming a gate. The storage area of the capacitor associated with each cell occupies substantially the entire cell area, providing improved performance compared to prior art structures. Additionally, the structures and methods of the present invention provide a substantially flatter topography so that the layers overlying L can be traversed more easily and reliably, thereby improving yield and lowering cost.

The above is the fifth dynamic random access of the present invention.
A preferred embodiment of the memory cell is described below along with a method of fabricating the same. Although specific times, temperatures, thicknesses, conductivity types, and numerous other details are provided to describe the construction method and the resulting structure itself, these The details are not to be construed as limiting the invention. For example, the terms source and drain are used to refer to specific electrodes and, as is well known, may alternatively apply depending on how the cell is biased. Furthermore, the method of the present invention is applicable to the fabrication of silicon MOS devices.
-, the method and the resulting random access memory cell can be easily applied to the fabrication of metal gate MOS devices. In such an embodiment, the north/train 8 lane region is not necessarily self-aligned to the metal gate, but may be fabricated using conventional MO3 techniques.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a semiconductor substrate in which silicon dioxide and silicon nitride are layered in a J:VC manner, showing the initial structure of an embodiment of the method of the present invention. FIG. 3 is a cross-sectional view after bit line formation; FIG. 4 is a cross-sectional view after forming a bit line; FIG. Figure 5 shows the patterning of the word line and transfer gate regions and the introduction of dopant conductivity type impurities in the north region and drain. Cross-sectional view after providing regions; Figure 6 shows each FtAM
Cross-sectional view after forming a second layer of polycrystalline silicon to provide the lower grade of the cell capacitor; Figure 7 shows a cross-sectional view after forming a third layer of polycrystalline silicon to provide the lower grade of the cell capacitor; 8 is a sectional view of the completed semiconductor structure; FIG. 9 is a plan view of an array of RAM cells made in accordance with the invention; FIG. 10 is from Figure 1 9 is an electrical diagram of a single RAM cell and a circuit containing the RAM cell illustrating the relationship between the structures depicted in FIG. 9; FIG. IO2 substrate 12: Silicon dioxide layer 14: Desirable material layer 1
6: Photoresist layer 2'3 Ni? Patent applicant: National Semiconductor (5 others) Procedural amendment (method) February 1985 - Yu day 1, case description lf 5.・Evening and ＼ A7ts Memo-1--a run, 1 Totsufu 4a, rdo L 2 Ni 1 呵, 3. Relationship with the case of the person making the amendment Applicant's address % 4"> Nan? Chil t Mihun Tafu Ku Cord size-
Shi? 74. Agent

Claims (1)

[Scope of Claims] (11) Semiconductor substrate; a data line region in the substrate for transferring data; connected to the data line region and charge storage means, electrically connecting the data line region to the charge storage means as desired; a lower electrically conductive region disposed at least partially above the switch means, wherein the charge storage means comprises: a lower electrically conductive region disposed at least partially above the switch means; an insulating layer disposed thereon; and an upper electrically conductive region disposed on the insulating layer and above the data line region, the switch means and the lower electrically conductive region. (2) a semiconductor substrate; a source region and a train region of a first conductivity type spaced apart in the substrate; a memory cell disposed between the north region and the drain region; an electrically conductive transfer gate region separated from the drain region by a layer of dielectric material; an electrically conductive line connected to the transfer gate and providing a control signal to the transfer gate; a first electrically conductive plate disposed north of a portion of the electrically conductive line, the entirety of the F rune region, and the entirety of the transfer gate region; a first electrically conductive plate which is electrically connected only;
an electrically conductive plate, the first and second electrically conductive plates comprising: a second plate providing capacitor means for charge storage;
Access memory cell. (3) Introducing an impurity of the first conductivity type into the substrate on the side opposite the electrically conductive transfer gate region and within a selected area (-1) thereby forming a spaced apart source adjacent to the transfer gate. forming a line region and a drain region, and forming at least 1 bit line region connected to the roof region in the selected region; forming a first electrically conductive plate overlying the entirety; depositing a layer of insulating material over at least the entirety of the first electrically conductive plate; and depositing a layer of insulating material overlying at least the entirety of the first electrically conductive plate; forming a second electrically conductive plate on a semiconductor substrate;