JPS646489B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a one-chip microcomputer, and more particularly to a one-chip microcomputer that can accurately perform an operation test in an internal program mode.

(2) Background of the technology In recent years, one-chip microcomputers have expanded their functionality and increased memory capacity such as built-in random access memory and read-only memory. It has become necessary to do so.
In particular, in order to test whether a one-chip microcomputer operates properly under actual usage conditions, it is desired to establish an effective test method in the internal program mode, which is the operating mode when executing a user program. ing.

(3) Prior art and problems Figure 1 shows part of the configuration of a conventional one-chip microcomputer. In the figure, 1 is a read-only memory that contains a user program, etc., 2 is a random access memory used as a work area when executing the user program, and 3 and 4 are used to store address data from an internal bus 5. Address registers, 6 and 7 are address buffers, 8 and 9 are read-only memory 1 and random access memory 2, respectively.
Address decoders 10 and 11 are AND gates. The one-chip microcomputer shown in FIG. 1 also has a processor (not shown), which is connected to the internal bus 5.

In the configuration shown in FIG. 1, read-only memory 1 is used for executing user programs, etc.
When reading a program stored in
Address data is transferred from a processor (not shown) to the address register 3 via the internal bus 5.
This address data is input from the address register 3 to the address buffer 6 and decoder 8,
The signal is input to the read-only memory 1 as a selection signal. In response to the input of the selection signal, read data is output from the read-only memory 1 to the AND gate 10, and the read-only memory enable signal ROME is input to the other terminal of the AND gate 10. As a result, the AND gate 10 is opened and the read data from the read-only memory 1 is sent to the internal bus 5, and is taken into the processor and processed. Also, when reading data from the random access memory 2, address data is input from the processor to the address register 4 via the internal bus 5, and the address data is converted into a selection signal by the address buffer 7 and decoder 9. and input into the random access memory 2.
Data read from random access memory 2 is sent to internal bus 5 by opening AND gate 11 in response to random access memory enable signal RAME, and transferred to the processor.

By the way, generally speaking, one-chip microcomputers have two modes: an external program mode in which instructions are transferred from the outside to the microcomputer's internal bus, etc., and executed for operational testing, and a read-only memory stored in the microcomputer's built-in read-only memory. There is an internal program mode that runs the programmed program. Conventionally, when testing a one-chip microcomputer, instructions such as a test program are given to the processor from the outside in the external program mode and executed, and in tests in the internal program mode, instructions are stored in the built-in read-only memory. I was running a user program.

However, in the conventional method, especially when testing in internal program mode, the user program is executed and evaluated, so it is impossible to sufficiently test each part of the hardware of a one-chip microcomputer. At the same time, the test content differs from user to user and becomes complicated, which increases the time and effort required for testing, which inconveniently increases the manufacturing cost of the one-chip microcomputer.

(4) Purpose of the Invention In view of the problems with the conventional type described above, the purpose of the present invention is to provide a one-chip microcomputer that has a built-in read-only memory and a random access memory, in which a test program is stored in the random access memory. Based on the idea that this is executed in the internal program mode, the present invention aims to enable more accurate and complete testing of the microcomputer, especially in the internal program mode, with a simple configuration.

(5) Structure of the Invention According to the present invention, a read-only memory connected to a central processing unit via an internal bus and in which a user program is stored in advance; A random access memory connected to a processing device and into which a test program is written under predetermined conditions, and read-only memory address data and random access memory address data from the internal bus when the test mode is not selected. are transferred to the corresponding read-only memory and random access memory, respectively, and when the test mode is selected, the address data for the read-only memory is transferred to the random access memory, and the address data for the read-only memory is transferred to the read-only memory. a first gate circuit that prohibits input of the data, and a first gate circuit that transmits data read from the random access memory and the read-only memory when the test mode is not selected in response to a random access memory enable signal and a read-only memory enable signal, respectively. and a second gate circuit that transfers data read from the random access memory when the test mode is selected to the internal bus in response to the read-only memory enable signal. , the user program is executed when an internal program mode is selected and the test mode is not selected, execution is prohibited when the test mode is selected, and the test program is executed when an external program mode is selected and the test mode is not selected. By providing a one-chip microcomputer, the information is written to the random access memory when not selected, and executed when the test mode is selected and when the internal program mode is selected. achieved.

(6) Embodiments of the invention Examples of the invention will be described below with reference to the drawings. FIG. 2 shows the configuration around each memory in a one-chip microcomputer according to an embodiment of the present invention. In the configuration shown in FIG. 2, in addition to the conventional configuration shown in FIG.
5 etc. circuit is added.

In the configuration shown in Figure 2, the test mode signal TEST
is at a low level, AND gate 13 is closed, AND gate 14 is opened, and AND gate 1
6 and 17 are closed. Therefore, in this case, the configuration is exactly the same as the conventional configuration shown in FIG. 1, and therefore, the operation is also the same as in the case of the configuration shown in FIG. On the other hand, when the test mode signal TEST is at a high level, the read-only memory address data sent to the address register 3 via the internal bus 5 is sent to the AND gate 13 and the OR gate 1.
Decoder 9 for random access memory via 5
is input. As a result, the random access memory 2 is addressed, and if the read-only memory enable signal ROME is at a high level, the AND gates 16 and 17 are opened and the read data from the random access memory is transferred to the internal bus 5. be transferred. Therefore, by storing the test program in the random access memory, the test program can be executed in the internal program mode as if it were stored in the read-only memory 1. In this case, since the AND gate 14 is closed, the address data from the read-only memory address register 3 is not input to the read-only memory 1, and therefore the program in the read-only memory 1 is read out. Never.

FIG. 3 shows, as an example, the usage status of each memory during normal operation and during a test according to the present invention. As shown in FIG. 3a, during normal operation, a random access memory having a capacity of, for example, 256 bytes is used as a work area and data memory for executing user programs. In this case, for example, a 4-kbyte read-only memory stores a user program, and the user program is executed in the internal program mode. On the other hand, Fig. 3b
As shown in , when performing the test according to the present invention, execution of the program in the read-only memory is prohibited, and part or all of the random access memory is used as a program area and the test program is stored in the program area. Then, the test program is executed in internal program mode.

FIG. 4 is a flowchart showing the procedure for testing a one-chip microcomputer using the test circuit described above. As shown in the figure, first, the test mode signal TEST is set to 0 and the mode switching signal MOD (not shown) is set to 1 to enter the external program mode. In this state, the operation of each part of the microcomputer is tested in the external program mode, that is, by inputting instructions from the external memory to the processor via the microcomputer's internal bus, etc., and having the processor execute the instructions. . After this test is completed, a standard test program is externally written into the random access memory within the one-chip microcomputer in the external program mode. In this case, as shown in FIG. 3b, part or all of the area in the random access memory is used as a program area, into which the standard test program is written. Next, the test mode signal TEST is set to 1 and the mode switching signal MOD is set to 0 to enter the internal program mode. In this state, the standard test program written in the random access memory is executed to test each part of the microcomputer. It is done.
This allows the microcomputer to be tested in the internal program mode, which is the same mode in which the user program is executed. Note that in the normal operating state when the user program is executed, the test mode signal TEST
is set to 0 and the mode signal MOD is set to 0.

(7) Effects of the Invention As described above, according to the present invention, by simply adding simple hardware, it is possible to conduct tests in the internal program mode that corresponds to the actual usage state of a one-chip microcomputer. Chip microcomputers can be tested more completely and test accuracy can be improved, and the random access memory already built into the one-chip microcomputer can be effectively used to provide special memory for testing. There will be no need. Further, according to the present invention, unlike tests performed using user programs, tests can be performed using a standard test program common to each user, reducing the number of steps required for testing, and thus providing a one-chip test. It is possible to prevent an increase in the cost of microcomputers.

[Brief explanation of the drawing]

FIG. 1 is a partial block circuit diagram showing the configuration near each memory of a conventional one-chip microcomputer, and FIG. 2 is a partial block circuit diagram showing the configuration near the test circuit of a microcomputer according to an embodiment of the present invention. 3 is an explanatory diagram showing the usage status of the random access memory and read-only memory in the configuration of FIG. 2, and FIG. 4 is an explanatory diagram showing the test procedure performed with the configuration of FIG. 2. This is a flowchart. 1... Read only memory, 2... Random access memory, 3, 4... Address register, 5... Internal bus, 6, 7... Address buffer, 8, 9... Address decoder, 10, 11... AND gate, 12
...Inverter, 13, 14...And gate, 15
…or gate, 16, 17…and gate.

Claims (1)

[Scope of Claims] 1. A read-only memory 1 connected to a central processing unit via an internal bus 5 and in which a user program is stored in advance; A random access memory 2 into which a test program is written under certain conditions, and a read-only memory address data and a random access memory address data from the internal bus when the test mode is not selected are stored in corresponding read-only memories. , to a random access memory, and when the test mode is selected, transfers the read-only memory address data to the random access memory, and prohibits input of the read-only memory address data to the read-only memory. Gate circuits 12, 13, 14, 1
5, when the test mode is not selected, the data read from the random access memory and the read-only memory are sent to the internal memory in response to a random access memory enable signal (RAME) and a read-only memory enable signal (ROME), respectively. second gate circuits 10 and 1 for transferring data read from the random access memory to the internal bus in response to the read-only memory enable signal when the test mode is selected;
1, 16, and 17, the user program is executed when an internal program mode is selected and when the test mode is not selected, and execution is prohibited when the test mode is selected, and the test program is an external program. The one-chip program is written in the random access memory when a mode is selected and when the test mode is not selected, and is executed when the test mode is selected and the internal program mode is selected. microcomputer.