JP3105881B2 - Microcomputer and its test method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer provided with a read-only memory or the like in which a program or the like executed at the time of startup is stored, and a test method therefor.
In particular, the present invention relates to a microcomputer capable of performing a test without changing an operation mode and a test method thereof.

[0002]

2. Description of the Related Art Conventionally, when a read-only memory (hereinafter referred to as a ROM) built in a microcomputer is tested, an external ROM provided outside the microcomputer is used. Special control for performing such a test is required in addition to control for normal operation.

For example, a method of testing a built-in ROM from an external memory by switching a test mode is disclosed (Japanese Patent Application Laid-Open No. 62-254241). FIG.
FIG. 1 is a schematic diagram showing a conventional microcomputer test method described in Japanese Patent Application Laid-Open No. 62-254241.
6 (a) to 6 (c) show Japanese Patent Application Laid-Open No. 62-25424.
FIG. 1 is a schematic diagram showing an address space in various operation modes of a conventional microcomputer described in Japanese Patent Application Publication No. 1 (JP-A) No. 1-2003.

In the conventional test method, an operation mode is specified in which the address 35 of the area in the internal ROM 34 becomes a start address when the reset signal 36 is released. Also, the built-in R
In the area indicated by the address 35 of the OM 34, a jump instruction for jumping to the area of the head address in the random access memory (hereinafter, referred to as RAM) 33 or an external memory (not shown) is recorded in advance. Further, an operation mode change command is recorded in advance in the area of the head address of the RAM or the external memory.

FIG. 6 (a) shows a setting mode terminal 37.
Is set and the reset is released, the central processing unit (hereinafter, referred to as CPU) 32 stores the internal ROM 34.
From the memory to the RAM 33, and changes the memory address to the RAM 33 address. And R
The test is executed based on the instruction recorded in AM33.
When executing the test, the operation mode is changed from an operation mode in which the internal ROM 34 as shown in FIG. 6A cannot be accessed to an internal ROM 34 as shown in FIG. And an operation mode in which addresses in the RAM 33 can be accessed simultaneously. This makes it possible to access the built-in ROM 34 from the RAM 33.
34 tests can be performed.

[0006]

However, in the conventional microcomputer shown in FIG.
4 and the RAM 33 need to record the jump instruction and the mode change instruction respectively. When the present invention is applied to a microcomputer having no mode change instruction, the mode change instruction needs to be added again. is there.

Further, since the operation of the CPU may change depending on the operation mode, if the operation mode is changed to make the area indicated by the address in the internal ROM 34 accessible, the operation of the CPU also changes. May not be able to perform a normal test.

In a microcomputer having a built-in ROM, the built-in ROM cannot be replaced and its contents cannot be replaced. Therefore, when a test of the built-in ROM is performed, an instruction is read after reset is released.
The address at the address is replaced by an external ROM. FIG.
1A to 1C are schematic diagrams showing address spaces in various operation modes of a conventional microcomputer. However, if the area indicated by the address in the internal ROM is replaced by the area of the address in the external ROM, FIG.
As shown in (a), access to the area in the internal ROM may not be possible at all. Further, as shown in FIG. 7B, access to a part of the area may not be performed due to replacement of a part of the area in the internal ROM. Further, as shown in FIG. 7C, the address may change. That is, the conventional microcomputer test method may not be able to perform the test in the same state as the original operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has been made in consideration of the problems described above.
And a test method therefor.

[0010]

A microcomputer according to the present invention comprises: a read-only memory in which a program is stored; a test memory in which a test program for testing the read-only memory is stored; or a central processing unit that reads out and executes the test program, the reset signal becomes low returning the and input from the outside predetermined signal the central processing unit to an initial state
An instruction output circuit for giving an instruction for jumping to the address of the test memory only once every time to the central processing unit.

In the present invention, the test of the read-only memory is executed when a predetermined signal is inputted from the outside and the reset is released, so that it is not necessary to change the operation mode, and the operation mode to be tested in advance is not required. , It is possible to perform a test in that operation mode. Therefore, there is no fear of malfunction due to the change of the operation mode.

In the present invention, the test memory may be a read-only memory provided externally or a random access memory provided internally. If a random access memory is used, the test can be processed at high speed.

Further, the command output circuit may be operable only once every time the reset signal goes low.

A microcomputer testing method according to the present invention provides a read-only memory storing a program,
In a test method of a microcomputer having a test memory storing a test program for testing the read-only memory and a central processing unit that reads and executes the program or the test program, a predetermined signal is input from the outside. And giving the central processing unit an instruction to jump to the address of the test memory once each time the reset signal for returning the central processing unit to the initial state becomes low. And

In the present invention, the test memory includes:
It may be a read-only memory provided outside or a random access memory provided inside.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A microcomputer according to an embodiment of the present invention will be specifically described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a microcomputer according to a first embodiment of the present invention.

Built-in R storing instructions to be executed at the time of startup
The microcomputer 1 having the built-in OM3 has a built-in R
Internal bus 10 connected to OM3 and internal bus 10
Is provided. An instruction output circuit 5 for outputting a jump instruction to the CPU 7 when the ROM test signal 11 is inputted from outside and the reset is released.
Is provided. From the CPU 7 to the instruction output circuit 5,
Internal memory selection signal 9 is transmitted, and internal ROM selection signal 8 is transmitted from instruction output circuit 5 to internal ROM 3.
Further, the microcomputer 1 is provided with an input terminal 4 to which an external ROM 2 which is provided outside and stores an instruction is connected. The input terminal 4 has an external R
OM selection signal 12 is transmitted. Further, a reset signal 6 is externally input to the CPU 7 and the instruction output circuit 5.

FIG. 2 is a timing chart showing a test method in the microcomputer according to the first embodiment of the present invention. FIGS. 3A to 3C are schematic diagrams showing address spaces in various operation modes of the microcomputer according to the first embodiment of the present invention.

First, a case where the instruction output circuit 5 does not operate while the ROM test signal 11 remains low will be described.
In this case, when the reset signal 6 of the microcomputer 1 is released, the CPU 7 starts operating. The address space at this time is as shown in FIG. For this reason, the CPU 7 sets the start address 0 in FIG.
Read the first instruction from the address. Then, the CPU 7
As shown in FIG. 3A, the instructions are sequentially executed from the instruction stored at the head address of the internal ROM 3.

Next, the case where the ROM test signal 11 becomes high and the instruction output circuit 5 operates will be described. For example, as shown in FIG. 2, if the ROM test signal 11 is high before the reset signal 6 is released, the internal memory selection signal 9 goes from low to high when the reset signal 6 is released. . As a result, the instruction output circuit 5 operates, and as shown in FIG. 3B, the address in the internal ROM 3 is set to the non-selection state, that is, the internal ROM selection signal 8 is kept low, A jump instruction to an address is replaced with a CP instead of an instruction output from built-in ROM 3.
Output to U7. The instruction output circuit 5 does not operate after outputting the jump instruction once every reset release.

Thereafter, when the output of the jump instruction is stopped, the CPU 7 executes the jump instruction, and sets the internal memory selection signal 9 to low and the external ROM selection signal 12 to high. Then, the CPU 7 fetches the instruction stored in the external ROM 2. The address space at this time is
It is as shown in FIG.

Thereafter, the CPU 7 sets the internal ROM selection signal 9
Is high, the instruction output circuit 5 does not operate because it has already output the jump instruction once, and the internal ROM selection signal 8
Goes high. Therefore, as shown in FIG. 3C, access to the built-in ROM 3 becomes possible.

As described above, according to this embodiment, the built-in RO
The test of the internal ROM 3 can be performed from the external ROM 2 without changing the operation of M3, that is, in the same state as the actual operation.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing a microcomputer according to the second embodiment of the present invention.

Built-in R storing instructions to be executed at startup
The microcomputer 15 incorporating the OM 17 is provided with an internal bus 20 connected to the internal ROM 17, a CPU 23 connected to the internal bus 20, and an instruction output circuit 22. The instruction output circuit 22 outputs a jump instruction to the CPU 23 when the ROM test signal 24 is input from outside and the reset is released. Further, the microcomputer 15 is provided with an input terminal 19 to which an external ROM 16 which is provided outside and stores an instruction is connected. A reset signal 27 is externally input to the CPU 23 and the command output circuit 22. Further, the microcomputer 15 is provided with a RAM 18 in which instructions for testing the built-in ROM 17 are recorded in advance.
The contents recorded in the RAM 18 are not erased by the reset.

In the microcomputer 15 configured as described above, the operation mode is changed to a mode for executing an instruction from the built-in ROM 17 by the reset signal 27, and the ROM test signal 24 is input to the instruction output circuit 22. At this time, since the contents of the RAM 18 are not erased by the reset, the command output circuit 22 receives the reset signal 27 and the ROM test signal 24 and outputs a jump command to the CPU 23 to the address area of the RAM 18. Then, according to the instruction recorded in the RAM 18, the CPU 2
3 tests the built-in ROM 17.

As described above, according to the second embodiment, since the RAM 18 is set as the recording destination of the test command, the speed is higher than when the external ROM is set as in the first embodiment. It is possible to read the instruction at the same time. Therefore, the test time can be shortened. Furthermore,
Since the instruction output circuit 22 does not output a signal to the internal ROM 17 or the like other than the CPU 23, the circuit can be inserted without changing the connection other than the CPU 23.

[0028]

As described in detail above, according to the present invention,
There is no need to change the operation mode, and if an operation mode in which a test is to be performed is set in advance, a test in that operation mode can be performed. Therefore, all the addresses of the built-in ROM can be tested in the same manner as the actual operation without changing the address space, so that tests in various operation modes can be performed. For this reason,
There is no worry about malfunction due to change of operation mode. Further, there is no need to record the jump instruction in the external memory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a microcomputer according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a test method in the microcomputer according to the first embodiment of the present invention.

FIGS. 3A to 3C are schematic diagrams showing address spaces in various operation modes of the microcomputer according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a microcomputer according to a second embodiment of the present invention.

FIG. 5 is a schematic view showing a conventional microcomputer testing method described in Japanese Patent Application Laid-Open No. 62-254241.

FIGS. 6A to 6C are Japanese Patent Application Laid-Open No. 62-254241.
FIG. 1 is a schematic diagram showing an address space in various operation modes of a conventional microcomputer described in Japanese Unexamined Patent Application Publication No. H10-115,004.

FIGS. 7A to 7C are schematic diagrams showing address spaces in various operation modes of a conventional microcomputer.

[Explanation of symbols]

 Microcomputers 2, 16; External ROMs 3, 17; Internal ROMs 4, 19; Input terminals 5, 22; Command output circuits 6, 27, 36; Reset signals 7, 23, 32; Selection signal 9; Internal memory selection signal 10, 20; Internal bus 11, 24; ROM test signal 12; External ROM selection signal 18, 33; RAM 31; Mode change circuit 34; ROM 35; Address 37; Setting mode terminal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/22-11/26 G06F 15/78

Claims (6)

(57) [Claims] 1. A read-only memory storing a program, a test memory storing a test program for testing the read-only memory, and a central processing unit reading and executing the program or the test program And a reset signal, which receives a predetermined signal from the outside and returns the central processing unit to the initial state, becomes low.
And a command output circuit for giving a command for jumping to the address of the test memory only once every time to the central processing unit. 2. The microcomputer according to claim 1, wherein the test memory is a read-only memory provided externally. 3. The microcomputer according to claim 1, wherein the test memory is a random access memory provided inside. 4. A read-only memory storing a program, a test memory storing a test program for testing the read-only memory, and a central processing unit reading and executing the program or the test program. In the microcomputer test method, once every time a predetermined signal is input from the outside and the reset signal for returning the central processing unit to the initial state becomes low, once.
The method of testing a microcomputer, characterized in that it comprises a step of providing an instruction only to jump to the address of the test memory to said central processing unit. 5. The microcomputer test method according to claim 4 , wherein the test memory is a read-only memory provided externally. 6. The test memory according to claim 1, wherein the test memory is a random access memory provided inside.
Microcomputer test methods described in 4.