JPS6281113A - latch circuit - Google Patents

Abstract

PURPOSE:To obtain a latch circuit whose stored data is not inverted even with irradiation of an alpha ray by providing the 2nd hold loop inverting even a low level output data into a high level data and returning it to the input side. CONSTITUTION:The 2nd hold loop la is added, an output Q is inputted to a data storage section via a gate G7 to duplicate the hold loop. Supposing that Q=L is caused by the irradiation of an alpha ray at Q=H, since the output Q is at L level (even if an alpha ray is irradiated to this part, the L output remains L output), the inverted output of the gate G7 is at H level and then the noninverting output of a gate G2 goes to H and an output of an AND gate G3 goes to H, and the storage state is restored. Even with the irradiation of alpharay at the latch state of Q=L, the state of Q=L is unchanged and the state of Q=L and the inversion of Q=H is maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a launch circuit reinforced against soft errors caused by alpha rays.

[Conventional technology]

The in-phase latch circuit has a structure shown in FIG. 5, and the out-of-phase latch circuit has a structure shown in FIG. In FIG. 5, Gl and G2 are OR gates that produce inverted and non-inverted outputs, G3 is an AND gate, and SD is a gate similar to Gl and G2, but is operated by one person and produces inverted and non-inverted outputs. Data DATA is applied to one input terminal of gate GI, and the data is taken into the latch circuit when clock CLK is at L (low) level. That is, CLK
If A (L), the output of gate G1 is determined by the input data DATA, and if this is set to H (high) level, one input of AND gate G3 becomes H, and the inverted output of gate SD is H, so gate G2 The non-inverting output of the gate G2 becomes H, so the output of the ant gate 03 becomes H1, so the latch circuit output Q becomes Hl, and since this H output is input to the gate G2, the non-inverting m power of the gate G2 is held at H. , the non-inverted output is held at L, which becomes the Q output of the latch circuit. Even if the clock CLK returns to H, the H output of gate G2 is held at the H output of gate G3, and the H output of gate G1 is held at the H output of gate G2, so the H output of gate G3 is also held. Thus, Q=H and Q=L are maintained.

When the clock CLK is the input data DATA-hLL when data is taken in at L level, the inverted output of GI and therefore the non-inverted output of H1 is output, and the output of G3 is L, therefore Q.
=L, G) The non-inverted output of G2 is H1, and the inverted output is L. When the clock CLK becomes H, the inverted output of gate SD becomes L, the inverted output of gate G2 becomes H1, and the non-inverted output of H1 becomes low.
The output of G3 becomes Q=L, and the state at the time of data capture is maintained. Loop l has the data latch function.

The gates SD, GA to G6 of the circuit in FIG. 6 are also of the same type as the gates in FIG. Become.

Further, since the inverted output of the gate SD is H, the output of the gate G5 is L1, so the inverted output Q of the date Ga is H1, and the non-inverted output becomes L. When the clock CLK becomes H, the inverted output of the gate Gs is L1, since the inverted output of the gate SD is L, the outputs of Ga and Gs are determined by the inverted output of the other gate, and Q=H, M-L are maintained. be done. When the input data DATA at the time of data acquisition is H1, the output of the gate G5 is H1, so Q=L, and the inverted output of the gate SD is H, so the inverted output of the gate G5 is H. When the clock CLK becomes H, the output of the gate G6 becomes the inverted output of the L1 gate SD, so the outputs of the gates Ga and Ga are determined by the inverted output of the other gate, and the above Q=L, Q=
H is retained. Data latch function is gate G4,05
has a cross-connection CC.

[Problem that the invention seeks to solve]

In such a latch circuit, when hold loops β and CC having a data launch function are irradiated with α rays and their H level changes to L level, the L level state is maintained and the latched data is inverted.

For example, in Fig. 5, when the output terminal of AND gate G3 is irradiated with alpha rays and the H level (Q=H) becomes L level, the gate G
The re-input of G2 becomes L, its non-inverted output is L11, the inverted output is H, and the output Q of Ant/G3 becomes L, which is held and the stored data is inverted. Similarly in Fig. 6, when Q=H and Q=L, α is applied to the output terminal of gate G a.
When ray irradiation occurs and Q=L, the output of gate G5 becomes HS.
The inverted output Q of O3 becomes high, the non-inverted output becomes H, and the stored data is inverted.

The present invention aims to improve these points and provide a latch circuit that is less likely to invert stored data even when irradiated with alpha rays.

[Means for solving problems]

The present invention provides a latch circuit that includes a hold loop that captures data that takes high and low levels, outputs the captured data, and returns high-level output data to the input side, and holds the output state by the loop. The low level output data is also inverted to high level data and returned to the input side.
It is characterized by the provision of a hold loop.

[Effect]

A latch circuit of the present invention is shown in FIGS. 1 and 2. 1st
The figure corresponds to FIG. 5, and FIG. 2 corresponds to FIG. 6, and the same parts are given the same reference numerals. As is clear from comparing the two, in the present invention, the output ζ on the opposite side is also G? or G
input to the data storage section via e, and hold loop 2
It gets worse. βa, lb are added second hold loops. In this way, even if the Q output is inverted due to α-ray irradiation, it will not be held (and the inversion of the latch data can be prevented).

In other words, if Q = H in Figure 1, then Q = L due to α ray irradiation, since the stone is covered (even if this part is also irradiated with α rays, the L output will be the same as the L output). Yes) Gate G8
Therefore, the inverted output of gate G5 becomes L, and therefore the inverted output of gate G4 becomes H1, the non-inverted output of H1 becomes L, and the original storage state is returned. Even if α rays are irradiated in the latched state of Q=L, there is no change in the state of Q=L, and the state of Q and Q is maintained at H.

The same is true for Figure 2, even if α rays are irradiated in the latched state of Q=H and Q=L, since Q has been set at this time, the inverted output of gate G8 is H1, so the inverted output of gate G5 However, the inverted output Q of the gate G4 is replaced by the non-inverted output of H1, and returns to the original storage state. When Q=L, there is no change in the state even if there is alpha ray irradiation.

〔Example〕

A part (principal part) of the embodiment is shown in FIGS. 3 and 4. Third
The figure corresponds to FIG. 1, and the gate GI is the transistor Q, ~
Q6 and gate G2 are composed of transistors Q8 to Q13. AND gate G3 is transistor Q3 and Q
It is constructed by connecting the collector of ll with wiring A,
Its output is taken out via emitter follower Q5. The input CLK of the transistor Q9 of the gate G2 is the gate SD
and the input O of transistor Glto
Is G7 a gate G? shows the inverted output of

FIG. 4 corresponds to FIG. 2, and gate G a is composed of transistors Q21 to Q27, and gate G5 is composed of transistors Q28 to Q34. The input OG6 of the transistor Q21 of the gate G4 is the inverted output of the gate G6, the input OG8 of the transistor Q2Q of the gate G5 is the inverted output of Ga, and the input O3 of the transistor Q30.
D is the inverted output of SD.

Gate SD, G? , G6. Although a specific example of Gll is not shown, it corresponds to gates Gl, G2, etc. Vr is the reference voltage applied to the base of the reference side transistor of each gate differential pair, and Vcs is the constant current source transistor Q4. Q12, Q
The voltages for determining the current value, Vcc and VEl, applied to the base of 24... are the positive voltages of the power supply.

This is the negative side voltage. In the circuit of FIG. 3, transistor Q3.
If the collector of Qll is irradiated with α rays, and in the circuit shown in Fig. 4, the collectors of transistors Q21 and Q22 are
In the presence of radiation, storage data inversion is observed, but this is avoided in the present invention.

(Effects of the Invention) As explained above, according to the present invention, output data is held in a hold loop, and the inverted output data is inverted by a gate and inputted to the hold loop, thus making the hold loop double. , it is possible to prevent the retained data from being reversed even if there is alpha ray irradiation, which is extremely effective.

[Brief explanation of drawings]

1 and 2 are symbol diagrams showing the latch circuit of the present invention, FIGS. 3 and 4 are circuit diagrams showing the main parts of the embodiment, and FIGS. 5 and 6 are symbol diagrams showing the conventional example. It is. In the drawing, CLK is a clock; 1. CC is a hold loop,
(la, lb are the second hold loops.

Claims (1)

[Claims] In a latch circuit that captures data that takes high and low levels, outputs the captured data, and returns high-level output data to the input side, and holds the output state by the loop, low-level output data The latch circuit is characterized in that it is provided with a second hold loop that inverts this to high level data and returns it to the input side.