JPS5933611A - Generating and detecting circuit of synchronizing signal - Google Patents

Abstract

PURPOSE:To reduce the effect of a code error and to obtain a synchronizing code with a simple constitution of both circuit and device, by generating the synchronizing code through a comparatively simple circuit and then detecting the code if the number of bits forming a synchronizing signal is large. CONSTITUTION:Pattern coincidence circuits 6 and 7 deliver a signal of one only when the coincidence is obtained with patterns of codes W1 and W2 respectively. The output of the circuit 6 is used to an input of one side of a shift register 8 having the stage number equal to the code length of W1, an OR circuit 10 and an AND circuit 11 respectively. The output of the register 8 is turned into the other input of the circuit 11 after passing through the circuit 10 and an inverter circuit 9. A counter circuit 12 is cleared when the output of the circuit 11 is equal to one, and the output of the circuit 10 is used to the clock of the circuit 12. The circuit 12 produces an output signal one when its count value exceeds four. At the same time, the output of an AND circuit 13 contains a signal showing a break of a synchronizing signal. Thus the detection is possible for a synchronizing code.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a synchronization signal generation/detection circuit, and particularly to a synchronization signal generation/detection circuit used in a digital signal magnetic recording/reproducing device 3 or the like.

[Background of the invention]

Like a digital videotape recorder (VTR),
Devices that record and playback POM-encoded television signals require interleaving processing to reduce the effects of burst errors caused by dropouts, and a series of "0" signals to facilitate carrier extraction during playback. Scrambling processing is being performed to prohibit and,
A synchronization code is inserted to indicate a break between these processes. The synchronization code used here often has a relatively long code length of several tens of bits, so that it is unlikely to occur in data. Therefore, there is a problem that the configurations of circuits and devices for generating and detecting the synchronization code become complicated.

Furthermore, if we try to provide redundancy to the synchronization code so that it can correctly detect the synchronization code even if a code error of about 1 bit occurs in one synchronization code, the number of synchronization code detection circuits and devices will increase dramatically. There is also the problem that the number of cases increases.

[Purpose of the invention]

An object of the present invention is to generate and detect the synchronization code using a relatively simple circuit when the number of bits (hereinafter referred to as code length) constituting the synchronization signal used in recording, reproducing, etc. of digital signals is long. The goal is to provide the means to do so.

[Summary of the invention]

In order to achieve the above object, the present invention has a structure of a synchronization code including a plurality of consecutive first pattern codes W1 and a second pattern code W2 different from the first pattern code.
A circuit is configured to generate and detect these.

Now, as a synchronization code, code length l! (bit) sign W1
n consecutive numbers and a code W2 of code length m (bits)
Code length r+1! Consider the sign of -1-m (bits). Here, the code W2 is used as a code indicating the end of the synchronization code. Therefore, among the synchronization codes, the one whose pattern matches the code W1 is l! There are n pieces with a period of (bits). Therefore, in detecting the synchronization code, it is sufficient to detect the pattern of code W, the pattern of code W2, and determine the period and number of patterns of Wl.

Therefore, in the present invention, the code length nI of the synchronization code!
+m (bits), it is possible to detect the synchronization code using l-bit W1 pattern matching judgment and m-bit W2 pattern matching judgment, which has a very small number of pits.
Compared to l+m bit pattern matching judgment, the circuit,
The configuration of the device becomes very simple.

Further, according to the present invention, detection of a synchronization code that allows a code error in one block of Wl among n consecutive codes W1 among synchronization codes can be realized with only slight changes in circuits and devices. do. For example, if there is a code error in the k-th code Wl, only the part of the k-th code W1 is W,
It is inconsistent with the pattern of Therefore, the number of patterns that match the pattern of code W1 is the number of patterns that match the pattern of code W1, excluding only the k-th pattern among the n patterns with a period of l. Therefore, the code W2
When the pattern of code W1 matches, if the number of matching patterns of code W1 is n - 1 or more in period l, it is detected as synchronization, then among the synchronization codes, n codes W1 A synchronization code can be constructed that tolerates a code error in one block of Wl in the part. Therefore, in this case, the detection circuit can be realized only by changing the number of times the pattern of code W1 matches from n to n-1.

[Embodiments of the invention]

The present invention will be explained below with reference to Examples.

For convenience of explanation, as an example of the configuration of the synchronization code, a code using 4 (n=4) consecutive first codes W1 (1110010), a code using the second code W2 (0001101),
In other words, the case is shown in which a synchronous code having a code length of 35 bits is used.

FIG. 1 shows an embodiment of a circuit for generating the synchronization code. In the same figure, block].

2 and 3 are flip-flop circuits, and 4 and 5 are exclusive OR circuits. Since it is obvious that the above-mentioned 35-bit synchronization code is generated from the output of the OR circuit 5 by the circuit having the configuration shown in the figure, a description of the operation will be omitted.

FIG. 2 shows an embodiment of the synchronization code detection circuit. FIG. 3 is a time chart for explaining the operation of the above embodiment. The pattern-number circuit 6 outputs a signal of 1 only when it matches the pattern of code W1, and the pattern-number circuit 7 outputs a signal of 1 only when it matches the pattern of code W2. The output of the pattern number circuit 6 becomes an input to one of the shift register circuits 8, one of the OR circuits 10, and one of the AND circuits 11, each having a number of stages equal to the code length of Wl. The output of the shift register circuit 8 becomes the other input of the AND circuit 11 after passing through the zero-pass circuit 10 and the inverter circuit 9.

When the output of the AND circuit 11 is 1, the counting circuit 12 is cleared, and the output of the OR circuit 10 becomes the clock of the counting circuit 12. The counting circuit 12 generates an output signal 1 when the count value is 4 or more.

Then, a signal indicating a break in the synchronization code is obtained at the output of the AND circuit 13, and the synchronization code is detected.

The synchronization detection circuit shown in FIG. 2 above can correctly detect the synchronization code even if a code error occurs in one of the plurality of codes W1 among the synchronization codes due to a slight circuit change. be able to be able to be able to be able to do so.

That is, only the counting circuit 12 shown above has a count value of 3.
Changed so that the output signal "1" is generated in the above cases,
All remaining circuits are the same.

FIG. 4 is a time chart diagram illustrating the operation when the circuit configuration of FIG. 2 is changed so that the counting circuit 12 can generate the output signal "1" when the count value is 3 or more as described above. be.

The output of the pattern matching circuit 6 is a signal with one less 1 because the patterns do not match in Wl with a code error, but the count value of the counting circuit 12 becomes 4, so that synchronization can be detected. That is, 1 of the continuous part of code W1
If a code error occurs in a block, it can be detected as a synchronous code.

In the embodiment, the code Wl is used for W2, but W2 may be any code other than W1.

〔Effect of the invention〕

As described above, the synchronous code according to the present invention has the advantage that even if the code length is long, it can be realized with a small number of circuits and devices.

Furthermore, the present invention allows for a synchronous code that is less susceptible to code errors and has a simple circuit and device configuration, resulting in extremely large effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a synchronization signal generation circuit according to the present invention, FIG. 2 is a block diagram of an embodiment of a synchronization signal detection circuit according to the present invention, and FIGS. FIG. 3 is a time chart diagram for explaining the operation of the embodiment of the synchronization signal detection circuit according to the present invention. 1.2.3...Clip-flop circuit, 4,5...
・Exclusive OR circuit, 6, 7...pattern--matching circuit,
8...Shift register, 12...Counting circuit.

Claims (1)

[Claims] 1. A synchronization code is generated by consecutively generating a plurality of first pattern codes and then adding a second pattern code different from the first pattern code. A synchronization signal generation circuit characterized by: 2. An input unit that receives a synchronization signal in which a plurality of consecutive first pattern codes are followed by a second pattern code different from the first pattern code; and and a circuit for determining the code of the second pattern and a circuit for determining at least the period and number of codes of the first pattern, and the synchronization code is detected by the output of the determining circuit. Characteristic synchronization code detection circuit. 3. In the detection circuit described in item 2, the circuit for determining the period and number of codes in the first pattern is configured to determine that the number is less than the number of consecutive codes in the first pattern. Features a synchronous signal detection circuit.