JPS62149074A - Biphase code demodulating device - Google Patents

Abstract

PURPOSE:To simplify the circuit without increasing number of digits of measurement when running at low speed and heighten ability to follow up abrupt change of tape speed by changing frequency of a clock in plural steps according to tape speed and demodulating at the same accuracy from low speed running to high speed running. CONSTITUTION:When tape speed is changed, the tape speed is detected by a tape speed N step detecting circuit 11 in preset N steps from low speed to high speed and inputted to a high frequency clock N step switching circuit 12. The circuit 12 generates N step high frequency clock f of frequency of N steps according to tape speed of N steps. Supposing that, for instance, change of tape speed of 1-110 times occurred, high frequency clocks of frequency of 1, 5, 10... times are generated corresponding to speed detection signals at each step when the circuit 11 became 1, 5, 10 times.... Accordingly, the range of tape follow-up of demodulating operation becomes narrow range of 1-5, 5-10, 10-15 times... in each step. In the case where tape speed makes abrupt change acceleratedly, width of steps of speed corresponding to the change is determined, and extraction of reproduction clocks is made nicely.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a biphase code demodulation device in a digital magnetic recording/reproducing device using a magnetic tape or the like as a recording medium.

2. Description of the Related Art In recent years, there has been remarkable progress in magnetic recording and reproducing devices using magnetic tape, which is a large-capacity, low-cost recording medium.

However, an essential problem with magnetic tape is the difficulty in high-speed access caused by the winding time. To solve this problem, a commonly used method is to record magnetic tape address signals, such as time codes, on specific trunks on the magnetic tape, so that they can be played back even when the magnetic tape is running at various speeds. death,
This is used as access control information.

For example, SMPTE time code in a VTR corresponds to this, and digital data such as time code is subjected to biphase code modulation (Bi-φ, also called FM modulation).

) is recorded. These recorded signals (d) need to be demodulated stably and reliably by following a wide range of tape speeds, ioo times or more, from low-speed tape running to high-speed running.

For this reason, many demodulation circuits for bi-phase encoded recording signals have been provided in the past (for example, Ogawa type "Video editing technology" (April 20, 1982), Kenrokukan Publishing, PP57
-60).

The main process of biphase code demodulation is to calculate the clock interval by measuring the fundamental period of the recorded signal using a high-frequency clock, and then compare the blue value of the previous clock interval with the next clock interval to calculate the clock component. This is a method of extracting and detecting the "1" component in the data (for example, Japanese Patent Application Laid-Open No. 56-1
06421).

Problems to be Solved by the Invention However, in the conventional configuration, a high frequency clock with a constant frequency regardless of the tape running speed is used to measure the clock interval from the fundamental period of the recorded signal. The higher the running speed of the reproducing clock, the narrower the reproduction clock interval, the worse the measurement accuracy, and the harder it is to obtain stable demodulation operation.

Conversely, if the frequency of the high-frequency clock is increased to improve measurement accuracy, the clock interval measurement value becomes sharper when the tape is running at low speed, and the number of bits must be increased to prevent overflow of counters, etc. When the scale becomes large or the tape speed changes rapidly due to acceleration, the previous clock period and the next clock period are significantly different, making it difficult to extract the reproduced clock synchronized with the biphase code modulated signal. However, there were problems such as the inability to perform normal demodulation.

In view of the above-mentioned problems, the present invention provides a biphase code demodulation device that follows the tape speed, maintains the same measurement accuracy at any speed, and at the same time requires a small circuit scale.

Means for Solving the Problem In order to achieve this object, the biphase code demodulator of the present invention includes tape speed setting means for detecting the tape speed by dividing it into N stages, and N stages corresponding to the output thereof. a high-frequency clock generating means for generating high-frequency clocks of various frequencies; first and second measuring means for extracting the clock from the reproduced signal; a clock period value holding means; a Z and percentage value setting means; It is composed of a comparison means, a reproduction clock generation means, and a "1" component detection means for detecting a "1" component from the reproduction signal.

Function: With this configuration, the frequency of the high-frequency clock for measuring the 0-tick interval is changed in N stages according to the tape speed, and measurement can be performed with the same number of digits (with the same precision) from low-speed running to high-speed running. The circuit can be simplified without increasing the number of digits for time measurement, and the ability to follow rapid changes in tape speed acceleration is improved.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a biphase code demodulation device in one embodiment 1y1 of the present invention.

In FIG. 1, 11 is a tape speed N stage detection circuit;
2 is a high frequency clock N-stage switching circuit, 13 is a first clock cycle measuring circuit, 14 is a clock cycle value holding circuit, 15 is a clock cycle % value setting circuit, 16 is a clock cycle ↓ 6 value setting circuit, 17 is a first comparison 18 is a second clock period measuring circuit, 19 is a second comparison circuit, 20 is a regeneration 0 check generation circuit, and 21 is a "1" calibration detection circuit.

The operation of the biphase code demodulation device configured as described above will be described below.

Figure 2 shows the timing of each part.

First, reproduced signal edge b that captures the edge of reproduced signal a
The clock width edge C, which is obtained by logically ORing and the reproduced clock i outputted from the reproduced clock generating circuit 20 and excluding the inverted edge in the "1" interval, is the first clock period consisting of an n-bit binary counter. It is input to the measurement circuit 13. In the first clock period measuring circuit 13, the high frequency clock N-stage switching circuit 12, while resetting the n-bit binary counter at the clock width edge C for each clock period,
The clock period is measured using the output high-frequency clock f. At this time, the n bit 2 immediately before the reset is performed.
The clock width meter fill value d by the decimal counter is
The clock cycle value holding circuit 14 made up of an n-bit flip-flop is set to 1iGX.

Next, the clock period value T□ of the clock width holding value e stored by the clock period value holding circuit 14 is set, and the respective set values are set in the first comparison circuit 17 and the second comparison circuit 19.
is input to one side. The clock width measurement value d by the first clock cycle measurement circuit 13 is input to the other input of the first comparison circuit 17, and a percentage value comparison output q that matches at the position of the previous clock cycle C is obtained.

The other input of the second comparator circuit 19 has n bits of 2
The measured value of the second clock cycle measuring circuit 18 consisting of a forward counter is input. Here, the second clock period measuring circuit 18 is reset by the M-value comparison output q and performs measurement using the N-stage high frequency clock L, so that the second comparison circuit 1
Like the 3J value comparison output, the coincidence output of 9 is output at a position further z after the previous clock cycle Ti, T T , 3/4. The initial value is set to "1", and each time the % value comparison output q and the % value comparison output 2 are input, the output state is inverted and the reproduced clock 1 is output.

The 1" detection circuit 21 detects the "1" component in the reproduced signal from the reproduced signal edge b and the reproduced black and ri i, and demodulates the demodulated data.
Output.

Here, when the tape speed changes, the tape speed N stage detection circuit 11 detects the tape speed in N stages set in advance from low speed to high speed, and inputs the detected tape speed to the high frequency clock N stage switching circuit 1S2.

The high-frequency clock N-stage switching circuit 12 is configured to generate N-stage high-frequency clock signals of N stages of frequency in accordance with N stages of tape speed. Here, if there is a tape speed change of 1 to 110 times, then the tape speed N stage detection circuit 1
If you increase 1, the tape speed will be 1x, 5x, 10x, etc.
When the speed detection signal is set to be generated at each stage, the high-frequency clock N-stage switching circuit 12 will be able to generate speed detection signals of 1x, 5x, 10x, etc.・Corresponding to the speed detection signal at each stage, 1x, 5x, 10x,
Generates a high frequency clock with a frequency of... Therefore, since the above-mentioned demodulation operation is performed using this high-frequency clock, the tape speed tracking range of the demodulation operation is 1 at each stage.
~5 times, 5 to 10 times, 10 to 15 times... Narrow a
It will be good if you surround yourself. Furthermore, if the width of each speed detection stage is the same, the clock cycle measurement value at each stage will be in the same range, and it is possible to reduce the number of digits of the counter, etc.

In addition, when the speed of the tape changes rapidly due to acceleration, such as rising or falling, by setting the width of the speed detection stage according to the change, the previous value can be changed immediately to the high frequency clock according to the speed. It is possible to successfully extract recovered clocks that have a large error between the clock cycle value held value and the next clock cycle measurement value.

Effects of the Invention The present invention includes speed detecting means for detecting tape speed in N stages, high frequency clock generating means for generating high frequency clocks with N stages of frequencies corresponding to the output thereof, and extracting clocks from reproduced signals. First and second measuring means as means, clock synchronization period value holding means, 34' and % value setting means, first and second
At each tape speed divided into N stages,
The clock cycle measurement value can be kept within the same range, the number of digits in the counter can be reduced, and the followability when the tape speed changes rapidly due to acceleration can be improved. Since the frequency is variable, it is possible to realize an excellent biphase code demodulation device that can respond to a wider range of changes in tape speed than before.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a bi-phase code demodulator according to an embodiment of the present invention, and FIG. 2 is a timing chart of each part of FIG. 1. 11... Tape speed N stage detection circuit, 12...
...High frequency clock N-stage switching circuit, 13...1st clock period meter! 1111 circuit, 14-... Clock frequency 1υ1 value holding circuit, 15... Clock period...
4-value setting circuit, 16...clock frequency jυ]! Value setting circuit, 17...First comparison circuit, 18...
...Second clock period measuring circuit, 19...Second comparison circuit, 20...Regenerated clock generation circuit, 2
1...." 1 "Detection circuit.

Claims (3)

[Claims] (1) tape speed detection means that detects the tape speed by dividing it into a plurality of stages; and high-frequency clock generation means that generates high-frequency clocks of different frequencies in response to the respective outputs of the tape speed detection means. , a first measuring means for measuring the clock period of the bi-phase code modulated signal by the count number of the high-frequency clock; and an output of the first measuring means is reset by the clock period of the bi-phase code modulated signal. clock period value holding means for holding the immediately previous output value; m times value setting means for setting values m and n times the clock period value held by the clock period value holding means; and n times the clock period value holding means. a value setting means, an output value of the m-fold value setting means and the first
a first comparing means for comparing the output value of the measuring means; a second measuring means for counting the number of high frequency clocks that is reset by the comparison match output of the first comparing means; and a second measuring means for counting the number of high frequency clocks; a second comparing means for comparing the output value of the setting means and the output value of the second measuring means; inputting the comparative coincidence outputs of the first comparing means and the second comparing means; and generating a bi-phase code. a clock generating means for generating a clock of the modulated signal; and a clock generating means for detecting a "1" component from the clock and the biphase code modulated signal, and outputting "0" and "1" data synchronized with the clock. 1. A biphase code demodulation device comprising: 1" component detection means. (2) The biphase code demodulator according to claim 1, wherein the tape speed detecting means detects the rotational speed of the reel motor by dividing it into a plurality of stages. (3) As m times value setting means and n times value setting means, 1/
3. A biphase code demodulation device according to claim 1 or 2, characterized in that a quadruple value setting means and a ½ value setting means are used.