[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPS59202642A - Manufacture of hybrid integrated circuit device - Google Patents

Manufacture of hybrid integrated circuit device

Info

Publication number
JPS59202642A
JPS59202642A JP7793683A JP7793683A JPS59202642A JP S59202642 A JPS59202642 A JP S59202642A JP 7793683 A JP7793683 A JP 7793683A JP 7793683 A JP7793683 A JP 7793683A JP S59202642 A JPS59202642 A JP S59202642A
Authority
JP
Japan
Prior art keywords
resin
chip
substrate
nitrogen gas
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7793683A
Other languages
Japanese (ja)
Other versions
JPH0367337B2 (en
Inventor
Koji Tanaka
幸二 田中
Chikashi Ito
史 伊藤
Toshio Sonobe
園部 俊夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NipponDenso Co Ltd filed Critical NipponDenso Co Ltd
Priority to JP7793683A priority Critical patent/JPS59202642A/en
Publication of JPS59202642A publication Critical patent/JPS59202642A/en
Publication of JPH0367337B2 publication Critical patent/JPH0367337B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To enable to prevent the heat fatigue of a soldered connection part by a method wherein a substrate connected with a chip parts by soldering is put in a heated state, the surface of the chip parts is coated with a resin for protection by dripping the resin from over the chip parts and the dripped resin is immediately made to harden. CONSTITUTION:In a condition that a substrate 1 has been retained at high temperatures by a heater 3 in a nitrogen gas atmosphere 6, a resin 5 is dripped in proper quantity from a nozzle 4 installed just above the central part of a chip 2 or over the chip 2 and, at the same time, a resin hardening is performed. Even a resin such as a silicone gel, etc., whose viscosity at the time before being hardened is very low, is made to harden while effusion of the substrate 1 is little. By this method, it is suppressed for the resin 5 to infiltrate in between the chip 2 and the substrate 1 and the push-up stress of the resin 5, which acts to the chip 2, is reduced, thereby enabling to significantly improve the breaking lifetime of the soldered part between the chip 2 and the substrate 1. On the other hand, degradation of the characteristics of the chip parts can be prevented, because nitrogen gas has been sealed in between.

Description

【発明の詳細な説明】 本発明は、フリップチップ等のチップ部品を搭載した混
成集積回路装置の製造方法に関し、特にチップ部品への
保護樹脂の被覆方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a hybrid integrated circuit device equipped with chip components such as flip chips, and more particularly to a method of coating chip components with a protective resin.

従来のフリップチップ素子搭載混成集積回路装置に於い
ては、アルミナ等の基板にフリップチップ素子を半田組
付した後、あるいはこの組付基板をケースに接着した後
に、保護用の樹脂を被覆していた。ところがこの構成の
もきでは、保護用の樹脂がチップと基板の間に侵入する
為、樹脂とチップ接続部の半田との間に熱ストレスが発
生し、半田が熱疲労することがあった。
In conventional hybrid integrated circuit devices equipped with flip-chip elements, a protective resin is coated after the flip-chip elements are soldered onto a substrate made of alumina or the like, or after the assembled substrate is glued to a case. Ta. However, with this configuration, the protective resin penetrates between the chip and the board, causing thermal stress to occur between the resin and the solder at the chip connection area, resulting in thermal fatigue of the solder.

本発明の目的は、上記の半田熱疲労を防ぐため、チップ
部品と基板との間には樹脂を侵入させない構造の形成方
法を提供することである。
An object of the present invention is to provide a method for forming a structure that does not allow resin to enter between a chip component and a substrate in order to prevent the above-mentioned solder heat fatigue.

以下、本発明の実施例について説明する。第1図は製造
装置の概要を示し、lはフリップチップ等のチップ部品
2が半田23により組付けられた配線基板であり、3は
窒素ガス雰囲気6中に設置された基板加熱用の加゛熱装
置、4は基板1上の組付部品の保護樹脂5を注入するノ
ズルである。尚、保護樹脂5は加熱硬化型の樹脂である
。これらによって基板1を窒素ガス雰囲気6で加熱装置
3により、高温に保った状態で、チップ2の中央部真上
又は上方に設置したノズル4から樹脂5をfI量滴下し
、同時に樹脂硬化を行なうものである。
Examples of the present invention will be described below. FIG. 1 shows an outline of the manufacturing equipment, in which 1 is a wiring board on which a chip component 2 such as a flip chip is assembled with solder 23, and 3 is a heating device for heating the board installed in a nitrogen gas atmosphere 6. The heating device 4 is a nozzle for injecting the protective resin 5 of the assembled parts on the board 1. Note that the protective resin 5 is a thermosetting resin. With these, while the substrate 1 is kept at a high temperature by the heating device 3 in a nitrogen gas atmosphere 6, an fI amount of resin 5 is dropped from the nozzle 4 installed directly above or above the center of the chip 2, and the resin is cured at the same time. It is something.

前記構成により樹脂5の被覆を行なうと、基板1を高温
状態にして加熱硬化型の樹脂を硬化さゼることにより、
シリコーンゲル等の硬化前の粘度の非常に低い樹脂でも
基板1の流れ出しが小さいうちに硬化させることができ
る。また窒素雰囲気中にて基板l上のチップ2の中央部
真上に樹脂5の注入ノスル4を設置し、これより樹脂を
適量滴下すると、樹脂はチップ2の面21部より面22
を伝わり、基板1上へ流れ出し、この時基板1の温度が
低い場合には樹脂5は流れ易いので基板1とチップ2の
間まで侵入してしまうか、基板温度が高い場合には、樹
脂の流れ出しが小さいうちに硬化さゼるので、基板1と
チップ2との間への樹脂5の侵入を微量に抑えられ、こ
の部分に窒素ガス6を閉し込めることができる。
When the resin 5 is coated with the above configuration, the substrate 1 is heated to a high temperature and the heat-curable resin is cured.
Even a resin having a very low viscosity before curing, such as silicone gel, can be cured while the flow of the substrate 1 is small. In addition, in a nitrogen atmosphere, an injection nozzle 4 for resin 5 is installed directly above the center of the chip 2 on the substrate l, and when an appropriate amount of resin is dropped from this, the resin flows from the surface 21 of the chip 2 to the surface 22.
At this time, if the temperature of the board 1 is low, the resin 5 will flow easily and will enter between the board 1 and the chip 2, or if the temperature of the board is high, the resin 5 will flow out onto the board 1. Since the resin 5 hardens while the outflow is small, the intrusion of the resin 5 into the space between the substrate 1 and the chip 2 can be suppressed to a very small amount, and the nitrogen gas 6 can be trapped in this area.

このような構成により、チップ2と基板1の間への樹脂
5の侵入を抑えられる。そこで、チップ2に働く樹脂5
の押し上げ応力は著しく低下し、チップ2と基板1の半
田付部の破断寿命を大幅に向上できる。一方、間に窒素
ガスを封入しであるため、チップ部品の特性低下を極力
防ぐことができる。
With this configuration, the resin 5 can be prevented from entering between the chip 2 and the substrate 1. Therefore, resin 5 working on chip 2
The pushing stress of the chip 2 and the substrate 1 is significantly reduced, and the life of the soldered portion between the chip 2 and the substrate 1 can be greatly improved. On the other hand, since nitrogen gas is sealed in between, deterioration of the characteristics of the chip components can be prevented as much as possible.

また、第3図に示すように、基板1に半田71で接着さ
れたコンデンサチップ7等の他のチップ部品に対しても
同様な効果がある。またチップ素子2の表面保護が十分
であれば、第4図に示すように、窒素雰囲気中に代えて
空気中に於いて樹脂5の被覆を行い、チップ2と基板1
との間に空気8を閉し込めた場合でも同じ効果かある。
Further, as shown in FIG. 3, similar effects can be obtained for other chip components such as the capacitor chip 7 bonded to the substrate 1 with solder 71. Further, if the surface protection of the chip element 2 is sufficient, as shown in FIG.
The same effect can be obtained even if air 8 is trapped between the two.

以上述べたように本発明では、チップ部品を半田接続し
た基板を、加熱した状態におき、チップ部品の上方より
保護用樹脂を滴下してこのチップ部品の表面に樹脂を被
覆しているから、滴下された樹脂は直ちに硬化されるた
め、この樹脂がチップ下部へ侵入することがほとんどな
く、従ってチップ部品と基板間に所望の空間を形成でき
、半田接続部分の熱疲労を防止できる構造が容易に得ら
れる。
As described above, in the present invention, the substrate to which the chip components are soldered is kept in a heated state, and the protective resin is dripped from above the chip components to coat the surface of the chip components with the resin. Since the resin that is dropped is cured immediately, there is almost no chance of this resin penetrating the bottom of the chip, making it possible to form the desired space between the chip components and the board, and easily create a structure that prevents thermal fatigue at the soldered joints. can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は本発明の一実施例を示す製造装置の
模式図及び混成集積回路装置の断面図、第3.4図は本
発明の他の応用例を示す混成集積回路装置の断面図であ
る。 1・・・配線基板、2・・・チップ部品、3・・・加熱
装置、4・・・ノズル、5・・・保護用樹脂、6川窒素
ガス雰囲気。 代理人弁理士 岡 部   隆
1 and 2 are a schematic diagram of a manufacturing apparatus and a sectional view of a hybrid integrated circuit device showing one embodiment of the present invention, and FIG. 3.4 is a schematic diagram of a hybrid integrated circuit device showing another application example of the present invention. FIG. DESCRIPTION OF SYMBOLS 1... Wiring board, 2... Chip parts, 3... Heating device, 4... Nozzle, 5... Protective resin, 6... Nitrogen gas atmosphere. Representative Patent Attorney Takashi Okabe

Claims (1)

【特許請求の範囲】[Claims] チップ部品を半田接続した基板を、保護用樹脂のほぼ硬
化温度まで加熱した状態におき、前記チップ部品の上方
より保護用樹脂を滴下して前記チップ部品の表面に樹脂
を被覆するようにした混成集積回路装置の製造方法。
A hybrid method in which a board to which a chip component is soldered is heated to approximately the curing temperature of the protective resin, and the protective resin is dropped from above the chip component to coat the surface of the chip component with the resin. A method of manufacturing an integrated circuit device.
JP7793683A 1983-05-02 1983-05-02 Manufacture of hybrid integrated circuit device Granted JPS59202642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7793683A JPS59202642A (en) 1983-05-02 1983-05-02 Manufacture of hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7793683A JPS59202642A (en) 1983-05-02 1983-05-02 Manufacture of hybrid integrated circuit device

Publications (2)

Publication Number Publication Date
JPS59202642A true JPS59202642A (en) 1984-11-16
JPH0367337B2 JPH0367337B2 (en) 1991-10-22

Family

ID=13647960

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7793683A Granted JPS59202642A (en) 1983-05-02 1983-05-02 Manufacture of hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS59202642A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177738A (en) * 1985-01-28 1986-08-09 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Mutual connection body
JPS62116542U (en) * 1986-01-17 1987-07-24
JPH01132129A (en) * 1987-11-18 1989-05-24 Sanyo Electric Co Ltd Manufacture of hybrid integrated circuit
EP0457453A2 (en) * 1990-05-18 1991-11-21 Dow Corning Corporation Method for transporting a cured organic or organosiloxane gel
US6376915B1 (en) 1999-02-26 2002-04-23 Rohm Co., Ltd Semiconductor device and semiconductor chip

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5232554A (en) * 1975-09-05 1977-03-11 Int Standard Electric Corp Ac generating electronic unit
JPS5831539A (en) * 1981-08-19 1983-02-24 Nec Corp Manufacture of hybrid integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5232554A (en) * 1975-09-05 1977-03-11 Int Standard Electric Corp Ac generating electronic unit
JPS5831539A (en) * 1981-08-19 1983-02-24 Nec Corp Manufacture of hybrid integrated circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61177738A (en) * 1985-01-28 1986-08-09 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Mutual connection body
JPH0222541B2 (en) * 1985-01-28 1990-05-18 Intaanashonaru Bijinesu Mashiinzu Corp
JPS62116542U (en) * 1986-01-17 1987-07-24
JPH01132129A (en) * 1987-11-18 1989-05-24 Sanyo Electric Co Ltd Manufacture of hybrid integrated circuit
EP0457453A2 (en) * 1990-05-18 1991-11-21 Dow Corning Corporation Method for transporting a cured organic or organosiloxane gel
US6376915B1 (en) 1999-02-26 2002-04-23 Rohm Co., Ltd Semiconductor device and semiconductor chip

Also Published As

Publication number Publication date
JPH0367337B2 (en) 1991-10-22

Similar Documents

Publication Publication Date Title
US6821878B2 (en) Area-array device assembly with pre-applied underfill layers on printed wiring board
KR101010159B1 (en) Flip-chip assembly with thin underfill and thick solder mask
KR100395444B1 (en) Method for mounting semiconductor element to circuit board, and semiconductor device
JPS6094744A (en) Hybrid ic device
JP3391282B2 (en) Electronic component manufacturing method
US5314842A (en) Resin-sealed type semiconductor device and method for manufacturing the same
JPS59202642A (en) Manufacture of hybrid integrated circuit device
KR100438991B1 (en) A process line for underfilling a controlled collapse chip connection (c4) integrated circuit package
JP4702370B2 (en) Circuit module manufacturing method
JP2005502187A (en) Prefilled underfill at package level to improve thermomechanical reliability of electronic component assemblies
JPH07288255A (en) Formation of solder bump
JP3835710B2 (en) Method for manufacturing composite semiconductor device
US5647529A (en) Method of controlling the temperature of a portion of an electronic part during solder reflow
JP2004014870A (en) Circuit module and its producing method
JP2008103450A (en) Method for manufacturing module
JP3260249B2 (en) Semiconductor device mounting method and its mounting body
JPS59143333A (en) Coating method of resin for protecting element
EP1286577B1 (en) Method of fixing electronic part
JPH1126641A (en) Semiconductor device and manufacture thereof
JP3086340B2 (en) Method of soldering electronic components with heat sink to printed circuit board
JPH06244224A (en) Part soldering method of semiconductor device
JPH11345918A (en) Method for mounting semiconductor device and mounted body
JPH03254134A (en) Resin seal of electric components
JP2862662B2 (en) Semiconductor sealing method
KR20070085145A (en) Apparatus and method for manufacturing semiconductor package capable of potting thermosetting resin while being heated