JPS59143333A - Coating method of resin for protecting element - Google Patents
Coating method of resin for protecting elementInfo
- Publication number
- JPS59143333A JPS59143333A JP1652783A JP1652783A JPS59143333A JP S59143333 A JPS59143333 A JP S59143333A JP 1652783 A JP1652783 A JP 1652783A JP 1652783 A JP1652783 A JP 1652783A JP S59143333 A JPS59143333 A JP S59143333A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- hole
- chip
- semiconductor element
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229920005989 resin Polymers 0.000 title claims abstract description 33
- 239000011347 resin Substances 0.000 title claims abstract description 33
- 238000000576 coating method Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims description 9
- 230000001681 protective effect Effects 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 abstract description 6
- 239000002904 solvent Substances 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000016 photochemical curing Methods 0.000 abstract 2
- 238000007664 blowing Methods 0.000 abstract 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、フリップチップ電極を用いる半導体素子へ
保護用樹脂を被覆する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of coating a semiconductor element using a flip-chip electrode with a protective resin.
混成集積回路装置において、フリップチップ電極により
ボンディングされた半導体素子を保護する手段として、
熱硬化性樹脂を直接半導体素子上（１）
に塗布する事が行なわれている。この場合、塗布された
樹脂は硬化前は軟らかい為、半導体素子の下にも侵入す
る。一般に、樹脂類は電極に使われているＰｕ−３ｎ系
半田に比べ熱膨張係数が約１桁大きく、３Ｘ１０−’〜
ｌＸｌ０−３／’Ｃである。この為、混成集積回路装置
が高温（通常１５０℃以内）環境下に置かれた時、半導
体素子の下部に侵入した樹脂がフリップチップ電極の半
田のそれ以上に膨張する為、素子を回路基板の上方向に
押し上げる力が作用する。そのため、温度サイクル等に
対して、フリップチップ電極３の半田が熱疲労を起しや
すい。In a hybrid integrated circuit device, as a means to protect semiconductor elements bonded by flip-chip electrodes,
Thermosetting resin is applied directly onto semiconductor elements (1). In this case, since the applied resin is soft before hardening, it also penetrates under the semiconductor element. In general, resins have a coefficient of thermal expansion that is about one order of magnitude larger than that of Pu-3n solder used for electrodes, and has a thermal expansion coefficient of 3X10-'~
lXl0-3/'C. For this reason, when a hybrid integrated circuit device is placed in a high temperature environment (usually within 150°C), the resin that has entered the bottom of the semiconductor element expands more than the solder of the flip chip electrode, causing the element to be placed on the circuit board. A force pushing upwards acts. Therefore, the solder of the flip chip electrode 3 is likely to suffer thermal fatigue due to temperature cycles and the like.
この発明の目的は、上記した欠点のない新規な半導体素
子の表面保護を行なう素子保護用樹脂の被覆方法を提供
することにある。An object of the present invention is to provide a novel method for coating a semiconductor element with a resin for protecting the surface thereof, which does not have the above-mentioned drawbacks.
即ち、本発明の素子保護用樹脂の被覆方法は、回路基板
上にフリップチップ電極を有する半導体素子が接続され
、この半導体素子上に保護用樹脂を被覆する方法であっ
て、前記回路基板の一部に予め穴を開け、この穴を塞ぐ
ようにして前記半導（２）
体素子を前記回路基板上に固定し、光硬化性樹脂を前記
半導体素子に被覆すると共に前記回路基板に対して光を
照射し、その後、前記回路基板の前記穴を通して前記半
導体素子の裏面にある前記樹脂の一部を取り除くことを
特徴とする。That is, the method for coating a device with a protective resin of the present invention is a method in which a semiconductor device having a flip-chip electrode is connected to a circuit board, and a protective resin is coated on the semiconductor device. The semiconductor element (2) is fixed on the circuit board by making a hole in advance and covering the hole, coating the semiconductor element with a photocurable resin and applying light to the circuit board. The method is characterized in that a portion of the resin on the back surface of the semiconductor element is removed through the hole of the circuit board.
以下、図に示す実施例について説明する。The embodiment shown in the figures will be described below.
まず、第１図のように、予め半導体素子組付は位置に穴
ＩＡのあいた混成集積回路装置用の回路基板１上の所定
導体パターン部分に、フリップチップ電極３を有する半
導体素子２を搭載し、この回路基板１を熱板又は電気炉
等により加熱して各電極部分を半田接続する。その際、
基板１の穴ＩＡは、フリップチップ電極３を厚生する各
バンプの端部より一定距離（例えば０．１ｉｎ）以上離
し、また穴径は、樹脂塗布後、溶剤により穴ＩＡを通し
て半導体素子２の下部が洗える程度（通常直径Ｑ、５ｍ
ｍ以上）にする必要がある。First, as shown in FIG. 1, the semiconductor element 2 is assembled in advance by mounting the semiconductor element 2 having the flip-chip electrode 3 on a predetermined conductor pattern portion on a circuit board 1 for a hybrid integrated circuit device having a hole IA at the position. The circuit board 1 is heated using a hot plate, an electric furnace, etc., and each electrode portion is connected by soldering. that time,
The hole IA of the substrate 1 is spaced at least a certain distance (for example, 0.1 inch) from the end of each bump that supports the flip-chip electrode 3, and the hole diameter is such that after resin is applied, a solvent is used to pass the hole IA through the hole IA to the bottom of the semiconductor element 2. (usually diameter Q, 5m)
m or more).
次に、第２図のように半導体素子２を外部環境により保
護する為に、紫外線等の光により硬化する光硬化性樹脂
４を半導体素子表面に滴下法又は（３）
浸漬法等により塗布する。その後、回路基板１の上方よ
り紫外線ランプによる光照射５を行ない樹脂４を硬化す
る。この場合、塗布膜厚は１１１前後であり、例えばラ
ンプ出力１６０Ｗ／ａｍのもので約１０秒程度の硬化時
間で済む。そして、半導体素子２の下部に侵入した樹脂
４Ａは、素子４の遮蔽硬化により光が照射されない為、
未硬化の軟らかい状態になっている。Next, as shown in FIG. 2, in order to protect the semiconductor element 2 from the external environment, a photocurable resin 4 that is cured by light such as ultraviolet rays is applied to the surface of the semiconductor element by a dropping method or (3) dipping method. . Thereafter, light irradiation 5 is performed from above the circuit board 1 using an ultraviolet lamp to harden the resin 4. In this case, the coating film thickness is around 111 mm, and for example, with a lamp output of 160 W/am, the curing time is about 10 seconds. The resin 4A that has entered the lower part of the semiconductor element 2 is not irradiated with light due to the shielding and hardening of the element 4.
It is in a soft, uncured state.
そこで次に、保護用樹脂４で覆われた回路基板１の全体
を溶剤中に浸すか、又は回路基板１の穴ＩＡに対応した
内径を持つノズルにより素子裏面に溶剤を吹き付けるか
して、未硬化骨の樹脂４Ａを半導体素子２の下部より取
り除いてしまう。その後、乾燥炉等において溶剤を除去
する。これにより第３図のように半導体素子下部の樹脂
が除かれ、そのためフリップチップ電極３に熱ストレス
のかからない混成集積回路装置になる。Next, the entire circuit board 1 covered with the protective resin 4 is immersed in a solvent, or the solvent is sprayed onto the back side of the element using a nozzle with an inner diameter corresponding to the hole IA of the circuit board 1. The hardened bone resin 4A is removed from the lower part of the semiconductor element 2. Thereafter, the solvent is removed in a drying oven or the like. As a result, the resin under the semiconductor element is removed as shown in FIG. 3, resulting in a hybrid integrated circuit device in which no thermal stress is applied to the flip chip electrode 3.
なお、上記実施例では樹脂被覆後に光照射を行っている
が、光強度によっては樹脂被覆処理と同時に光照射を行
なうようにしてもよい。また、樹（４）
脂被覆後には光強度を強くするなどの如く光強度を可変
させてもよい。In the above embodiment, light irradiation is performed after resin coating, but depending on the light intensity, light irradiation may be performed simultaneously with resin coating. Further, the light intensity may be varied by increasing the light intensity after coating with the resin (4).
また、第３図の如く形成された回路装置は、さらに他の
部品に実装される前に、穴ＩＡの部分を樹脂等の公知の
手段により密封し、湿気等が半導体素子２の裏面に触れ
ないように保護しておくのが好しい。Furthermore, before the circuit device formed as shown in FIG. It is best to protect it from
以上述べた如く本発明方法によれば、フリップチップ電
極を有する半導体素子の下部より保護用樹脂を良好に取
り除くことができ、フリップチップ電極部分の半田の熱
疲労を解消できるようになる。As described above, according to the method of the present invention, the protective resin can be effectively removed from the lower part of a semiconductor element having a flip-chip electrode, and thermal fatigue of the solder in the flip-chip electrode portion can be eliminated.
第１図乃至第３図は本発明方法を説明するための図であ
る。
１・・・回路基板、ＩＡ・・・穴、２・・・半導体素子
、３・・・フリップチップ電極、４・・・光硬化性樹脂
。
代理人弁理士 岡 部 隆
（５）
第１図
第２図
第３図1 to 3 are diagrams for explaining the method of the present invention. DESCRIPTION OF SYMBOLS 1... Circuit board, IA... Hole, 2... Semiconductor element, 3... Flip chip electrode, 4... Photocurable resin. Representative Patent Attorney Takashi Okabe (5) Figure 1 Figure 2 Figure 3
Claims (1)
接続され、この半導体素子上に保護用樹脂を被覆する方
法であって、前記回路基板の一部に予め穴を開け、この
穴を塞ぐようにして前記半導体素子を前記回路基板上に
固定し、光硬化性樹脂を前記半導体素子に被覆すると共
に前記回路基板に対して光を照射し、その後、前記回路
基板の前記穴を通して前記半導体素子の裏面にある前記
樹脂の一部を取り除くことを特徴とする素子保護用樹脂
の被覆方法。A method in which a semiconductor element having flip-chip electrodes on a circuit board is connected and a protective resin is coated on the semiconductor element, the method comprising making a hole in a part of the circuit board in advance and plugging the hole. The semiconductor element is fixed on the circuit board, the semiconductor element is coated with a photocurable resin, and the circuit board is irradiated with light, and then the back surface of the semiconductor element is coated through the hole of the circuit board. A method for coating a device with a resin for protecting an element, the method comprising removing a portion of the resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1652783A JPS59143333A (en) | 1983-02-03 | 1983-02-03 | Coating method of resin for protecting element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1652783A JPS59143333A (en) | 1983-02-03 | 1983-02-03 | Coating method of resin for protecting element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59143333A true JPS59143333A (en) | 1984-08-16 |
Family
ID=11918739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1652783A Pending JPS59143333A (en) | 1983-02-03 | 1983-02-03 | Coating method of resin for protecting element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59143333A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5164328A (en) * | 1990-06-25 | 1992-11-17 | Motorola, Inc. | Method of bump bonding and sealing an accelerometer chip onto an integrated circuit chip |
| US5385869A (en) * | 1993-07-22 | 1995-01-31 | Motorola, Inc. | Semiconductor chip bonded to a substrate and method of making |
| US5710071A (en) * | 1995-12-04 | 1998-01-20 | Motorola, Inc. | Process for underfilling a flip-chip semiconductor device |
| USRE43404E1 (en) | 1996-03-07 | 2012-05-22 | Tessera, Inc. | Methods for providing void-free layer for semiconductor assemblies |
-
1983
- 1983-02-03 JP JP1652783A patent/JPS59143333A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5164328A (en) * | 1990-06-25 | 1992-11-17 | Motorola, Inc. | Method of bump bonding and sealing an accelerometer chip onto an integrated circuit chip |
| US5385869A (en) * | 1993-07-22 | 1995-01-31 | Motorola, Inc. | Semiconductor chip bonded to a substrate and method of making |
| US5710071A (en) * | 1995-12-04 | 1998-01-20 | Motorola, Inc. | Process for underfilling a flip-chip semiconductor device |
| USRE43404E1 (en) | 1996-03-07 | 2012-05-22 | Tessera, Inc. | Methods for providing void-free layer for semiconductor assemblies |
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