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JPS5810884A - Manufacture of semiconductor laser having embedded heterogeneous structure - Google Patents

Manufacture of semiconductor laser having embedded heterogeneous structure

Info

Publication number
JPS5810884A
JPS5810884A JP10968881A JP10968881A JPS5810884A JP S5810884 A JPS5810884 A JP S5810884A JP 10968881 A JP10968881 A JP 10968881A JP 10968881 A JP10968881 A JP 10968881A JP S5810884 A JPS5810884 A JP S5810884A
Authority
JP
Japan
Prior art keywords
layer
active layer
inp
laminated
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10968881A
Other languages
Japanese (ja)
Other versions
JPS6248919B2 (en
Inventor
Mitsuhiro Kitamura
北村 光弘
Ikuo Mito
郁夫 水戸
Isao Kobayashi
功郎 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10968881A priority Critical patent/JPS5810884A/en
Publication of JPS5810884A publication Critical patent/JPS5810884A/en
Publication of JPS6248919B2 publication Critical patent/JPS6248919B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2054Methods of obtaining the confinement
    • H01S5/2059Methods of obtaining the confinement by means of particular conductivity zones, e.g. obtained by particle bombardment or diffusion
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/2054Methods of obtaining the confinement
    • H01S5/2081Methods of obtaining the confinement using special etching techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • H01S5/2275Buried mesa structure ; Striped active layer mesa created by etching

Landscapes

  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To manufacture InGaAsPBHLD characterized by the small leaking current and therefore the excellent temperature characteristics by obtaining a current block layer for preventing a leaking current with excellent reproducibility. CONSTITUTION:A semiconductor layer including at least an active layer 303 is laminated on an N type InP substrate 1. On the surface of a wafer having the multilayered film structure described above, a stripe shaped diffused protecting mask 305 is formed. Then, P type impurities are selectively diffused to the part deeper than the active layer 303. A part of the entire part of said P type impurity region 306 is chemically etched selectively to the surface of the active layer, and a mesa stripe 307 is formed. The active layer 303 at the part other than said mesa stripe is melted back. Then only the upper surface of the mesa stripe 307 is removed, the N type current block layer 309 is laminated, a P type embedded layer 310 is laminated, an N-InGaAsP cap layer 311 is laminated, and the growing is finished.

Description

【発明の詳細な説明】 本発明は埋め込みへテロ構造半導体レーザ特にInP 
t−基板とするInGaAsP[1め込みへテロ構造半
導体レーザの製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a buried heterostructure semiconductor laser, particularly an InP
The present invention relates to a method of manufacturing an InGaAsP [1-embedded heterostructure semiconductor laser using a t-substrate.

埋め込みへテロ構造半導体レーザ(以下BH−LDと略
す。)は低い発振しきい値電流、安定化された発振横モ
ード、高温動作可能などの優れ九特性を有するため光フ
アイバ通信用光源として注目を集めている0例えば平地
等p1979年12月発行の電子材料誌第18巻第12
号の58ページから61ページで報告しているように@
1図に示す形状のI nGaAs P BH−L D 
f製作シテイル。
Buried heterostructure semiconductor lasers (hereinafter abbreviated as BH-LD) are attracting attention as light sources for optical fiber communications because they have excellent characteristics such as low oscillation threshold current, stabilized oscillation transverse mode, and high-temperature operation. Collected 0 For example, flat land, etc.P Electronic Materials Magazine Vol. 18 No. 12 published December 1979
As reported on pages 58 to 61 of the issue @
InGaAs P BH-LD with the shape shown in Figure 1
F production details.

ところでAjGa人3系のレーザに比べてInGaAs
P系のレーザでは一般に発振しきい値電流の温度依存性
が大きく、わずかな温度上昇に対して発振しきい値電流
が大きく上昇してしまうという欠点がある。特にInG
aム5PBH−LDでは活性層周辺のInPOp−n接
合を介して流れるもれ電流が増加するために5第1図に
おいてp形InP[itブロック層106が無い場合に
は発振しきい値電流は温度の上昇とともにさらに大きく
上昇する。したがってもれ電at防止するために第1図
において電流とじこめ層107とn形りラッド層102
との間に、活性層側面につながるp形InP層ios 
e設け、メサ側面部t pnpn構造とすることが必要
である。
By the way, compared to AjGa3 type laser, InGaAs
P-based lasers generally have a drawback in that the oscillation threshold current has a large temperature dependence, and the oscillation threshold current increases significantly even with a slight temperature rise. Especially InG
In a PBH-LD, the leakage current flowing through the InPO p-n junction around the active layer increases. It increases further as the temperature rises. Therefore, in order to prevent electrical leakage, the current confinement layer 107 and the n-type rad layer 102 are shown in FIG.
There is a p-type InP layer connected to the side surface of the active layer between
It is necessary to provide a mesa side surface and a pnpn structure.

ところで第1図に示すBHLD  の製造過程において
、p形InP電流ブo、り層106’QInGaAsP
活性層103の側面につなげて形成するためには。
By the way, in the manufacturing process of the BHLD shown in FIG.
In order to form the active layer 103 so as to be connected to the side surface of the active layer 103.

逆メサ形状に工、チングする場合のエツチング深さ、お
よびp形InP電流ブロック層106の成長膜厚を精度
良く制御する必要があるが、′現在用いられている液相
エピタキシャル成長法、およびBrメタノール系エツチ
ング液などを用いたメサエッチングの手法では必ずしも
十分な制御性があるとは言えず、電流ブロック層106
の位置は活性層側面の所望の位置に再現性よく形成され
にくい、したがって第1図に示すInGaAsP BH
−LDの製作歩留9が悪いという結果を招いている。さ
らにこの例においては2回目のエピタキシャル成長時に
メサ側面112が高温度雰囲気中に長時間さらされるた
め、いわゆる熱ダメージ等により。
It is necessary to precisely control the etching depth when etching and etching into an inverted mesa shape and the growth thickness of the p-type InP current blocking layer 106, but it is necessary to precisely control the etching depth and the growth thickness of the p-type InP current blocking layer 106. It cannot be said that the mesa etching method using a mesa etching solution etc. has sufficient controllability, and the current blocking layer 106
It is difficult to form the InGaAsP BH at the desired position on the side surface of the active layer with good reproducibility.
-This results in a poor manufacturing yield of LD. Furthermore, in this example, during the second epitaxial growth, the mesa side surface 112 is exposed to a high temperature atmosphere for a long time, resulting in so-called thermal damage.

活性層103の幅が小さくなると発振しきい値電流密度
が上昇してしまうという欠点がtt)シ、信頼性も十分
とは言えない0例えば50℃、5mWの定出力寿命試験
においては通常の平らな活性層をもつInGaAsP 
LDと比べて約1け友劣化率が大きい。
The drawback is that the oscillation threshold current density increases as the width of the active layer 103 becomes smaller, and the reliability is not sufficient.For example, in a constant output life test of 5mW at 50°C InGaAsP with active layer
Compared to LD, the deterioration rate is about 1 order of magnitude higher.

本発明の目的は上記の欠点を除くべく、もれ電流が少な
く、シたがって温度特性のすぐれた、信頼性の高いIn
GaAsP BHLD′gr再現性よく製造する方法を
提供することにある。
The object of the present invention is to eliminate the above-mentioned drawbacks by producing a highly reliable Indium alloy with low leakage current and excellent temperature characteristics.
The object of the present invention is to provide a method for producing GaAsP BHLD'gr with good reproducibility.

本発明によれば1置方位が(100)、Toるいは(1
00)  近傍であるn形InP基板に少くともI n
 1−x G a x A s 1 ++ y P y
 (0< x < 1 e O<Y <1 )活性層管
含む半導体層を積層させた多層膜構造ウェファの表面に
<011>方向に沿ったストライプ状の拡散保鏝マスク
を形成゛した後、p形不純物を前記I n 1−x G
 a x A m 1 ++ y P y  活性層よ
りも深く選択拡散する工程と1選択拡散されたp形不純
物領域の一部1+は全部を前記I n 1− X G 
a XA l 1−YP、活性層表面まで選択化学エツ
チングして<011>方向に平行なメサストライプを形
成する工程と、前記メサストライプ以外の部分の前記I
n1−1G a xA s 1−アPy活性層をメルト
バックさせた後前記メサストライプの上面のみを除いて
n形I n 1−x/Gax’ A@1 、/ P、/
 (O<X’<X、)’< 3”<1 )電流プロ、り
層を積層させ、さらにp形In、、、、、x*Ga x
g As 1−y# P、#埋め込み層を全面にわたっ
て連続して積層させるエピタキシャル成長工程とを含む
ことを特徴とする埋め込みへテロ構造半導体レーザの製
造方法が得られる。
According to the present invention, the 1-position orientation is (100), To or (1
00) At least I n in the nearby n-type InP substrate
1-x G a x A s 1 ++ y P y
(0 < x < 1 e O < Y < 1) After forming a stripe-shaped diffusion protection mask along the <011> direction on the surface of a multilayer structure wafer in which semiconductor layers including active layer tubes are laminated, The p-type impurity is
a x A m 1 ++ y P y A step of selectively diffusing deeper than the active layer and a part 1+ of the selectively diffused p-type impurity region is entirely transferred to the above In 1-
a XA l 1-YP, selective chemical etching up to the surface of the active layer to form mesa stripes parallel to the <011>direction;
After melting back the n1-1G a xA s 1-A Py active layer, the n-type I n 1-x/Gax' A@1 , /P, / is formed except for only the upper surface of the mesa stripe.
(O <X'<
gAs 1-y#P,# A method for manufacturing a buried heterostructure semiconductor laser is obtained, which includes an epitaxial growth step of continuously laminating a buried layer over the entire surface.

実施例を説明する前にメルトバック法によって埋め込み
活性層を形成する方法について簡単に説明する9通常の
DH−LDウェファを作製する際にもエピタキシャル成
長前に導入されるInP基板表面の熱ダメージ層などを
除去して良好なエピタキシャル成長層を成長させるため
にInメルトまたはInP未飽和溶液を用いてエピタキ
シャル成長開始直前に基板表面をメルトバックする方法
がとられている。これは接触させる溶液が未飽和である
とき表面のInPが溶液中に溶けだすことを利用して表
面ダメージ層を基板表面からと9除き。
Before explaining the examples, we will briefly explain the method of forming a buried active layer using the melt-back method. In order to remove this and grow a good epitaxial growth layer, a method is used in which the substrate surface is melted back using an In melt or an unsaturated InP solution just before the start of epitaxial growth. This removes the surface damage layer from the substrate surface by utilizing the fact that when the solution to be contacted is unsaturated, InP on the surface begins to dissolve into the solution.

いわゆる熱ダメーレのないきれいな表面を出しているの
である。ところでこのようなメルトバックの効果はIn
PよシもInGaAsPのほうが大きく。
This results in a clean surface with no heat damage. By the way, the effect of such meltback is In
InGaAsP also has a larger P value.

より長波長の組成のInGaAsP層はどメルトバック
されやすいという性質がある。そこで第2図(a)に示
すようにInGaAsP  活性層202の上に一部分
だけInPメサストライプを残しておくと。
An InGaAsP layer having a composition with a longer wavelength has a property of being easily melted back. Therefore, as shown in FIG. 2(a), only a portion of the InP mesa stripe is left on the InGaAsP active layer 202.

InP未飽和溶液でメルトバックの条件を選んでやるこ
とにより、第2図(b)のようにInPメサスドライブ
203以外の部分のInGaAsP  活性層202t
−メルトバックさせて、いわゆる表面の熱ダメージ層を
とり除くことができる。このようなことは例えに過飽和
度△T=−10℃、(未飽和)に選んだInP未飽和溶
液を用いて620℃で30秒間メルトバックすることに
よって第2図(b)に示したようにInGaAsP活性
層202iInPメサストライプ203部分のみに残す
ことが可能となる。なおこの際InPメサストライプ2
03屯わずかにメルトバックされるためInPメサスト
ライプ203の角が少し丸まる傾向にある。第1図の例
の場合のように活性層102側面を高温度雰囲気中にさ
らすことがないため、埋め込み活性層が熱ダメージを受
けに<<、シたがって活性層幅が小さく表りでも発振し
きい値電流密度が大きく上昇することなく高い信頼性の
埋め込みへテロ構造半導体レーザを再現性よ、く製作す
ることが可能となる。
By selecting meltback conditions using an InP unsaturated solution, the InGaAsP active layer 202t in the area other than the InP mesus drive 203 is removed as shown in FIG. 2(b).
- The so-called heat-damaged layer on the surface can be removed by melting back. This can be achieved by melting back at 620°C for 30 seconds using an unsaturated InP solution with a supersaturation degree △T = -10°C (unsaturated), as shown in Figure 2 (b). It becomes possible to leave the InGaAsP active layer 202i only in the InP mesa stripe 203 portion. In this case, InP mesa stripe 2
Since the InP mesa stripe 203 is slightly melted back, the corners of the InP mesa stripe 203 tend to be slightly rounded. Since the side surface of the active layer 102 is not exposed to a high-temperature atmosphere as in the case of the example shown in FIG. 1, the buried active layer is not subject to thermal damage. It becomes possible to manufacture a highly reliable buried heterostructure semiconductor laser with good reproducibility without significantly increasing the threshold current density.

II3図は本発明の実施例の製造方法を示すための断面
図tあられす、tず第3図(1)においてn−InP基
板301上ニn−InPバッファ層302(Te ドー
プ、厚さ5μm)、ノンドープI n s、ye Ga
 、、。
FIG. 23 is a cross-sectional view showing the manufacturing method of the embodiment of the present invention. In FIG. 3(1), an n-InP buffer layer 302 (Te doped, 5 μm thick ), non-doped I n s, ye Ga
,,.

Aso、5spe、as活性層303(波長1.3μm
組成、厚す0.15 μm ) 、 p−InPクラッ
ド層304(Zn  ドープ、厚さ0.6μm)l順次
積層させた通常の1nGaAsP−InP DHウェフ
ァにp形不純物の選択拡散保護マスクとしてSin、C
VD膜を約0.3μm稚積する。通常のフォトリングラ
フィの手法によ九<011>方向にそって幅4μmのフ
ォトレジスト・ストライプ全形成してこれをマスクとし
てフッ酸を用いてエツチングし1選択拡散保護マスク3
05を残す1次にp形不純物としてZn f深さ約1つ
2μmまで拡散してp形不純物拡散層 306を形成す
る。このとき図に示すように選択拡散保護マスク305
の下部には幅2〜3μmの拡散されない層が残ることに
なる1次に第3図(2)において選択拡散保護マスク3
05t−こんどはエツチングマスクとして用い、InP
の選択エツチング液である塩酸:純水=4:1の混合工
、チンダ液を用いてp−InPクラッド層304のみエ
ツチングする。その後選択拡散保護マスク305を塩9
去って高さ1μmのp−InPメサ307?形成する。
Aso, 5spe, as active layer 303 (wavelength 1.3 μm
Composition, thickness: 0.15 μm), p-InP cladding layer 304 (Zn doped, thickness: 0.6 μm) was sequentially stacked on an ordinary 1nGaAsP-InP DH wafer, and a p-type impurity selective diffusion protective mask of Sin, C
A VD film is deposited to a thickness of about 0.3 μm. A photoresist stripe with a width of 4 μm is completely formed along the <011> direction using the usual photolithography method, and this is used as a mask for etching using hydrofluoric acid. 1 Selective diffusion protection mask 3
A p-type impurity diffusion layer 306 is formed by diffusing Zn f as a primary p-type impurity except for Zn to a depth of about 1 2 μm. At this time, as shown in the figure, a selective diffusion protection mask 305
In FIG. 3 (2), a selective diffusion protection mask 3 is applied, leaving behind an undiffused layer with a width of 2 to 3 μm under the mask.
05t-This time it is used as an etching mask, and InP
Only the p-InP cladding layer 304 is etched using a selected etching solution, which is a 4:1 mixture of hydrochloric acid and pure water. Then select diffusion protection mask 305 with salt 9
A p-InP mesa 307 with a height of 1 μm? Form.

この段階で図に示すようにメサ部分以外ではn−InP
バッファ層302中に層形02中拡散層306#1形成
されている。第3図(3)において埋め込み成長を行な
う、溶液の過飽和度をΔ’l’=−10℃にとったIn
P未飽和溶液を用いてメサストライプ以外の部分(’ 
IJ、7@ ”@J@A”@48 ps、ss活性層3
03tメルトバックしてBH−LDの埋め込まれた:[
fl*、teoae、ioλm@j&PLH活性層30
g ?形成した後n−InP電流ブロック層309 (
’I’eドープ。
At this stage, as shown in the figure, n-InP is
A layer type 02 medium diffusion layer 306 #1 is formed in the buffer layer 302 . In Fig. 3 (3), the supersaturation degree of the solution was set to Δ'l' = -10°C for buried growth.
Areas other than mesa stripes ('
IJ, 7@”@J@A”@48 ps, ss active layer 3
03t meltback and BH-LD embedded: [
fl*, teoae, ioλm@j&PLH active layer 30
G? After forming the n-InP current blocking layer 309 (
'I'e dope.

平担部厚さ0.4μm)′t−メサストライプの上面以
外に成長させる。これは筆者らが特願昭55−1232
61において詳しく述べているように狭いメサストライ
プ上面のみを除いてInPMit積層させるものであり
、BH−LD のもれ電流の防止に特に都合がよい、そ
の後p−1nP埋め込み層310(Zflドープ、平担
部厚さ1.5μm)を全面に連続して積層り、n−In
GaAsPキャップ層311 (Teドープ厚さ0.5
μm)を積層させて成長を終える。埋め込み成長に際し
電流ブロック層となるp−InP不純物拡散層306と
n−InP電流ブロック層309のp −n接合はIn
640G為@、80k” @、n P@、u活性層30
8の真横に形成されており、 InGaAsP BH−
LDのもれ電流の防止に特に有効である。最後に第3図
(4)に示すように得られた多層膜ウェファを通常の方
法により8μmの幅でp−InP埋め込み層31Gに達
する深さで選択Zn拡散層312を形成した後p側にA
uZnオーミック電極313゜n側にAu−Ge−Ni
オーミック電極314 t−形成しく110)  面が
ファブリ・ペロー共振器面となるようニヘき開してIn
GaAsP BH−LD を作製する。
(Thickness of flat part: 0.4 μm)' Grown on areas other than the upper surface of the t-mesa stripe. This is a patent application filed by the authors in 1232-1982.
As described in detail in 61, InPMit is layered except for the upper surface of the narrow mesa stripe, which is particularly convenient for preventing leakage current of BH-LD. N-In
GaAsP cap layer 311 (Te doped thickness 0.5
µm) to finish the growth. The p-n junction between the p-InP impurity diffusion layer 306 and the n-InP current blocking layer 309, which will become the current blocking layer during buried growth, is made of InP.
640G @, 80k” @, n P@, u active layer 30
It is formed right next to 8, and InGaAsP BH-
This is particularly effective in preventing LD leakage current. Finally, as shown in FIG. 3(4), a selective Zn diffusion layer 312 with a width of 8 μm and a depth reaching the p-InP buried layer 31G is formed on the obtained multilayer film wafer by the usual method, and then a selective Zn diffusion layer 312 is formed on the p-side. A
Au-Ge-Ni on the n side of the uZn ohmic electrode 313゜
Ohmic electrode 314 T-formed 110) The surface is opened to the Fabry-Perot resonator surface, and the In
GaAsP BH-LD is produced.

第4図はこのようにして製作した本発明の実施例の斜視
図である5図中402は例えば1.3μm波長組成のI
 n 6.7 (1()a 6 、@・AS・、ssP
・、ss活性層。
FIG. 4 is a perspective view of the embodiment of the present invention manufactured in this way. In FIG. 5, 402 is an I
n 6.7 (1()a 6 , @・AS・,ssP
・, ss active layer.

403はp−InPクラッド層であり、n−Inpt<
ッファ層409にp−InP不純物拡散層404−あら
かじめ設けられている。405はn−InP 電流ブロ
ック層でアリ、図かられかるようにメサ上部を除いた部
分に成長している。406,407はそれぞれp−In
PJlめ込み層、 n−GaInAsP キャップで1
りn、選択Zn拡散層408tメサ上部のみp−InP
埋め込み層406に達する7ように形成することにより
、電流はIn・、7・Ga・、HAS・、・SP・、a
m活性層402部分のみに有効に流れることになる。電
流ブロック層となるp形不純物拡散層404とn−In
P=電流ブロック層405のp −n接合は活性層40
2の真横に形成されており、これはInGaAsP B
H−LD  のもれ電流の防止に特に有効である。ま九
メルトバック法を用いることにより2回目のエピタキシ
ャル成長時におこる熱ダメージの影響も少なく、高い信
頼性が期待できル、仁のInGaAsP BH−LD 
 K9儒を正1口側を負とするバイアス電圧を加えると
活性層4020部分はpn接合の順バイアスであるため
この領域で発光再結合が生じるが、その他の領域は大部
分がpnpn接合となるため負性抵抗特性を示し、ター
ンオン電圧以下では電流がほとんど流れない。
403 is a p-InP cladding layer, and n-Inpt<
A p-InP impurity diffusion layer 404 is provided in the buffer layer 409 in advance. Reference numeral 405 denotes an n-InP current blocking layer, which grows in the area excluding the upper part of the mesa, as shown in the figure. 406 and 407 are respectively p-In
PJl embedded layer, 1 with n-GaInAsP cap
Selective Zn diffusion layer 408t p-InP only on top of mesa
By forming the layer 7 to reach the buried layer 406, the current flows through In・, 7・Ga・, HAS・, ・SP・, a
It effectively flows only to the m active layer 402 portion. The p-type impurity diffusion layer 404 and n-In which become the current blocking layer
P=p-n junction of current blocking layer 405 is active layer 40
2, and this is InGaAsP B
This is particularly effective in preventing leakage current of H-LD. By using the melt-back method, there is less influence of thermal damage during the second epitaxial growth, and high reliability can be expected.
When applying a bias voltage that makes the positive side of K9 negative negative, the active layer 4020 part is forward biased as a pn junction, so radiative recombination occurs in this region, but most of the other regions become pnpn junctions. Therefore, it exhibits negative resistance characteristics, and almost no current flows below the turn-on voltage.

したがって電流は活性層402に集中して流れるため2
0mA 程度の低い発振しきい値電流が得られた9本発
明の製造方法においては活性層402よりも深く形成す
るp形不純物の選択拡散、および選択拡散保護マスクを
用いてInGaAsP活性層表面までを選択エツチング
して活性層をメルトバックしたのちメサ上部以外に電流
プロ、り層が自動的に確実に形成されるためBH−LD
におけるもれ電流が低減され、さらに2回目のエピタキ
シャル成長時に導入される熱ダメージ層を除去すること
ができ、したがって発振しきい値電流の温度特性のすぐ
れた。かつ信頼性の高いBH−LDが再現性曳く得られ
た。
Therefore, since the current flows concentratedly in the active layer 402, 2
9 In the manufacturing method of the present invention, in which a low oscillation threshold current of about 0 mA was obtained, p-type impurity is selectively diffused to be formed deeper than the active layer 402, and a selective diffusion protection mask is used to diffuse the p-type impurity to the surface of the InGaAsP active layer. After selectively etching and melting back the active layer, a current layer is automatically and reliably formed in areas other than the top of the mesa, resulting in BH-LD.
The leakage current in the oscillation threshold current is reduced, and the thermally damaged layer introduced during the second epitaxial growth can be removed, resulting in excellent temperature characteristics of the oscillation threshold current. Moreover, a highly reliable BH-LD was obtained with good reproducibility.

本発明の実施例では活性層として1.3μmの組、成の
Iflo、tsGae、ssAle、ashs、ss 
k用いているが。
In the embodiment of the present invention, the active layer is made of Iflo, tsGae, ssAle, ashs, ss with a thickness of 1.3 μm.
I am using k.

これに限定されることな(InP基板に格子整合LりI
n1−x GaxAsl−y py混晶(0<x<1゜
oくyく1)の発光波長範囲として1.1μmから1.
7μmの間のどの波長の結晶であってもかまわない、ま
要電流ブロック層としてn−InP層(x’=0.  
y’=1)t−用いたが、この層は活性層に電流金集中
させるという機能をもてばよいので活性層よりもエネル
ギーギャップの大きなn形Inx−X’Ga X/ A
s 1 ++ y P yI層、すなわち活性層In1
−xGaxAs   Pに対してOくxj<x、y<、
y’くit−満−77 たすようなn形I n 1 ++X/ Ga x’ A
 I 1−y’ P y1層、あるいは半絶縁性のI 
n 1−xl Ga z’ As l−y’ P y’
層でありてもさしつかえない、p形InPjJlめ込み
層は活性層のエネルギーギャップとは無関係にp形11
mm−xj GaxyAsl−y* P、#  (0〉
x“<1゜0<y”く1)層を用いてもさしつかえない
This is not limited to (lattice matching L I to InP substrate)
The emission wavelength range of the n1-x GaxAsl-y py mixed crystal (0<x<1° x 1) is from 1.1 μm to 1.
It does not matter if the crystal has any wavelength between 7 μm, and an n-InP layer (x'=0.
y'=1)t- was used, but this layer only needs to have the function of concentrating the current gold in the active layer, so n-type Inx-X'Ga X/A, which has a larger energy gap than the active layer, is used.
s 1 ++ y P yI layer, that is, active layer In1
−xGaxAs For P, O xj<x, y<,
y'kuit-man-77 n-type I n 1 ++X/ Ga x' A
I 1-y' P y1 layer or semi-insulating I
n 1-xl Gaz' As ly' P y'
The p-type InPjJl embedded layer can be a p-type 11 layer regardless of the energy gap of the active layer.
mm-xj GalaxyAsl-y* P, # (0>
x"<1°0<y" (1) A layer may be used.

本発明はfnGaAsP BH−LD  のもれ電流上
防止するための電流ブロック層が再現性よく得られる製
造方法であり、InGaAsP BH−LD  O製作
歩留りが大幅に向上でき丸さらに2度目のエピタキシャ
ル成長時に導入される活性層の熱ダメージの影響が小さ
くできるため、信頼性の高いInGaAsPBH−LD
が再現性よく得られるという特徴を有する。
The present invention is a manufacturing method that can obtain a current blocking layer for preventing leakage current of fnGaAsP BH-LD with good reproducibility, and the production yield of InGaAsP BH-LDO can be greatly improved. InGaAsPBH-LD is highly reliable because the effect of thermal damage on the active layer can be reduced.
can be obtained with good reproducibility.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例のInGaAsP BH−LDの斜視図
、第2図はメルトバック法により埋め込み活性層ストラ
イプを形成する場合の形状を示す図、第3図は本発明に
よる製造方法管示すための断面図、第4図は本発明の実
施例の斜視図である。 図中101はH−InP基板、102はn−InPバ、
ファ層% 103はInGaAsP活性層、104はp
−InPクラッド層、105はp−GaInAsP 電
極層、106はp−InP電流ブロック層、107はn
−InP電流ブロック層、108はn−InGaAsP
1゜109は8i0.膜、110はp形オーミック電極
。 111はn形オーミック電極、201はInP基板。 202はInGaAsP層、203はInPメサストラ
イプ、204はメルトバック後InPメサストライプ下
部のみに残されfcInGaAsP層、303はIn0
.7゜Ga 00sOAs o、ss re、as活性
層、305は選択拡散保護マスク、306はp形不純物
拡散層。 307はp−InP メサストライプ、308はIn(
1,7゜Ga0jIムS @、45 P O,li活性
層、31Oはp−InP  埋め込み層、311はn−
Ga I nAs Pキaryプ層。 312はZn拡散層、313はAu Znnオーツり電
極、314はAuGe−Ni オーミy 9WAIL 
402はI”0jOG”0.IOA”0jiP1.IM
活性層、4o4はp形不純物拡散層24o5はn−In
P電流プロ、り層で第1図 /10 2σ子
FIG. 1 is a perspective view of a conventional InGaAsP BH-LD, FIG. 2 is a diagram showing the shape of buried active layer stripes formed by the melt-back method, and FIG. 3 is a diagram showing the manufacturing method according to the present invention. The sectional view, FIG. 4, is a perspective view of an embodiment of the invention. In the figure, 101 is an H-InP substrate, 102 is an n-InP substrate,
Far layer% 103 is InGaAsP active layer, 104 is p
-InP cladding layer, 105 is p-GaInAsP electrode layer, 106 is p-InP current blocking layer, 107 is n
-InP current blocking layer, 108 is n-InGaAsP
1°109 is 8i0. 110 is a p-type ohmic electrode. 111 is an n-type ohmic electrode, and 201 is an InP substrate. 202 is an InGaAsP layer, 203 is an InP mesa stripe, 204 is an fcInGaAsP layer left only at the bottom of the InP mesa stripe after meltback, and 303 is an In0
.. 7°Ga 00sOAs o, ss re, as active layer, 305 is a selective diffusion protection mask, and 306 is a p-type impurity diffusion layer. 307 is p-InP mesa stripe, 308 is In(
1,7゜Ga0jImuS@, 45 PO,li active layer, 31O is p-InP buried layer, 311 is n-
GaInAsP cap layer. 312 is a Zn diffusion layer, 313 is an Au Znn automatic electrode, 314 is an AuGe-Ni 9WAIL
402 is I"0jOG"0. IOA”0jiP1.IM
The active layer 4o4 is a p-type impurity diffusion layer 24o5 is n-In
P current pro, Figure 1/10 2σ in layer

Claims (1)

【特許請求の範囲】 面方位が(100L Toるいは(100)近傍である
allの導電形のInP基板に少くともInニーXGa
x As1−yPy (0<x<1.0<y<1 )活
性層を含む半導体層を積層させた多層膜構造ウエファノ
表面K<011> 方向に沿ったストライプ状の拡散保
護マスクを形成した後、第2の導電形不純物を前記I’
m−x GaxAs□−アP、活性層よりも深く選択拡
散する工程と1選択拡散され九p形不純物領域の一部ま
たは全部を前記I n 1−8GaxA、1−アPy活
性層表面まで選択エツチングして<011>方向に平行
なメサストライプを形成する工程と、前記メサストライ
プ以外の部分の前記In1−1GaxAS   P  
活性層をメルト1−F   T バククさせた後前記メサストライプの上面のみt除イテ
前記に1の導電形のIn l、/ Gaxt As 1
−ytP y/(0<x’ < x t Y < Y’
 <1 )電流ブロック層を積層させ、さらに前記第2
の導電形の”−1−x’Gax#A”i −y” Py
’ 111め込み層を全面にわたって連続して積層させ
るエピタキシャル成長工程とを含むことを特徴とする埋
め込みへテロ構造半導体レーザの製造方法。
[Claims] At least In knee
x As1-yPy (0<x<1.0<y<1) After forming a stripe-shaped diffusion protection mask along the K<011> direction on the surface of the wafer, which has a multilayer film structure in which semiconductor layers including an active layer are laminated. , the second conductivity type impurity is I'
A step of selectively diffusing m-x GaxAs□-AP deeper than the active layer and selectively diffusing part or all of the p-type impurity region to the surface of the In 1-8GaxA, 1-APy active layer. etching to form mesa stripes parallel to the <011>direction;
After melting the active layer 1-F T , only the upper surface of the mesa stripe is removed by t.
−ytP y/(0<x'<xtY<Y'
<1) A current blocking layer is laminated, and the second
"-1-x'Gax#A"i -y" Py of conductivity type
1. A method for manufacturing a buried heterostructure semiconductor laser, comprising: an epitaxial growth step of continuously laminating a 111 embedded layer over the entire surface.
JP10968881A 1981-07-14 1981-07-14 Manufacture of semiconductor laser having embedded heterogeneous structure Granted JPS5810884A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10968881A JPS5810884A (en) 1981-07-14 1981-07-14 Manufacture of semiconductor laser having embedded heterogeneous structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10968881A JPS5810884A (en) 1981-07-14 1981-07-14 Manufacture of semiconductor laser having embedded heterogeneous structure

Publications (2)

Publication Number Publication Date
JPS5810884A true JPS5810884A (en) 1983-01-21
JPS6248919B2 JPS6248919B2 (en) 1987-10-16

Family

ID=14516664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10968881A Granted JPS5810884A (en) 1981-07-14 1981-07-14 Manufacture of semiconductor laser having embedded heterogeneous structure

Country Status (1)

Country Link
JP (1) JPS5810884A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4948753A (en) * 1984-03-27 1990-08-14 Matsushita Electric Industrial Co., Ltd. Method of producing stripe-structure semiconductor laser
US5028563A (en) * 1989-02-24 1991-07-02 Laser Photonics, Inc. Method for making low tuning rate single mode PbTe/PbEuSeTe buried heterostructure tunable diode lasers and arrays
US5119388A (en) * 1989-02-24 1992-06-02 Laser Photonics, Inc. Low tuning rate PbTe/PbEuSeTe buried quantum well tunable diode lasers and arrays
JPH0557922U (en) * 1991-12-26 1993-07-30 日本ビクター株式会社 Power amplifier drive circuit
EP0610777A1 (en) * 1993-02-12 1994-08-17 ALCATEL ITALIA S.p.A. Semiconductor laser with low threshold current and related manufacturing process

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4948753A (en) * 1984-03-27 1990-08-14 Matsushita Electric Industrial Co., Ltd. Method of producing stripe-structure semiconductor laser
US5028563A (en) * 1989-02-24 1991-07-02 Laser Photonics, Inc. Method for making low tuning rate single mode PbTe/PbEuSeTe buried heterostructure tunable diode lasers and arrays
US5119388A (en) * 1989-02-24 1992-06-02 Laser Photonics, Inc. Low tuning rate PbTe/PbEuSeTe buried quantum well tunable diode lasers and arrays
JPH0557922U (en) * 1991-12-26 1993-07-30 日本ビクター株式会社 Power amplifier drive circuit
EP0610777A1 (en) * 1993-02-12 1994-08-17 ALCATEL ITALIA S.p.A. Semiconductor laser with low threshold current and related manufacturing process
US5504769A (en) * 1993-02-12 1996-04-02 Alcatel Italia S.P.A. Semiconductor laser having low current threshold

Also Published As

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