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JPS57133642A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS57133642A
JPS57133642A JP1921381A JP1921381A JPS57133642A JP S57133642 A JPS57133642 A JP S57133642A JP 1921381 A JP1921381 A JP 1921381A JP 1921381 A JP1921381 A JP 1921381A JP S57133642 A JPS57133642 A JP S57133642A
Authority
JP
Japan
Prior art keywords
layer
atom
density
type
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1921381A
Other languages
Japanese (ja)
Inventor
Masaaki Ohira
Tadashi Daimon
Koichiro Takahata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1921381A priority Critical patent/JPS57133642A/en
Publication of JPS57133642A publication Critical patent/JPS57133642A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To increase the adhesive strength for the case located on the reverse side by a method wherein, at the same time when the diffusion process for high density impurity is performed on the surface, photoetching is performed on the semiconductor wafer having a high density diffusion layer of 10<20>atom/cm<3> generated on the back side, and the density of the back side is reduced to 10<20>atom/ cm<3> or below. CONSTITUTION:A P type base layer 3 is formed by diffusion on the N<-> type epitaxial layer 2 which was surrounded by an SiO2 film 8 to be used for insulation isolation, an N<+> type emitter layer 4 and an N<+> type collector contact layer 5 are provided in the base layer 3 and an NPN transistor, having a layer 2 as a collector, is constituted. Then, the reverse side of a semiconductor chip 20 is fixed by adhesion on the bottom face of the case, but as the impurity density of the N<+> diffusion layer 6, located on the reverse side of a P type substrate 1, generated when the layers 4 and 5 were formed, is 10<20>atom/cm<3> or above, no excellent adhesive strength is obtained. Therefore, the impurities are removed until the surface having 10<20>atom/cm<3> or below is exposed by performing photoetching on the layer 6, and the adhesive strength is increased by reducing the density of impurities.
JP1921381A 1981-02-12 1981-02-12 Semiconductor device and manufacture thereof Pending JPS57133642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1921381A JPS57133642A (en) 1981-02-12 1981-02-12 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1921381A JPS57133642A (en) 1981-02-12 1981-02-12 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS57133642A true JPS57133642A (en) 1982-08-18

Family

ID=11993087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1921381A Pending JPS57133642A (en) 1981-02-12 1981-02-12 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS57133642A (en)

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