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JPS5687142A - Sequence control system for rom address - Google Patents

Sequence control system for rom address

Info

Publication number
JPS5687142A
JPS5687142A JP16502979A JP16502979A JPS5687142A JP S5687142 A JPS5687142 A JP S5687142A JP 16502979 A JP16502979 A JP 16502979A JP 16502979 A JP16502979 A JP 16502979A JP S5687142 A JPS5687142 A JP S5687142A
Authority
JP
Japan
Prior art keywords
address
branch
information
written
multiplex
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16502979A
Other languages
Japanese (ja)
Other versions
JPS586970B2 (en
Inventor
Sadao Nakao
Tadashi Hanada
Akihiro Maruo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54165029A priority Critical patent/JPS586970B2/en
Publication of JPS5687142A publication Critical patent/JPS5687142A/en
Publication of JPS586970B2 publication Critical patent/JPS586970B2/en
Expired legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To ensure a highly efficient execution for the data process to the address information with multiplex branch when the multiplex branch address is read out, by giving a control so as to secure an access for the address of the instruction which is directly required.
CONSTITUTION: Both the address information and the branch address selection information which designates the multiplex branch address are stored in the ROM1, and the function to select the destination of the multiplex branch address is given to the branch address selection information. The address information for access is written into the ROM1 after partitioned into several devices. At the same time, the address register 2 containing the written address destination is provided along with the decoder 5 which decodes the branch address selection information of the ROM1. Then the output of the decoder 5 is applied to the next ROM address control circuit 4, and the address to be written into the register 2 is turned into the address relating the address written into the register 2 in accordance with the output of the decoder 5 or into the address obtained by combining the divided address information through a selection. Thus a direct access is possible for the address of the required instruction.
COPYRIGHT: (C)1981,JPO&Japio
JP54165029A 1979-12-19 1979-12-19 ROM address sequence control method Expired JPS586970B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54165029A JPS586970B2 (en) 1979-12-19 1979-12-19 ROM address sequence control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54165029A JPS586970B2 (en) 1979-12-19 1979-12-19 ROM address sequence control method

Publications (2)

Publication Number Publication Date
JPS5687142A true JPS5687142A (en) 1981-07-15
JPS586970B2 JPS586970B2 (en) 1983-02-07

Family

ID=15804481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54165029A Expired JPS586970B2 (en) 1979-12-19 1979-12-19 ROM address sequence control method

Country Status (1)

Country Link
JP (1) JPS586970B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60112143A (en) * 1983-11-22 1985-06-18 Nec Ic Microcomput Syst Ltd Rom specifying next address
JPS6282402A (en) * 1985-10-07 1987-04-15 Toshiba Corp Sequence controller
JPS6444508A (en) * 1987-08-12 1989-02-16 Hitachi Ltd Sequence controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49103548A (en) * 1973-02-05 1974-10-01
JPS5058960A (en) * 1973-09-25 1975-05-22

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49103548A (en) * 1973-02-05 1974-10-01
JPS5058960A (en) * 1973-09-25 1975-05-22

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60112143A (en) * 1983-11-22 1985-06-18 Nec Ic Microcomput Syst Ltd Rom specifying next address
JPS6359173B2 (en) * 1983-11-22 1988-11-18
JPS6282402A (en) * 1985-10-07 1987-04-15 Toshiba Corp Sequence controller
JPS6444508A (en) * 1987-08-12 1989-02-16 Hitachi Ltd Sequence controller

Also Published As

Publication number Publication date
JPS586970B2 (en) 1983-02-07

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