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JPS5578365A - Memory control unit - Google Patents

Memory control unit

Info

Publication number
JPS5578365A
JPS5578365A JP15253378A JP15253378A JPS5578365A JP S5578365 A JPS5578365 A JP S5578365A JP 15253378 A JP15253378 A JP 15253378A JP 15253378 A JP15253378 A JP 15253378A JP S5578365 A JPS5578365 A JP S5578365A
Authority
JP
Japan
Prior art keywords
memory
information
timing
register
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15253378A
Other languages
Japanese (ja)
Inventor
Itaru Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15253378A priority Critical patent/JPS5578365A/en
Publication of JPS5578365A publication Critical patent/JPS5578365A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve system performance and reliability by providing a storage means which stores performance information indicating the access time of a memory and the transfer speed of signals and generating an interface timing for the memory.
CONSTITUTION: Memory interface control part 100 which controls the timing to memory MEM is provided, and this control part 100 is provided with read information and write information registers 102 and 103, address information register 105 and request information register 106. Interface timing information holding circuit 103 for the memory where addresses given from the external ar inputted through register 105 and decoder 107 is provided, and performance information such as the access time and the transfer speed of signals are stored in performance information holding circuit 202 of this circuit 103, and the interface timing for memory MEM is generated by memory interface control circuit 104, thus improving system performance and reliability.
COPYRIGHT: (C)1980,JPO&Japio
JP15253378A 1978-12-08 1978-12-08 Memory control unit Pending JPS5578365A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15253378A JPS5578365A (en) 1978-12-08 1978-12-08 Memory control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15253378A JPS5578365A (en) 1978-12-08 1978-12-08 Memory control unit

Publications (1)

Publication Number Publication Date
JPS5578365A true JPS5578365A (en) 1980-06-12

Family

ID=15542512

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15253378A Pending JPS5578365A (en) 1978-12-08 1978-12-08 Memory control unit

Country Status (1)

Country Link
JP (1) JPS5578365A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6168654A (en) * 1984-09-12 1986-04-09 Panafacom Ltd Memory control method
JPH0855077A (en) * 1994-05-17 1996-02-27 Lg Semicon Co Ltd Information use circuit
US5821996A (en) * 1988-10-27 1998-10-13 Canon Kabushiki Kaisha Solid-sate camera with solid-state memory for holding characteristic code representing characteristic of an internal circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6168654A (en) * 1984-09-12 1986-04-09 Panafacom Ltd Memory control method
US5821996A (en) * 1988-10-27 1998-10-13 Canon Kabushiki Kaisha Solid-sate camera with solid-state memory for holding characteristic code representing characteristic of an internal circuit
JPH0855077A (en) * 1994-05-17 1996-02-27 Lg Semicon Co Ltd Information use circuit

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