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JPS5682961A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5682961A
JPS5682961A JP16058779A JP16058779A JPS5682961A JP S5682961 A JPS5682961 A JP S5682961A JP 16058779 A JP16058779 A JP 16058779A JP 16058779 A JP16058779 A JP 16058779A JP S5682961 A JPS5682961 A JP S5682961A
Authority
JP
Japan
Prior art keywords
memory
stored
pieces
address information
memory control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16058779A
Other languages
Japanese (ja)
Inventor
Masahiro Kawakatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16058779A priority Critical patent/JPS5682961A/en
Publication of JPS5682961A publication Critical patent/JPS5682961A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable to exercise memory control with efficiency by entering two pieces of address information differing in memory address register access time and by selecting either for decoding.
CONSTITUTION: Memory 1 can be accessed at a high speed and is stored with a microprogram high in frequency of use. Memory 2, on the other hand, is a low- speed memory and stored with a microprogram other than that stored in memory 1. Further, two pieces of address information of memory 1 are entered in memory address register 3. Those pieces of address information include chip selection information, which is decoded by decoder 4, so that memory 1 or 2 will be selected with selective signal CSO or CSI sent as a result of the decoding operation. Thus, memory control can be exercised with efficiency.
COPYRIGHT: (C)1981,JPO&Japio
JP16058779A 1979-12-11 1979-12-11 Memory control system Pending JPS5682961A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16058779A JPS5682961A (en) 1979-12-11 1979-12-11 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16058779A JPS5682961A (en) 1979-12-11 1979-12-11 Memory control system

Publications (1)

Publication Number Publication Date
JPS5682961A true JPS5682961A (en) 1981-07-07

Family

ID=15718172

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16058779A Pending JPS5682961A (en) 1979-12-11 1979-12-11 Memory control system

Country Status (1)

Country Link
JP (1) JPS5682961A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6182184B1 (en) 1990-04-18 2001-01-30 Rambus Inc. Method of operating a memory device having a variable data input length
US6426916B2 (en) 1990-04-18 2002-07-30 Rambus Inc. Memory device having a variable data output length and a programmable register

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6182184B1 (en) 1990-04-18 2001-01-30 Rambus Inc. Method of operating a memory device having a variable data input length
US6260097B1 (en) 1990-04-18 2001-07-10 Rambus Method and apparatus for controlling a synchronous memory device
US6266285B1 (en) 1990-04-18 2001-07-24 Rambus Inc. Method of operating a memory device having write latency
US6314051B1 (en) 1990-04-18 2001-11-06 Rambus Inc. Memory device having write latency
US6378020B2 (en) 1990-04-18 2002-04-23 Rambus Inc. System having double data transfer rate and intergrated circuit therefor
US6415339B1 (en) 1990-04-18 2002-07-02 Rambus Inc. Memory device having a plurality of programmable internal registers and a delay time register
US6426916B2 (en) 1990-04-18 2002-07-30 Rambus Inc. Memory device having a variable data output length and a programmable register
US6570814B2 (en) 1990-04-18 2003-05-27 Rambus Inc. Integrated circuit device which outputs data after a latency period transpires
US6584037B2 (en) 1990-04-18 2003-06-24 Rambus Inc Memory device which samples data after an amount of time transpires

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