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JPS56162167A - Switching system for dual computers - Google Patents

Switching system for dual computers

Info

Publication number
JPS56162167A
JPS56162167A JP6390180A JP6390180A JPS56162167A JP S56162167 A JPS56162167 A JP S56162167A JP 6390180 A JP6390180 A JP 6390180A JP 6390180 A JP6390180 A JP 6390180A JP S56162167 A JPS56162167 A JP S56162167A
Authority
JP
Japan
Prior art keywords
input
busses
devices
computer
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6390180A
Other languages
Japanese (ja)
Other versions
JPS6321943B2 (en
Inventor
Yoshio Shionaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6390180A priority Critical patent/JPS56162167A/en
Publication of JPS56162167A publication Critical patent/JPS56162167A/en
Publication of JPS6321943B2 publication Critical patent/JPS6321943B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To avoid interruption of the processing of a main system to prevent troubles of the simultaneous use of input/output devices, by communicating the connection release and the connection state of input/output devices independently of service switching when service operation modes are switched. CONSTITUTION:A #1 computer 1 and a #2 computer 2 are systems independent of each other which do not include shared memories, and information exchange devices 14 and 15 for computers 1 and 2 are arranged on input/output busses 12 and 13 of respective systems to exchange control information between both systems. Input/output devices 16-19 which are shared and switched to be used by computers 1 and 2 are connected to busses 12 and 13 through input/output bus switching devices 20-23. A mode switching command is issued to busses 12 and 13 automatically or manually by a command device 24 connected to busses 12 and 13, and the mode state is displayed on an alarm circuit in the device 24 to give a desired warning to the operator. The computer 1 and the computer 2 are used as the master system and the slave system respectively to execute prescribed processings for every processing, thereby preventing the simultaneous use of devices 16-19 at the mode switching time.
JP6390180A 1980-05-16 1980-05-16 Switching system for dual computers Granted JPS56162167A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6390180A JPS56162167A (en) 1980-05-16 1980-05-16 Switching system for dual computers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6390180A JPS56162167A (en) 1980-05-16 1980-05-16 Switching system for dual computers

Publications (2)

Publication Number Publication Date
JPS56162167A true JPS56162167A (en) 1981-12-12
JPS6321943B2 JPS6321943B2 (en) 1988-05-10

Family

ID=13242674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6390180A Granted JPS56162167A (en) 1980-05-16 1980-05-16 Switching system for dual computers

Country Status (1)

Country Link
JP (1) JPS56162167A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63155354A (en) * 1986-12-19 1988-06-28 Nippon Telegr & Teleph Corp <Ntt> Route initialization system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0473199A (en) * 1990-07-13 1992-03-09 Sukegawa Electric Co Ltd Decorative panel and manufacture thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52139330A (en) * 1976-05-17 1977-11-21 Hitachi Ltd Urgent control system
JPS5462751A (en) * 1977-10-28 1979-05-21 Toshiba Corp Switching system for composite computer system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52139330A (en) * 1976-05-17 1977-11-21 Hitachi Ltd Urgent control system
JPS5462751A (en) * 1977-10-28 1979-05-21 Toshiba Corp Switching system for composite computer system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63155354A (en) * 1986-12-19 1988-06-28 Nippon Telegr & Teleph Corp <Ntt> Route initialization system
JP2795844B2 (en) * 1986-12-19 1998-09-10 日本電信電話株式会社 Route initialization method

Also Published As

Publication number Publication date
JPS6321943B2 (en) 1988-05-10

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