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GB1516559A - Multiprocessor system for a switching centre - Google Patents

Multiprocessor system for a switching centre

Info

Publication number
GB1516559A
GB1516559A GB2910876A GB2910876A GB1516559A GB 1516559 A GB1516559 A GB 1516559A GB 2910876 A GB2910876 A GB 2910876A GB 2910876 A GB2910876 A GB 2910876A GB 1516559 A GB1516559 A GB 1516559A
Authority
GB
United Kingdom
Prior art keywords
computer
memory
july
stand
computers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2910876A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Standard Electric Corp
Original Assignee
International Standard Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Standard Electric Corp filed Critical International Standard Electric Corp
Publication of GB1516559A publication Critical patent/GB1516559A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2048—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share neither address space nor persistent storage
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54508—Configuration, initialisation
    • H04Q3/54533—Configuration data, translation, passwords, databases
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/54558—Redundancy, stand-by
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Theoretical Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)

Abstract

1516559 SPC exchanges INTERNATIONAL STANDARD ELECTRIC CORP 13 July 1976 [22 July 1975] 29108/76 Heading H4K [Also in Division G4] A data-processing system for the real-time control of a switching system, e.g. a telephone exchange, wherein the two systems are interconnected by two transmission buses A & B, includes two active computers C1, C2 operating in a loadsharing mode and one stand-by computer CSB. Each computer has a memory M1-M3 and memory controller CM1-CM3, one input of each controller being connected to a respective interface unit DMA. Two program stores MM1, 2 are provided and each computer is linked to the other two computers through a link unit IPL. Should an active computer fail, the connecting arrangements SA/SB and S1/S2 function as follows (a) one of the transmission fuses is connected to the stand-by computer and (b) the program store previously connected to the memory of the failed computer is connected to memory M3.
GB2910876A 1975-07-22 1976-07-13 Multiprocessor system for a switching centre Expired GB1516559A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7522816A FR2319264A1 (en) 1975-07-22 1975-07-22 PERFECTED CONTROL SYSTEM OF SWITCHING EQUIPMENT

Publications (1)

Publication Number Publication Date
GB1516559A true GB1516559A (en) 1978-07-05

Family

ID=9158191

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2910876A Expired GB1516559A (en) 1975-07-22 1976-07-13 Multiprocessor system for a switching centre

Country Status (6)

Country Link
BE (1) BE844371R (en)
BR (1) BR7604678A (en)
DE (1) DE2632561B2 (en)
ES (1) ES450040A1 (en)
FR (1) FR2319264A1 (en)
GB (1) GB1516559A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2217487A (en) * 1988-04-13 1989-10-25 Yokogawa Electric Corp Dual computer system
GB2301464A (en) * 1995-05-19 1996-12-04 Compaq Computer Corp Multi-server fault tolerance using in-band signalling
US5822512A (en) * 1995-05-19 1998-10-13 Compaq Computer Corporartion Switching control in a fault tolerant system
GB2328352A (en) * 1997-08-12 1999-02-17 Lucent Technologies Uk Limited Redundant communication network
US6032271A (en) * 1996-06-05 2000-02-29 Compaq Computer Corporation Method and apparatus for identifying faulty devices in a computer system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT8003504A0 (en) * 1980-09-05 1980-09-05 Sits Soc It Telecom Siemens EQUIPMENT FOR THE MANAGEMENT OF AUXILIARY INFORMATION RELEVANT TO A CENTRAL CONTROL OF A PLURALITY OF PERIPHERAL USERS AND FOR THE DIAGNOSIS OF THE SAME CENTRAL CONTROL

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2217487A (en) * 1988-04-13 1989-10-25 Yokogawa Electric Corp Dual computer system
GB2217487B (en) * 1988-04-13 1992-09-23 Yokogawa Electric Corp Dual computer system
GB2301464A (en) * 1995-05-19 1996-12-04 Compaq Computer Corp Multi-server fault tolerance using in-band signalling
US5675723A (en) * 1995-05-19 1997-10-07 Compaq Computer Corporation Multi-server fault tolerance using in-band signalling
US5822512A (en) * 1995-05-19 1998-10-13 Compaq Computer Corporartion Switching control in a fault tolerant system
GB2301464B (en) * 1995-05-19 2000-04-26 Compaq Computer Corp Multi-server fault tolerance using in-band signalling
US6032271A (en) * 1996-06-05 2000-02-29 Compaq Computer Corporation Method and apparatus for identifying faulty devices in a computer system
GB2328352A (en) * 1997-08-12 1999-02-17 Lucent Technologies Uk Limited Redundant communication network

Also Published As

Publication number Publication date
BR7604678A (en) 1978-01-31
FR2319264A1 (en) 1977-02-18
BE844371R (en) 1977-01-24
ES450040A1 (en) 1977-07-16
DE2632561A1 (en) 1977-02-03
FR2319264B1 (en) 1982-04-02
DE2632561B2 (en) 1978-01-05

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee