JPS56104468A - Manufacture of mos semiconductor device - Google Patents
Manufacture of mos semiconductor deviceInfo
- Publication number
- JPS56104468A JPS56104468A JP584580A JP584580A JPS56104468A JP S56104468 A JPS56104468 A JP S56104468A JP 584580 A JP584580 A JP 584580A JP 584580 A JP584580 A JP 584580A JP S56104468 A JPS56104468 A JP S56104468A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxidation
- polycrystalline
- si3n4
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To flatten the surface of the MOS semiconductor device by covering the polycrystalline Si side surface exposed upon oxidation with an Si3N4 to thus prevent the oxidation of the polycrystalline Si side surface, precisely controlling the width and length of the gate and preventing the occurrence of the projection of the oxide film. CONSTITUTION:An SiO2 film 22, a polycrystalline film 23 containing impurity, an SiO2 film 24 and an Si3N4 film 25 are selectively formed on the Si substrate 21, boron is injected thereto, and an isolating region 27 is formed. An SiO2 film 28 is then formed by thermal oxidation, and the entire surface is covered with an Si3N4 film 29. The Si3N4 film is removed by a sputter etching or the like, and the film 25, 29 are retained only on the upper and side surfaces of the polycrystalline silicon. An isolating thick oxide film 30 is formed by thermal oxidation. Since the polycrystalline Si side surface is covered with the film 29, no lateral oxidation occurs, nor the projection of the oxide film occurred due to the oxidation of the side surface of the Si 23.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP584580A JPS56104468A (en) | 1980-01-23 | 1980-01-23 | Manufacture of mos semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP584580A JPS56104468A (en) | 1980-01-23 | 1980-01-23 | Manufacture of mos semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56104468A true JPS56104468A (en) | 1981-08-20 |
JPS6159675B2 JPS6159675B2 (en) | 1986-12-17 |
Family
ID=11622344
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP584580A Granted JPS56104468A (en) | 1980-01-23 | 1980-01-23 | Manufacture of mos semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56104468A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5840839A (en) * | 1981-09-04 | 1983-03-09 | Toshiba Corp | Manufacture of semiconductor device |
JPS6473772A (en) * | 1987-09-16 | 1989-03-20 | Nec Corp | Manufacture of semiconductor storage device |
JPH02230775A (en) * | 1989-03-02 | 1990-09-13 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS632778U (en) * | 1986-06-18 | 1988-01-09 |
-
1980
- 1980-01-23 JP JP584580A patent/JPS56104468A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5840839A (en) * | 1981-09-04 | 1983-03-09 | Toshiba Corp | Manufacture of semiconductor device |
JPS6473772A (en) * | 1987-09-16 | 1989-03-20 | Nec Corp | Manufacture of semiconductor storage device |
JPH02230775A (en) * | 1989-03-02 | 1990-09-13 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPS6159675B2 (en) | 1986-12-17 |
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